JPH03120748A - Lead frame - Google Patents

Abstract

PURPOSE:To reduce inductances of a power source connection part and ground part and to provide a lead frame in which the waveform of a high speed signal is not deteriorated by forming the connection part and the ground part as power source and ground planes, and arranging on the surface of a die pad and/or inner leads. CONSTITUTION:The power source plans 1 of a film pattern is formed by adhering a conductor foil 11 to the surface of a low dielectric constant resin film 12, and a land 13 made of a slit hole for connecting a ground plane 2 to a ground pin is formed at one end. A lead frame 3 has a die pad 31 and inner leads 32, the plane 2 is arranged on the pad 31 and the leads 32, and the plane 1 is arranged thereon. In this case, lands 23, 13 are brought into coincidence with ground pins 32c, lands 24, 14 are brought into coincidence with ground pin 32b, and slits 25, 15 are brought into coincidence with many signal pins 32a, 32a,....

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a lead frame for mounting a semiconductor element, and in particular to a lead used in a dual in-line package type semiconductor device having a guide pad on which a semiconductor element is assembled. It's about frames.

[Prior Art] Lead frames have conventionally been used to assemble semiconductors such as high-speed devices such as C-MOS that operate at high frequencies. A semiconductor device is formed by packaging a semiconductor pellet assembled with this lead frame.

As shown in FIG. 9, a conventional high-speed device package includes an outer lead (not shown) connected to an external circuit and an inner lead 0 connected to a semiconductor pellet 01.
There is one that uses a lead frame in which 2 is formed. As shown in the figure, this package is equipped with a base 03 made of alumina ceramics, a semiconductor pellet; The semiconductor pellet 01 and the inner lead 02 are bonded with a wire 05 made of A1 or the like, and in this state, a cap 06 made of alumina ceramics is sealed on the base 03 using a low melting point glass 07. DIP (Du
This is a hermetic type package, which is one of the types (In-Line Package).

In addition, as another package, a lead frame is used in which only the outer leads are formed, and the inner leads are printed on ceramics using a fine line conductor.
er-DIP) type.

Furthermore, there is also a type of package that uses a lead frame on which both inner leads and outer leads are formed and is sealed with plastic.

Recently, with the increase in the number of pins on LSIs, the above-mentioned DI
The P-type ceramic package has a multi-pin structure with a maximum of about 1,000 pins and is pancaged.
Also, a third-deep type package has a multi-pin structure of about 42 pins.

[Problem to be solved by the invention] By the way, when considering problems in connection and mounting of high-speed devices such as C-MOS, conventional mounting technology using bipolar transistors has problems due to insufficient characteristic impedance of wiring within the package. As a result, the signal transmission band becomes narrower. As a result, pulses with a fast rise and fall are subject to waveform distortion and attenuation, resulting in problems such as noise and trouble.

One factor of the noise voltage that causes this noise l/rub is the back electromotive voltage V emf generated by the inductance L of the power supply line that is the power supply connection part. This back electromotive force Ve
Since mf is proportional to the line inductance L and the speed (diet) when the current is turned off, it is expressed by the following equation.

That is, Vemf= −(d i / d t ) and C−M
The switching time of high-speed devices such as OSs is more than an order of magnitude faster than that of bipolar transistors, so if such high-speed devices are wired using the same connection method as bipolar transistors, back electromotive force that generates line inductance L will occur. The power consumption also increases by an order of magnitude or more.

Furthermore, in the case of a conventional DIP type package, as the number of pins 08 of the lead 02 increases, the power pin 09 and the ground pin (not shown, but almost the same shape as the power pin) are made of semiconductor pellets, as shown in Figure 10. Because it exists symmetrically with respect to
The length becomes longer. For this reason, the line inductance L of the power supply lead becomes extremely large, which is undesirable because malfunctions due to switching occur.

Therefore, in order to prevent malfunctions due to switching, it is necessary to either make the switching speed not faster than necessary or to wire the power supply line with low inductance in order to suppress the back electromotive force Vemf.

However, in order to achieve higher performance in devices, higher switching speeds are essential, so the best way to improve performance is to reduce the inductance of the power supply line to prevent device malfunctions. This is an appropriate measure.

Currently, as a countermeasure to this, the position of the power pin of the lead frame is set in the center of the package.
Measures have been taken to reduce the line inductance L. However, with this measure, the area covered with resin or ceramic after packaging becomes narrower, making it easier for moisture to enter from the power supply line, and corrosion of the LSI's power supply electrode pads. This is not recommended as a countermeasure.

On the other hand, when transmitting high-speed signals from one device to the next, a matching resistor with the same resistance value as the characteristic impedance of normal wiring is placed at the input terminal of the next device to prevent reflections. Measures are being taken. However, when a matching resistor is placed outside the package, there is a problem in that the presence of lead wiring and bonding wires inside the package results in an open stub, which causes deterioration of the transmission waveform.

The present invention has been made in view of such problems, and an object of the present invention is to provide a lead frame that can reduce the inductance of the power supply connection section and the ground section inside the package.

Another object of the present invention is to provide a lead frame that does not degrade the waveform of high-speed signals transmitted from one device to the next.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention uses a lead frame that includes at least an inner lead and a Gui pad on which a semiconductor pellet is mounted, and also has a power supply connection part and a ground part made of a plane. The present invention is characterized in that a power plane and a ground plane are formed together by structural members, and the power plane and the ground plane are disposed on the surface of the guide pad and/or the inner lead.

Moreover, the present invention forms the power plane and the ground plane in a laminated structure, and the power plane and the ground plane are made of two layers consisting of a conductive foil serving as a power connection part and a ground part, and a low dielectric constant resin film. Alternatively, it is characterized in that it is formed of a multilayer film, and a microstrip line is formed by a ground plane and an inner lead formed of these two or multilayer films.

[Function] In the lead frame according to the present invention having such a configuration, the power connection portion and the ground portion are formed as a power plane and a ground plane with a plane structure, so that the inductance of the power connection portion can be reduced and at the same time. The decoupling structure can suppress the bounce of the power supply voltage.

Further, since the ground plane and the signal pin of the inner lead form a microstrip line, a matching resistor is provided inside the package. This makes it possible to control the characteristic impedance inside the package and prevent deterioration of the transmission waveform.

[Example] Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows a film pattern disposed on a lead frame according to the present invention, and (a) is a plan view of an upper layer plane forming a power supply plane of the film pattern;
(b) is a cross-sectional view along the IBrB line in (a), (
c) is a top view of the lower plane forming the ground plane of the film pattern; (d) is the I in (c);
It is a sectional view along the D-ID line. In the figure, 1 is a power plane, 2 is a ground plane, 11.21 is a conductor foil,
12 and 22 are low dielectric constant resin films, 13.23 is a land portion for connecting the ground plane 2 and the ground pin of the lead frame, and 14.24 is 1 for connecting the power plane 1 and the power pin of the lead frame. The lands 15 and 25 are slits for wire bonding.

As shown in FIGS. 1A and 1B, a film pattern power plane 1 is formed by bonding a conductive foil 11 to the surface of a low dielectric constant resin film 12. As shown in FIGS. At one end of the conductive foil 11 and the conductive resin film 12, a land portion 13 consisting of a hole for connecting the ground plane 2 and the ground pin of the lead frame is formed.

In addition, these conductor foils 11 and low dielectric constant resin films 12
A land portion 14 consisting of a slit hole for connecting the power plane 1 and the power pin of the lead frame is formed at the other end of the lead frame.

The positions of these land portions 13 and 14 are not particularly limited, and one or more land portions 13 and 14 may be provided at any desired position of the film pattern.

Further, in the center of the conductor foil 11 and the low dielectric constant resin film 12, a large number of wire bonding wires 1-15 are provided in order to connect the electrode pads on the semiconductor pellet and the signal pins of the lead frame with metal wires. .15. ... is formed by punching. These slits 15, 15.・・・
・ is provided individually for each signal pin of the lead frame. Note that the slit holes 15 may be formed in a large shape so as to be connected to a series of regions where signal pins are present, so that one slit hole 15 corresponds to several signal pins.

Similarly, as shown in Figures (c) and (d), the ground plane 2 of the film pattern is a low dielectric constant resin film 2.
A conductive foil 21 is bonded to the surface of 2. These conductor foil 21 and low dielectric constant resin film 22 include
A land portion 23 similar to the power plane 1 described above.
24 and slit 25 are provided at the same position.

FIG. 2 is a partially exploded perspective view of a lead frame for a high-speed device formed by disposing a laminated film of a power plane 1 and a ground plane 2 on a lead frame with a die pad. In the figure, 3 is a lead frame, 31 is a die pad, 32 is an inner lead, 32a is a signal pin in the inner lead 32, 32b is a power pin in the inner lead 32, 32c is an inner lead 32
This is the ground pin.

As shown in FIG. 2, the lead frame 3 includes a die pad 31 and inner leads 32.

A ground plane 2 is provided on the surface of the die pad 31 and the surface of the inner leads 32 of this lead frame 3, and a power plane 1 is provided on the second side of the ground plane 2. In that case, the land portion 23.13 is connected to the ground pin 32.
In addition, the land portion 24°14 is connected to the power pin 32b, and the Surin 1-25.15 is connected to the numerous signal pins 32a,
32 a, . . . match each other.

Next, a method of connecting the power plane 1 and the ground plane 2 configured in this way to the @source pin 32b and the ground pin 32c of the lead frame 3 will be described.

FIG. 3 is a perspective view of each land portion 13, 23, 14, 24 of the power plane 1 and the ground plane 2.

As shown in FIG. 3(a), the connection method for connecting the power plane 1 and the power pin 32b of the lead frame 3 is as follows: 14 are provided with slit holes passing through them. A slit hole is also provided in the land portion 24 of the ground plane 2, but in this case, the slit hole 24a is formed in the conductor foil 21 and has a larger diameter than the slit hole in the land portion 14, and has a low dielectric potential. A slit hole 24b having approximately the same diameter as the slit hole 14 is provided in the land portion 24 of the resin film 22 on the same axis as the slit hole 24a. And both planes 1°20 land part 14.24
are matched to form a stepped structure, and connected to the power supply pin 32b of the inner lead 32 of the lead frame 3 by soldering or the like.

Similarly, the ground plane 2 and the ground pin 32c of the lead frame 3 are connected to the conductor foil 1 of the power plane 1.
A slit hole 13a with a relatively large diameter is formed in the land portion 13 of 1.
At the same time, a low dielectric constant film 120 land portion 1 is formed.
For 3, this suritsu! 5- A slit hole 13b having a smaller diameter than the slit hole 13a is formed coaxially with the slit hole 13a. -force, ground plane 2
A slit hole having the same diameter as the slit hole 13b is formed through the conductor foil 21 and the low dielectric constant resin film 22. Then, in the same manner as described above, the land portions 13.23 of both planes 1 and 2 are aligned, and connection between both planes 1.2 and the ground pin 32c of the lead frame 3 is made by soldering or the like.

FIG. 4 is a perspective view of the vicinity of the signal pin 32a of the lead frame 3 formed in this manner. Note that the power supply plane 1 is omitted for the sake of simplicity.

As shown in FIG. 4, the signal pin 32 of the lead frame 3
Of the regions where a, 32 a, ... and the conductor foil 21 and the low dielectric constant resin film 22 overlap, region B
is the connection area between the signal pin connection electrode pad (not shown) on the semiconductor pellet and the signal pin connection bonding post 328' of the lead frame 3, that is, the area where the slit hole 25 is formed; A region C existing outside B is a region C in which a microstrip line portion 4 constituted by the ground plane 2 and the signal pin 32a of the lead frame 3 is formed.

FIG. 5 shows a laminated structure of a power plane 1 made of a conductive foil 11 and a low dielectric constant film 12, a ground plane 2 made of a conductive foil 21 and a low dielectric constant film 22, and a signal pin 32a of a lead frame 3. FIG.

In FIG. 5, since the coupling with the power plane 1 is approximately ignored, the microstrip line section 4 is formed by the ground plane 2 and the inner lead 32 as described above. On the other hand, the conductor foil 21 constituting the ground plane 2 and the conductor foil 11 and low dielectric constant resin film 12 constituting the power supply plane 1 form a decoupling capacitor 5 that suppresses the bounce of the power supply voltage due to inductance generated in the power supply line. is formed. This decoupling capacitor 5 is electrically connected to the gate of the semiconductor chip as shown in FIG.

Note that L is the inductance of the inner lead 32.

Characteristic impedance Zl of microstrip line section 4
l is expressed by the following equation, where E is the relative dielectric constant of the low dielectric constant resin film 22, and W is the width of the signal pin 32a of the inner lead 32. That is, here, W-=W+a.ΔW.

As is clear from this equation, in a DIP package or the like where the frequency is high and the flat width W of the signal pin 32a in the inner lead 3 is relatively large, the low dielectric constant resin film 12 constituting the power plane 1 or the ground plane 2
．． The power plane 1 or the ground plane 2 must be made of a material having a small dielectric constant E of 22.

In that case, if the material constituting the ground plane has a dielectric constant of about 4.0, it is possible to form a capacitor with a decoupling function with a thickness of about 100 μm when placed in an actual package. 4. In the resin constituting the microstrip line, 4.
Since a resin having a dielectric constant of 0 or more causes too much delay and is not preferred in practice, the low dielectric constant resin film 12 has a dielectric constant E of approximately 4.00.
It is desirable that the low dielectric constant resin film 22 be formed of a material having a dielectric constant E of less than 4.00. In this way, the capacitance values C, C2 of each low dielectric constant resin film are controlled by the relative permittivity of the low dielectric constant resin films 12 and 22,
Controls the capacity of the capacitor.

+9= Further, the characteristic impedance Ze is set in consideration of all problems such as matching conditions with the characteristic impedance of the printed circuit board to be mounted, signal delay time inside the package, and noise. For example, from the relationship between the characteristic impedance of the printed circuit board and the signal delay time shown in Figure 7, the delay time due to the load of the signal source is suppressed as the characteristic impedance increases, but the delay due to the load increases as the characteristic impedance increases. Therefore, the characteristic impedance is 40
The optimum value is approximately 60Ω. On the other hand, from the relationship between the characteristic impedance of the printed circuit board and noise shown in Figure 8,
The higher the characteristic impedance setting value, the smaller the △ engineering noise caused by current fluctuations can be suppressed, but the higher the characteristic impedance, the thicker the cross stroke noise (because the characteristic impedance is 40 to 60 Ω).
degree is the optimal value. The characteristic impedance of the printed circuit board is normally set at 50Ω, so in order to prevent reflections from occurring at the junction between the package lead and the printed circuit board, the characteristic impedance Z is set over the entire package.
It is optimal that the setting value of B is also 50Ω.

Furthermore, in FIG. 5, the transmission speed V of the traveling wave, which is the signal in the signal pin 32a, is proportional to 1/i, so if the dielectric constant is high, the signal transmission speed will be delayed, so the dielectric constant High +) f 24 is not preferred. For example, a glass epoxy substrate (American 1i Acupuncture Industry Association standard: G-
10) or polyimide (trade name: Kapton or Corbilex), etc. can be used.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various design changes can be made.

For example, in the above-mentioned embodiment, only a DIP type package has been described, but the present invention can be applied to, for example, an S
MD (Surface Mount Device)
, Q F P (Quad Flat Package
), TQFP (ThinQuad Flat Pac
It can also be applied to packages such as

Further, in the above embodiment, the power plane 1 and the ground plane 2 are arranged so as to straddle both the die pad 31 and the inner lead 32. It is also possible to arrange it only in 32.

Further, although the power plane 1 and the ground plane 2 are made of two-layered films consisting of a conductive foil and a low dielectric constant resin film, they can also be formed into multi-layered films.

[Effects of the Invention] As is clear from the above explanation, the lead frame of the present invention has a brane structure for the power supply connection section and the grounding section, which reduces the system inductance and the bounce of the power supply voltage. You will be able to do this.

Furthermore, since the microstrip line is formed by the conductor foil and low dielectric constant resin film forming the ground plane and the signal pins of the lead frame, the characteristic impedance of the signal line inside the package can be controlled.

In addition, since the resin films used for the power and ground planes can be selected arbitrarily, delays in the package itself can be avoided, and high-speed device performance can be improved without compromising the performance of high-speed devices. You will get the package.

Furthermore, the plane structure of the power plane and the ground plane allows heat generated by elements and the like to be effectively transferred to the die pad, so that the die pad can be used as a heat sink. In particular, if the die pad is made of a copper-based material, the heat dissipation effect can be greatly increased.

[Brief explanation of the drawing]

FIG. 1 shows an example of a power plane and a ground plane used in a lead frame according to the present invention, (a)
is a plan view of the power plane, (b) is the I in (a)
(c) is a plan view of the ground plane; (d) is a cross-sectional view taken along the ID-ID line in (C); FIG. 2 is a partially exploded perspective view of this lead frame; Figure 3 shows a partially enlarged view of the power plane 23-- and the ground plane, (a)
(b) is a partial enlarged view of the connection part with the power pin, (b) is a partial enlargement view of the connection part with the ground pin, Figure 4 is a partial enlargement view of the overlapping part between the power plane and the signal pin of the lead frame, and Figure 5
The figure is a cross-sectional view along the V-v line in Figure 4, Figure 6 is a circuit diagram showing the principle of a decoupling capacitor, Figure 7 is a diagram showing the relationship between the characteristic impedance of the board and delay time, and Figure 8 is a diagram showing the relationship between the characteristic impedance of the board and the delay time. 9 is a cross-sectional view of a conventional hermetic type package, and FIG. 10 is a wiring diagram partially showing a printed conductor pattern of a dip type package. 1...Power plane, 2...Ground plane, 11,
21... Conductor foil, 12.22... Low dielectric constant resin film, 13, 14, 23.24... Land chick 1
5, 25...Slit L3-...Lead frame,
31...Die pad, 32...Inner lead, 3
2a...Signal pin, 32b...Power pin, 32
c...Ground pin, 4...24- microstrip line, 5...Decoupling capacitor

Claims (10)

[Claims] (1) In a lead frame that includes at least a die pad on which a semiconductor element is mounted and an inner lead that is electrically connected to the semiconductor element, the power connection part and the ground part are formed as a power plane and a ground plane, respectively, by members having a plane structure. A lead frame characterized in that the power plane and the ground plane are arranged on the surface of the die pad and/or the surface of the inner lead. (2) In a lead frame equipped with at least a die pad on which a semiconductor pellet is mounted and an inner lead, the power connection part and the ground part are respectively formed as a power plane and a ground plane by members of a plane structure, and these power plane and ground plane A lead frame characterized in that: is arranged on the peripheral edge of the surface of the die pad. (3) The lead frame according to claim 1 or 2, wherein the power plane and the ground plane have a laminated structure of conductive foil films based on a low dielectric constant resin film. (4) The power supply plane and the ground plane having a laminated structure are formed of a two-layer or multilayer film consisting of a conductor foil and a low dielectric constant resin film that constitute the power supply connection part and the ground part. The lead frame according to claim 3. (5) The lead frame according to claim 3, wherein a microstrip line is formed by the ground plane and the inner lead. (6) The lead frame according to claim 5, wherein a characteristic impedance of a microstrip line constituted by the ground plane and the inner lead is set to 40 to 60 Ω. (7) The ground plane forming the inner lead and the microstrip line has a relative permittivity that is the same as or smaller than the relative permittivity of the low permittivity resin film that constitutes the power supply plane. Claim 5 characterized in that it is formed of a low dielectric constant resin film.
Or the lead frame described in 6. (8) The low dielectric constant resin film constituting the power plane is formed of a material with a dielectric constant of approximately 4.0, and the low dielectric constant resin film constituting the ground plane has a dielectric constant of approximately 4.0. 8. The lead frame according to claim 7, wherein the lead frame is made of a material having a diameter smaller than .0. (9) The lead frame according to any one of claims 1 to 8, wherein a slit for connecting the semiconductor element and a signal pin of the inner lead is formed in the power plane and the ground plane. . (10) A claim characterized in that a hole is formed in the power supply plane and the ground plane for connecting the power supply connection part and/or the ground part to the power supply pin and/or ground pin of the inner lead. The lead frame according to any one of Items 1 to 8.