JPH03119735A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03119735A
JPH03119735A JP1255255A JP25525589A JPH03119735A JP H03119735 A JPH03119735 A JP H03119735A JP 1255255 A JP1255255 A JP 1255255A JP 25525589 A JP25525589 A JP 25525589A JP H03119735 A JPH03119735 A JP H03119735A
Authority
JP
Japan
Prior art keywords
bonding
film
bonded
laminated
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1255255A
Other languages
Japanese (ja)
Inventor
Mamoru Yasaka
守 家坂
Kumio Koorido
郡戸　久美男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1255255A priority Critical patent/JPH03119735A/en
Publication of JPH03119735A publication Critical patent/JPH03119735A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48455—Details of wedge bonds
    • H01L2224/48456—Shape
    • H01L2224/48458—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]

Abstract

PURPOSE:To make a continuity to a film to be bonded sure by a method wherein, in a semiconductor device of a structure where a bonding wire is bonded to the film to be bonded which is laminated on a semiconductor substrate via a substratum layer and to a bonding auxiliary layer to obtain a bonding strength, at least one part of the auxiliary layer is situated at the inside of a bonding face of the bonding wire. CONSTITUTION:A bonding wire 7 is bonded to a transparent electrode film 17; a voltage is applied to the film 17 from the outside via the wire. In a bonding structure which is bonded in this manner, a polycrystalline Si pedestal 24 which is covered with an SiO2 film 23 and an Al bonding pad 25 laminated on it are formed only inside an opening region 26 formed in a photoconductive film 16 in such a way that their height is nearly the same as the surface of the film 17. By this constitution, the pad 25 is not formed under the film 16; a difference in level is not formed in the film 16. Consequently, it is possible to prevent a disconnection at a stepped part of the film 17 laminated on the film 16; an electrical. continuity of the film 17 becomes sure.

Description

【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は、回路要素が積層されている半導体装置に関
し、特にボンディングの接合構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device in which circuit elements are stacked, and particularly relates to an improvement in a bonding structure.

（従来の技術） 積層型の半導体装置、例えばＣＯＤ　（電荷結合デバイ
ス）が形成された半導体基板に光導電膜及びこの光導電
膜上に透明電極膜を積層形成したような固体撮像装置に
あっては、最上層の電極膜に外部から電圧を印加するた
めに、基板上に形成されたボンディング・パッドと電極
膜を電気的に接続する必要がある。(Prior Art) In a stacked semiconductor device, for example, a solid-state imaging device in which a photoconductive film is stacked on a semiconductor substrate on which a COD (charge-coupled device) is formed, and a transparent electrode film is stacked on the photoconductive film. In order to externally apply a voltage to the uppermost electrode film, it is necessary to electrically connect the bonding pad formed on the substrate and the electrode film.

この接続方法としては、ボンディング・ワイヤを用いて
行なう方法がある。As a method for this connection, there is a method using a bonding wire.

しかしながら、電極膜へのボンディング・ワイヤの直接
ボンディングでは、例えば超音波ボンディング法を用い
た場合には、十分なボンディング強度が得られない、ま
た、ネールヘッド法を用いた場合には、基板温度を高温
にするため、電極膜下の光導電膜の膜質が劣化してしま
う。However, direct bonding of the bonding wire to the electrode film does not provide sufficient bonding strength, for example when using the ultrasonic bonding method, and when using the nail head method, the substrate temperature Due to the high temperature, the quality of the photoconductive film under the electrode film deteriorates.

一方、ボンディング・ワイヤにＡｕ線を用いた場合には
、基板を高温に保持することなく十分な強度が得られる
が、Ａｕ４Ｊの延伸性により周辺をモード等で固定しな
いと短絡故障が発生し易くなる。On the other hand, when Au wire is used as the bonding wire, sufficient strength can be obtained without holding the board at high temperatures, but due to the stretchability of Au4J, short circuit failures are likely to occur unless the periphery is fixed in mode etc. Become.

また、電極膜上に予めＡｅ膜により、ボンディング・パ
ッドを形成することも考えられるが、ポンディングパッ
ドに接合強度を与えるために加熱が必要となるため、上
述したと同様に膜質劣化が生じる。It is also conceivable to form a bonding pad in advance with an Ae film on the electrode film, but heating is required to impart bonding strength to the bonding pad, resulting in film quality deterioration as described above.

さらに、電極膜下の光導電膜は通常２μｍ〜５μｍ程度
の厚さを必要とするため、基板上のポンディングパッド
と＠極膜とをボンディング・ワイヤで直接接続すること
は極めて困難となる。Furthermore, since the photoconductive film under the electrode film usually requires a thickness of about 2 μm to 5 μm, it is extremely difficult to directly connect the bonding pad on the substrate and the @electrode film with a bonding wire.

そこで、このような不具合を解消する方法としては、特
開昭６１−８２４４０号公報に示されているような方法
がある。Therefore, as a method for solving such problems, there is a method as disclosed in Japanese Patent Laid-Open No. 61-82440.

第４図（ａ）は上記特開昭６１−８２４４０号公報に記
載された発明におけ実施例の固体撮像装置の要部断面構
造図である。なお、第４図（ｂ）は同図（ａ）の平面図
であり、同図（ｂ）の■−■断面が同図（ａ）である。FIG. 4(a) is a sectional structural view of a main part of a solid-state imaging device according to an embodiment of the invention described in the above-mentioned Japanese Patent Laid-Open No. 61-82440. Note that FIG. 4(b) is a plan view of FIG. 4(a), and the cross section taken along the line ■-■ in FIG. 4(b) is FIG. 4(a).

第４図において、半導体基板上に形成された絶縁Ｍ１上
には、表面が酸化膜２で被覆されたポリシリコンからな
る台座３の上部において凸状となるＡ４のボンディング
・パッド４が形成されている。また、基板１にはａ−３
ｉＨ（アモルファスシリコン）膜からなる光導電Ｍ５が
、ボンディング・パッド４の凸部が開口されて形成され
ている。In FIG. 4, an A4-sized bonding pad 4 having a convex shape is formed on the top of a pedestal 3 made of polysilicon whose surface is covered with an oxide film 2 on an insulator M1 formed on a semiconductor substrate. There is. Also, the board 1 has a-3
A photoconductive layer M5 made of an iH (amorphous silicon) film is formed by opening the convex portion of the bonding pad 4. As shown in FIG.

この光導ｔＭ５の上には、ＩＴＯＪｌｊからなる透明電
極膜６が積層形成されている。ここで、台座３によるボ
ンディング・パッド４の段差は２μｍ程度とし、光導電
膜５の厚さは２〜３μｍ程度とする。これにより、光導
電ＪＩｉ５と電極膜６との開口部に、ボンディング・パ
ッド４の凸部表面が電極膜６の表面よりも僅かに低い露
出状態が得られる。A transparent electrode film 6 made of ITOJlj is laminated on the light guide tM5. Here, the level difference of the bonding pad 4 due to the pedestal 3 is about 2 μm, and the thickness of the photoconductive film 5 is about 2 to 3 μm. As a result, the surface of the convex portion of the bonding pad 4 is exposed at a slightly lower level than the surface of the electrode film 6 in the opening between the photoconductive JIi 5 and the electrode film 6.

このような状態において、ボンディング・パッドの露出
した凸部表面と電８ｉｉ膜６の双方にボンディング・ワ
イヤ７を例えば超音波ボンディング法により接合させる
。In this state, the bonding wire 7 is bonded to both the exposed convex surface of the bonding pad and the electrode 8ii film 6 by, for example, an ultrasonic bonding method.

このような接合方法にあっては、ボンディング強度はボ
ンディング・パッド４にボンディング・ワイヤ７を接合
することにより得られるので、上記した不具合は解消さ
れる。In such a bonding method, the bonding strength is obtained by bonding the bonding wire 7 to the bonding pad 4, so the above-mentioned problems are solved.

しかしながら、このような接合方法にあっては、第４図
（ａ）に示す点線の部分８で示すように、すなわちボン
ディング・パッド４の周縁部上において、ボンディング
・パッド４の周縁部の段差により、光導電膜５に急峻な
段差が生じる。このため、この段差部で光導電膜５より
もかなり薄く形成された電極膜６に段切れが発生する。However, in such a bonding method, as shown by the dotted line portion 8 in FIG. , a steep step occurs in the photoconductive film 5. Therefore, a step break occurs in the electrode film 6, which is formed much thinner than the photoconductive film 5, at this step portion.

このような段切れは、ボンディング・パッド４の周縁、
すなわち第４図（ｂ）に示す斜線内外の境界において発
生する。このため、第４図（ｂ）に示す斜線の内側の電
ｔｉｆｌ膜６と、斜線の外側の電極膜６とは境界部分で
分離されてしまう、したがって、ボンディング・ワイヤ
７とｔ　ｉ＃ＩＷ！Ａ　６との接合部（第４図（ｂ）に
交斜線で示す）は、斜線内の電極膜６上にあるため、斜
線外の電極膜６への電気導通が行なわれなくなる。この
ため、信号電荷が得られなくなったり、残像焼きつき特
性の劣化を招き画像欠陥を引き起こすことになる。Such a break occurs at the periphery of the bonding pad 4,
That is, it occurs at the boundaries inside and outside the diagonal lines shown in FIG. 4(b). For this reason, the electrode tifl film 6 inside the diagonal line shown in FIG. 4(b) and the electrode film 6 outside the diagonal line are separated at the boundary. Therefore, the bonding wire 7 and the ti#IW! Since the junction with A 6 (indicated by cross-hatched lines in FIG. 4(b)) is on the electrode film 6 within the hatched area, electrical conduction to the electrode film 6 outside the hatched area is no longer established. For this reason, it becomes impossible to obtain signal charges, and the afterimage burn-in characteristic deteriorates, resulting in image defects.

このような電極膜６の段切れは、ボンディング・パッド
４や光導電膜５の膜厚に依存する。Such a break in the electrode film 6 depends on the thickness of the bonding pad 4 and the photoconductive film 5.

例えば、ボンディング・パッド４の膜厚を十分に薄くし
た場合には、光導電膜５に生じる段差は小さくなり、電
極膜６の段切れは防止できる。For example, when the film thickness of the bonding pad 4 is made sufficiently thin, the step difference that occurs in the photoconductive film 5 becomes small, and breakage of the electrode film 6 can be prevented.

しかしながら、ボンディング・パッド４は、装置の製造
工程の複雑化を避けるために、基板１上に形成される八
βによる配線と同一工程により形成するなめに、その膜
厚を薄くすることは困難となる。However, since the bonding pad 4 is formed in the same process as the 8β wiring formed on the substrate 1 in order to avoid complicating the manufacturing process of the device, it is difficult to reduce its film thickness. Become.

（発明が解決しようとする課題） 以上説明したように、光導電膜上に比較的薄く積層形成
された電ｆ！膜にボンディング・ワイヤを接合させる構
造において、ボンディング強度を確保するために設けら
れたボンディング・パッドの段差により、電極膜に段切
れが発生し、電極膜への電圧印加を確実に行なうことが
困難になるといった問題を招いていた。(Problems to be Solved by the Invention) As explained above, the electric f! In a structure in which a bonding wire is bonded to a film, the step of the bonding pad provided to ensure bonding strength causes a break in the electrode film, making it difficult to reliably apply voltage to the electrode film. This led to problems such as

そこで、この発明は、上記に鑑みてなされたものであり
、その目的とするところは、十分なボンディング強度を
有し、積層形成される被ボンディング膜にボンディング
・ワイヤを介して確実に電気導通できるボンディングワ
イヤの接合構造を有する半導体装置を提供することにあ
る。Therefore, the present invention has been made in view of the above, and its purpose is to have sufficient bonding strength and to ensure electrical conduction through bonding wires to bonding films that are laminated. An object of the present invention is to provide a semiconductor device having a bonding structure of bonding wires.

〔発明の構成〕[Structure of the invention]

（課題を解決するための手段） 上記目的を達成するために、半導体基板上に下地層を介
して積層された被ボンディング膜と、接合強度を得る接
合補助層とにボンディング線が接合された構造を有する
半導体装置において、この発明は、前記接合補助層の少
なくとも一部の周縁が、前記ボンディング線の接合面の
内側領域となるように前記接合補助層を形成して構成さ
れる。(Means for solving the problem) In order to achieve the above object, a structure in which a bonding line is bonded to a bonding target film laminated on a semiconductor substrate via a base layer and a bonding auxiliary layer for obtaining bonding strength. In the semiconductor device according to the present invention, the bonding auxiliary layer is formed such that at least a portion of the periphery of the bonding auxiliary layer is located inside a bonding surface of the bonding line.

（作用） 上記構成において、この発明は、接合強度を十分に得る
ための接合補助層に積層されていない部分の下地層に積
層された被ボンディング膜にボンディングワイヤを接合
させるようにしている。(Function) In the above configuration, the present invention is configured such that the bonding wire is bonded to the bonding target film laminated on the base layer in the portion not laminated on the bonding auxiliary layer in order to obtain sufficient bonding strength.

（実施例） 以下、図面を用いてこの発明の詳細な説明する。(Example) Hereinafter, the present invention will be explained in detail using the drawings.

第１図はこの発明の一実施例に係わる半導体装置におけ
る積層固体撮像装置の概略構造を示す図であり、第２図
は第１図における要部構造を示す図である。第１図（ａ
）は装置の平面図、同図（ｂ）は同図（ａ）のＩ−Ｉ線
に沿った断面図である。第２図（ｂ）は要部構造の平面
図、第２図（ａ）は同図（ｂ）の■−■線に沿った断面
図である。FIG. 1 is a diagram showing a schematic structure of a stacked solid-state imaging device in a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the main part structure in FIG. 1. Figure 1 (a
) is a plan view of the device, and figure (b) is a sectional view taken along line II in figure (a). FIG. 2(b) is a plan view of the main structure, and FIG. 2(a) is a sectional view taken along the line ■-■ in FIG. 2(b).

まずはじめに、第１図を参照して積層型の固体撮像装置
の概略構造について説明する。First, a schematic structure of a stacked solid-state imaging device will be described with reference to FIG.

第１図において、半導体基板、例えばＰ型のシリコン基
板１１には、ｎ型の不純物領域からなる蓄積ダイオード
１２が２次元状に配列形成され、それぞれの蓄積ダイオ
ード１２は、周囲が絶縁膜１３で被覆された画素引出し
電ｆｉ１４を介してそれぞれ対応した画素電極１５に接
続されている。In FIG. 1, storage diodes 12 made of n-type impurity regions are arranged in a two-dimensional manner on a semiconductor substrate, for example, a P-type silicon substrate 11, and each storage diode 12 is surrounded by an insulating film 13. Each of the pixel electrodes is connected to the corresponding pixel electrode 15 via a covered pixel lead-out voltage fi14.

画素電極１５上には、例えばアモルファスシリコン膜か
らなる光導電膜１６が形成され、光導電膜１６上には透
明型［ｉ膜１７が積層形成されている。A photoconductive film 16 made of, for example, an amorphous silicon film is formed on the pixel electrode 15, and a transparent [i-film 17] is laminated on the photoconductive film 16.

また、それぞれの蓄積ダ１°オード１２の近傍の絶縁膜
１３中には、垂直ＣＯＤレジスタの転送電極１８が、垂
直方向に配列形成されている。Further, transfer electrodes 18 of a vertical COD register are arranged in the vertical direction in the insulating film 13 near each storage node 12.

このような構造において、透明電極膜１７を介して光導
電膜１６で受光された入射光により信号電荷が生成され
、生成された信号電荷は透明電極膜１７に印加された電
圧により、画素電極１５に誘導され、画素引出し電８ｉ
！１４を介して蓄積ダイオード１２に蓄積される。蓄積
された信号電荷は、垂直ＣＯＤレジスタにより水平ＣＯ
Ｄレジスタ１９に転送され、水平ＣＯＤレジスタ１９か
ら信号出力部２０を介して信号電圧として外部に読出さ
れる。In such a structure, signal charges are generated by incident light received by the photoconductive film 16 via the transparent electrode film 17, and the generated signal charges are transferred to the pixel electrode 15 by the voltage applied to the transparent electrode film 17. The pixel lead-out voltage 8i
! The signal is stored in the storage diode 12 via the storage diode 14. The accumulated signal charge is transferred to the horizontal COD by the vertical COD register.
The voltage is transferred to the D register 19 and read out from the horizontal COD register 19 via the signal output section 20 as a signal voltage.

このような固体撮像装置において、透明電極膜１７にボ
ンディング・ワイヤ７を接合して、このボンディング・
ワイヤ７を介して外部から透明電極膜１７に電圧を印加
するための、ボンディング接合構造が、第１図（ａ）で
は領域２１及び、第１図（ｂ）ではフィールド酸化膜２
２上の絶縁膜１３上に形成されている。In such a solid-state imaging device, the bonding wire 7 is bonded to the transparent electrode film 17, and this bonding wire 7 is bonded to the transparent electrode film 17.
A bonding structure for applying a voltage to the transparent electrode film 17 from the outside via the wire 7 is formed in the region 21 in FIG. 1(a) and in the field oxide film 2 in FIG. 1(b).
2 is formed on the insulating film 13 on top of the insulating film 13 .

このボンディング接合構造の特徴とするところは、第２
図に示すように、第４図に示した従来構造に対して、例
えばシリコン酸化膜２３で被覆されたポリシリコンから
なる台座２４と、この台座２４上に積層された例えばＡ
２からなるボンディング・バッド２５とを、その表面の
高さが絶縁膜１３上に光導電膜１６を介して積層された
透明電極膜１７の表面と同程度の高となるように、光導
電膜１６が開口された開口領域２６内にのみ形成したこ
とにある。The feature of this bonding structure is that the second
As shown in the figure, in contrast to the conventional structure shown in FIG.
A bonding pad 25 consisting of a photoconductive film 2 is placed on a photoconductive film such that its surface height is approximately the same as the surface of the transparent electrode film 17 laminated on the insulating film 13 with the photoconductive film 16 interposed therebetween. 16 is formed only in the opening area 26.

このような構造において、第２図（ｂ）に示す一点鎖線
内で、ボンディング・ワイヤ７とボンディング・バッド
２５及び透明電極膜１７とが接合される。In such a structure, the bonding wire 7, the bonding pad 25, and the transparent electrode film 17 are bonded together within the dashed line shown in FIG. 2(b).

したがって、このような接合構造にあっては、ボンディ
ング・バッド２５が、第４図に示した従来構造のように
、光導電膜１６下には形成されず、光導電［１６が開口
された領域２６にのみ形成されているので、光導電Ｊ１
１６に段差が生じることはなくなる。これにより、光導
電ＷＡ１６上に積層される透明型ｔ！膜１７の段切れを
防止することが可能となる。ゆえに、透明電極Ｍ１７の
電気導通は確実なものとなり、確実に信号電荷が得られ
るとともに、残像焼きつき特性の劣化が防止され、画像
欠陥を抑制することができる。Therefore, in such a bonding structure, the bonding pad 25 is not formed under the photoconductive film 16 as in the conventional structure shown in FIG. 26, the photoconductor J1
16 will no longer occur. This allows the transparent mold t! to be laminated on the photoconductive WA 16! It becomes possible to prevent the membrane 17 from breaking. Therefore, the electrical conduction of the transparent electrode M17 is ensured, and signal charges are reliably obtained, and deterioration of the afterimage burn-in characteristic is prevented, and image defects can be suppressed.

また、ボンディング・パッド２５の表面の高さを透明型
１Ｍ１７のそれと同程度にすることが可能であるので、
ボンディング・ワイヤ７とボンディング・パッド２５と
の接合面と、ボンディング・ワイヤ７と透明型Ｉ［１７
どの接合面がほぼ同一平面となり、ボンディング・ワイ
ヤ７とボンディング・パッド２５とを良好に接続するこ
とができ、十分なボンディング強度を得ることができる
。Furthermore, since it is possible to make the surface height of the bonding pad 25 comparable to that of the transparent type 1M17,
The bonding surface between the bonding wire 7 and the bonding pad 25, and the bonding surface between the bonding wire 7 and the transparent mold I[17
Which bonding surfaces are substantially the same plane, so that the bonding wire 7 and the bonding pad 25 can be connected well, and sufficient bonding strength can be obtained.

次に、この発明の他の実施例を説明する。Next, another embodiment of the invention will be described.

第３図はこの発明の他の実施例に係わる固体撮像装置に
おける要部構造を示す図にあり、同図（ｂ）は平面図、
同図（ａ）は同図（ｂ）の■−■線に沿った断面図であ
る。なお、第３図において、第２図と同符号のものは同
一機能を有するものである。FIG. 3 is a diagram showing the main structure of a solid-state imaging device according to another embodiment of the present invention, and FIG. 3(b) is a plan view;
Figure (a) is a sectional view taken along the line ■-■ in figure (b). Note that in FIG. 3, components having the same symbols as those in FIG. 2 have the same functions.

第３図に示す実施例の特徴とするところは、第２図に示
した実施例に比して、ポンディングパッド２７の形成領
域を、光導電膜１６が開口された領域に限定せずに、ボ
ンディング・パッド２７の周縁の少なくとも一部が、第
２図（ｂ）に−点鎖線内で示すボンディング・ワイヤ７
の接合領域の内側となるように、ボンディング・パッド
２７を形成したことにある。The feature of the embodiment shown in FIG. 3 is that, compared to the embodiment shown in FIG. , at least a portion of the periphery of the bonding pad 27 is connected to the bonding wire 7 shown within the dashed line in FIG. 2(b).
The reason is that the bonding pad 27 is formed inside the bonding area of the bonding pad 27.

このような構造にあっては、ボンディング・パッド２７
に積層されていない部分の光導電［１６上に積層された
透明電極膜１７、すなわち、第３図（ｂ）に領域２８で
示す部分の透明電極ｖ１７がボンディング・ワイヤ７と
接合される。In such a structure, the bonding pad 27
The portion of the transparent electrode film 17 laminated on the photoconductor [16] that is not laminated on the photoconductor 16, that is, the transparent electrode v17 of the portion shown as a region 28 in FIG. 3(b), is bonded to the bonding wire 7.

したがって、このような構造にあっては、ボンディング
・パッド２７の周縁部上の透明電極膜１７で（第２図中
ａ、ｂ、ｃ、ｄで示す）段切れが生じ易くなるが、周辺
の透明電極膜１７と分度されていない部分の透明電極膜
１７、すなわち領域２８で示す部分の透明電極膜１７に
ボンディング・ワイヤ７が接合され、ボンディング・パ
ッド２７に積層されていない光導電膜１６上のすべての
透明電極膜１７が電気的に接続された状態となり、第２
図（ｂ）に示す矢印に沿って電気導通が得られる。ゆえ
に、上記実施例にあっても、前記実施例と同様の効果を
得ることができる。Therefore, in such a structure, breakage (indicated by a, b, c, and d in FIG. 2) is likely to occur in the transparent electrode film 17 on the peripheral edge of the bonding pad 27; The bonding wire 7 is bonded to a portion of the transparent electrode film 17 that is not separated from the transparent electrode film 17, that is, a portion of the transparent electrode film 17 indicated by a region 28, and the photoconductive film 16 that is not laminated to the bonding pad 27 All the upper transparent electrode films 17 are electrically connected, and the second
Electrical continuity is obtained along the arrow shown in Figure (b). Therefore, even in the above embodiment, the same effects as in the above embodiment can be obtained.

なお、この発明は、固体撮像装置を一実施例として説明
したが、これに限ることはなく、回路要素が形成された
半導体基板上に、熱的に脆弱な下地層が積層形成され、
この下地層上にボンディング・ワイヤとの接合強度が十
分に得られない被ボンディング膜が形成された半導体装
置にあっても、この発明を適用できることは、勿論であ
る。Although the present invention has been described using a solid-state imaging device as an example, the present invention is not limited to this.
Of course, the present invention can also be applied to a semiconductor device in which a bonding target film that does not have sufficient bonding strength with a bonding wire is formed on the base layer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明によれば、接合強度を得
るためのボンディング・パッドに積層されていない部分
の下地層に積層された被ボンディング膜にボンディング
・ワイヤを接合させるようにしなので、十分なボンディ
ング強度を確保して、被ボンディング膜への電気導通を
確実にとることが可能な半導体装置を提供することがで
きる。As explained above, according to the present invention, the bonding wire is bonded to the bonding target film laminated on the base layer in the portion not laminated on the bonding pad to obtain bonding strength, so that sufficient bonding strength is obtained. It is possible to provide a semiconductor device that can ensure bonding strength and ensure electrical continuity to a film to be bonded.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例に係わる固体撮像装置の構
造を示す図、第２図は第１図に示す装置の要部構造図、
第３図はこの発明の他の実施例を示す要部構造図、第４
図は従来の半ＩｌＰ体装置の要部構造を示す図である。 １．２．１３・・・絶縁膜、 ３．２４・・・台座、 ４．２５・・・ボンディング・パッド、５．１６・・・
光導電膜、 ６．１７・・・透明電極膜、 ７・・・ボンディング・ワイヤ、 ８・・・段切れ、 １１・・・半導体基板、 ２６・・・開口領域。FIG. 1 is a diagram showing the structure of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a diagram showing the main part structure of the device shown in FIG. 1,
FIG. 3 is a structural diagram of main parts showing another embodiment of the present invention, and FIG.
The figure shows the main structure of a conventional semi-IIP body device. 1.2.13... Insulating film, 3.24... Pedestal, 4.25... Bonding pad, 5.16...
Photoconductive film, 6.17... Transparent electrode film, 7... Bonding wire, 8... Step cutting, 11... Semiconductor substrate, 26... Opening region.

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基板上に下地層を介して積層された被ボン
ディング膜と、接合強度を得る接合補助層とにボンディ
ング線が接合された構造を有する半導体装置において、 前記接合補助層の少なくとも一部の周縁が、前記ボンデ
ィング線の接合面の内側領域となるように、前記接合補
助層を形成したことを特徴とする半導体装置。(1) In a semiconductor device having a structure in which a bonding line is bonded to a bonding target film laminated on a semiconductor substrate via a base layer and a bonding auxiliary layer for obtaining bonding strength, at least a portion of the bonding auxiliary layer. The semiconductor device characterized in that the bonding auxiliary layer is formed such that a peripheral edge thereof is an inner region of the bonding surface of the bonding line. （２）前記接合補助層は、下地層と積層されないように
形成されることを特徴とする請求項１記載の半導体装置
。(2) The semiconductor device according to claim 1, wherein the bonding auxiliary layer is formed so as not to be laminated with a base layer. （３）前記半導体基板は、電荷結合デバイスが形成され
、前記下地層は光導電膜であり、前記被ボンディング膜
は透明電極膜であることを特徴とする請求項１又は請求
項２記載の半導体装置。(3) The semiconductor according to claim 1 or 2, wherein the semiconductor substrate has a charge-coupled device formed thereon, the base layer is a photoconductive film, and the bonding target film is a transparent electrode film. Device.
JP1255255A 1989-10-02 1989-10-02 Semiconductor device Pending JPH03119735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1255255A JPH03119735A (en) 1989-10-02 1989-10-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1255255A JPH03119735A (en) 1989-10-02 1989-10-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03119735A true JPH03119735A (en) 1991-05-22

Family

ID=17276203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1255255A Pending JPH03119735A (en) 1989-10-02 1989-10-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03119735A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101629612B1 (en) * 2015-09-21 2016-06-10 (주)금강칠판교구산업 Chalkboard sheet structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101629612B1 (en) * 2015-09-21 2016-06-10 (주)금강칠판교구산업 Chalkboard sheet structure

Similar Documents

Publication Publication Date Title
KR100297038B1 (en) Solid state image sensor and method for fabracating the same
US7533570B2 (en) Electrostatic-capacitance-type acceleration sensor
JPH0370912B2 (en)
JP6700811B2 (en) Semiconductor device and method of manufacturing semiconductor device
US11408772B2 (en) Process for producing an infrared detector and associated infrared detector
JPH07202159A (en) Solid-state image pickup device
JPH06326293A (en) Photodetector
JPH0590452A (en) Resin-sealed type semiconductor device
JPH03119735A (en) Semiconductor device
TW200307355A (en) Semiconductor integrate device and the manufacturing method thereof
JPH03265171A (en) Image sensor and photoelectric conversion device
JP2005101315A (en) Semiconductor device
US7612442B2 (en) Semiconductor device
JPH05243549A (en) Solid-state image sensing device and its manufacture
JPS62145771A (en) Solid-state image pickup device
JPS6051376A (en) Solid-state image pickup device
JPH0129413B2 (en)
JPS6345856A (en) Solid-state image sensor
JPH07114275B2 (en) Solid-state imaging device
JPS6322469B2 (en)
JPH025473A (en) Solid state image sensor and manufacture thereof
JPS60171A (en) Solid-state image pickup device
JPH02252253A (en) Manufacture of semiconductor device
JPS6273661A (en) Solid-state image pickup device
JPH05152508A (en) Semiconductor device