JPH03116747A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03116747A
JPH03116747A JP1254247A JP25424789A JPH03116747A JP H03116747 A JPH03116747 A JP H03116747A JP 1254247 A JP1254247 A JP 1254247A JP 25424789 A JP25424789 A JP 25424789A JP H03116747 A JPH03116747 A JP H03116747A
Authority
JP
Japan
Prior art keywords
wiring
semiconductor device
bridge
electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1254247A
Other languages
Japanese (ja)
Other versions
JPH088283B2 (en
Inventor
Fumiaki Emori
江森 文章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1254247A priority Critical patent/JPH088283B2/en
Publication of JPH03116747A publication Critical patent/JPH03116747A/en
Publication of JPH088283B2 publication Critical patent/JPH088283B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/141Analog devices
    • H01L2924/1423Monolithic Microwave Integrated Circuit [MMIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the yield of semiconductor devices and enable lowering the price by forming an adjusting element, at least one of the electrodes of which is open, and a bridge wiring across the adjusting element, pressurizing the bridge wiring based on the result of measurement of the electric characteristic, and making adjustment by contact with the open electrode of the adjusting element. CONSTITUTION:Surface circuits 2 formed on a compound semiconductor semi- insulating substrate 1 are connected with a bridge wiring 3 across an electrode also serving as a resistor and as a capacitor. The MMIC chip thus formed is packaged in a semiconductor case 4 and electrically connected thereto with bonding wires 5. For example the high-frequency electric characteristic of a gain is measured. If the desired electric characteristic is not obtained, the bridge wiring 3 is pressurized with a wedge and electrically connected to the electrode therebelow and the high-frequency electric characteristic is measured again. After it is confirmed that the desired characteristic is obtained, a cap 10 is put to complete a semiconductor device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にガリウム砒素あるいは
インジウムリン゛(以下GaAs、InPと記す)等の
化合物半導体からなる半絶縁性基板上に形成されたマイ
クロ波モノリシック集積回路(以下MMICと記す)を
用いた半導体装置の製造方法に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device formed on a semi-insulating substrate made of a compound semiconductor such as gallium arsenide or indium phosphide (hereinafter referred to as GaAs or InP). The present invention relates to a method of manufacturing a semiconductor device using a microwave monolithic integrated circuit (hereinafter referred to as MMIC).

〔従来の技術〕[Conventional technology]

化合物半導体からなる半絶縁性基板上に電界効果トラン
ジスタ(以下FETと記す)構造を有する能動素子とこ
の能動素子の機能を発揮させる。
An active element having a field effect transistor (hereinafter referred to as FET) structure is provided on a semi-insulating substrate made of a compound semiconductor, and the function of this active element is exhibited.

受動素子による整合回路から成るMMICは、ハイブリ
ッド型集積回路(以下HI Cと記す)に比べて高周波
特性に優れ、小型・低価格化が可能であり且つ信頼性も
高い事から特に数10GHz領域に於いて実用化されつ
つある。
MMIC, which consists of a matching circuit using passive elements, has superior high-frequency characteristics compared to hybrid integrated circuits (hereinafter referred to as HIC), can be made smaller and cheaper, and has high reliability, so it is particularly popular in the several tens of GHz range. It is being put into practical use.

従来、MMICは半絶縁性基板の主表面に密着して形成
された薄膜金属と例えばSiのイオンを半絶縁性基板に
注入した注入層等から成り、更に、例えばセラミックか
ら成る半導体容器に実装され製造されていた。この製造
方法を図を用いて説明する。
Conventionally, an MMIC consists of a thin metal film formed in close contact with the main surface of a semi-insulating substrate and an implanted layer in which, for example, Si ions are implanted into the semi-insulating substrate, and is further mounted in a semiconductor container made of, for example, ceramic. It was manufactured. This manufacturing method will be explained using figures.

第4図(a)〜(f)は、従来のMMICの製造方法を
説明する為に工程順に示した模式的断面図である。
FIGS. 4(a) to 4(f) are schematic cross-sectional views shown in order of steps to explain a conventional MMIC manufacturing method.

第4図(a)に示す例えばGaAs、InPといった化
合物半導体からなる半絶縁性基板1の主表面に、光感光
波術を応用し、例えばTi−Pt−Auの厚さ1100
nの多層構造の薄膜金属やSiイオンの注入層により形
成されたFET等による表面回路2が第4図(b)の様
に形成されMMICチップを成ず。第4図(C)の様に
、このMMICチップでは半導体容器4に例えばAuS
n合金を加熱溶融させる事により実装される。その後、
第4図(d)の様に例えば30μmのAu線のボンディ
ングワイヤー5を熱圧着する事で、MMICチップと半
導体容器4とを電気的に接続する。更に、第4図(e)
の様に、半導体容器4にキャップ10を被せる。組み立
てられたこの半導体装置は、信号源7からの高周波信号
を通し、検波器8により特性検査され、所望の特性の得
られないものは不良廃棄され良品のみが製造される。
A photosensitive wave technique is applied to the main surface of a semi-insulating substrate 1 made of a compound semiconductor such as GaAs or InP shown in FIG.
A surface circuit 2 consisting of an FET or the like formed of a thin film metal having a multilayer structure of n and an implanted layer of Si ions is formed as shown in FIG. 4(b) to form an MMIC chip. As shown in FIG. 4(C), in this MMIC chip, the semiconductor container 4 is made of, for example, Au.
It is mounted by heating and melting the n-alloy. after that,
As shown in FIG. 4(d), the MMIC chip and the semiconductor container 4 are electrically connected by thermocompression bonding a bonding wire 5 made of, for example, a 30 μm Au wire. Furthermore, Fig. 4(e)
Cover the semiconductor container 4 with the cap 10 as shown in FIG. The characteristics of the assembled semiconductor devices are inspected by a detector 8 using a high-frequency signal from a signal source 7, and those that do not have the desired characteristics are rejected and only non-defective devices are manufactured.

〔発明が解決しようとする課題〕 上述した従来のMMICは、電気的に調整する余地が無
く、最終工程にて不良のものは廃棄しなくてはならず歩
留がMMICチップを作る拡散工程によって決定され、
回路内でFET等の素子ばらつきを修正できないという
欠点があった。
[Problems to be Solved by the Invention] The conventional MMIC described above has no room for electrical adjustment, and defective products must be discarded in the final process, resulting in a reduction in yield due to the diffusion process for making MMIC chips. decided,
There is a drawback that variations in elements such as FETs cannot be corrected within the circuit.

特に、数10GHzに於けるMMICにあっては、FE
Tに高周波での高性能を要求されそのゲート長Agも例
えば0.25μm、ゲート・ソース間距離0.4μmと
いった微細寸法である。よって、0.05μmの物理寸
法のばらつきが、特性ばらつきとしては20%以上もの
ばらつきを生む事となる。現在ゲート長の制御性は、量
産ペースで0.1μmである。よってMMICは、特性
均一性は高いもののMMICチップを作る拡散工程のロ
ット異存性が高く、ロットアウトにより数100個のM
MICチップを全滅させる事もめずらしく無い。こうし
た歩留の低さがMMICによる半導体装置の低価格化の
妨げとなっており、その優秀性は認められているものの
普及を遅らせている原因でもある。
In particular, for MMICs at several tens of GHz, FE
High performance at high frequencies is required for T, and its gate length Ag is also minute, such as 0.25 μm and gate-source distance 0.4 μm. Therefore, a variation in physical dimensions of 0.05 μm causes a variation in characteristics of 20% or more. At present, the controllability of gate length is 0.1 μm at a mass production pace. Therefore, although MMIC has high characteristic uniformity, there is high lot-to-lot variation in the diffusion process for making MMIC chips, and due to lot-out, hundreds of MMICs are produced.
It is not uncommon for MIC chips to be completely destroyed. This low yield is an impediment to lowering the price of semiconductor devices using MMICs, and although their superiority is acknowledged, it is also the cause of slowing down their widespread use.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、化合物半導体からな
る半絶縁性基板に電界効果トランジスタ、受動素子によ
る整合回路及び少なくとも1つの橋状配線を含む導体配
線からなるマイクロ波回路を形成してマイクロ波モノリ
シック集積回路チップを準備する工程を含む半導体装置
の製造方法において、所定位置に少なくとも一電極を開
放状態にした調整用素子及び前記調整用素子をまたいで
前記橋状配線を設ける工程と、電気的特性の測定結果に
基づいて前記橋状配線を加圧して前記調整用素子の開放
電極に接触させる調整工程とを有するというものである
The method for manufacturing a semiconductor device of the present invention includes forming a microwave circuit consisting of a field effect transistor, a matching circuit using passive elements, and a conductor wiring including at least one bridge-like wiring on a semi-insulating substrate made of a compound semiconductor. A method for manufacturing a semiconductor device including the step of preparing a monolithic integrated circuit chip, the step of providing an adjustment element with at least one electrode in an open state at a predetermined position and the bridge-like wiring across the adjustment element; The method further includes an adjustment step of applying pressure to the bridge-like wiring to bring it into contact with the open electrode of the adjustment element based on the measurement results of the characteristics.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(h)は、本発明の一実施例を説明する
為に工程順に示した模式的断面図である。      
  −・ 第1図(a>に示す例えばTi−Pt−Auの厚さ11
00nの多層構造の薄膜金属やSiイオンの注入層によ
り形成されたFET等による表面回路2が第1図(b)
の様に形成される。更に、表面回路2同志をエアーブリ
ッジと称する例えば幅100μm、厚さ2μmのAuメ
ツキによる橋゛上配線3にて接続する。この橋上配線は
、第1図(C)の様に例えば抵抗、コンデンサの機能を
有する先のTi−Pt−Auの薄膜金属でできた電極(
例えば100μmX100μm)をまたぐ構造である。
FIGS. 1(a) to 1(h) are schematic cross-sectional views shown in order of steps to explain an embodiment of the present invention.
- For example, the thickness 11 of Ti-Pt-Au shown in Figure 1 (a)
Figure 1(b) shows a surface circuit 2 consisting of an FET, etc. formed of a thin film metal with a 00n multilayer structure and an implanted layer of Si ions.
It is formed like this. Further, the surface circuits 2 are connected to each other by a bridge wiring 3 called an air bridge, which is made of Au plating and has a width of 100 μm and a thickness of 2 μm, for example. As shown in Fig. 1(C), this bridge wiring is made of an electrode made of the previously mentioned Ti-Pt-Au thin film metal that has the function of a resistor and a capacitor.
For example, it has a structure spanning 100 μm x 100 μm).

この様にしてできたMM I Cチップを次に第1図(
d)の様に半導体容器4に例えばA u S n合金を
320℃にて加熱溶融させる事により実装する。その後
、第1図(e)の様に例えば30μmφのAu線のボン
ディングワイヤー5を280°Cにてウェッジと称する
サファイア針による熱圧着をする事で、MMICチップ
と半導体容器4とを電気的に接続する。
The MM IC chip made in this way is shown in Figure 1 (
As shown in d), it is mounted in the semiconductor container 4 by heating and melting, for example, an AuSn alloy at 320°C. Thereafter, as shown in FIG. 1(e), the MMIC chip and the semiconductor container 4 are electrically bonded by thermocompression bonding, for example, a 30 μmφ Au bonding wire 5 at 280°C using a sapphire needle called a wedge. Connecting.

こうして作られたMMICチップの実装された半導体装
置を、第1図(f)の様に、入力側に高周波の信号源7
からの信号を同軸ケーブル6により供給し、出力側にこ
の半導体装置から出る信号を検波する為の検波器8を同
軸ケーブル6を介して接続する事により、例えば利得の
高周波電気特性を測定し試験する。この際、所望の電気
的特性が得られない場合、あらかじめ開発・設計時に決
めてあった橋状配線3をウェッジにより加圧し、橋状配
線3がまたいでいた電極と電気的に接続される。そして
、再度高周波電気特性を測定試験し、所望の特性を確認
した後、第1図(b)に示す様にキャップ10を被せて
この半導体装置の製造を完了する。
As shown in FIG. 1(f), the semiconductor device mounted with the MMIC chip manufactured in this way is connected to a high-frequency signal source 7 on the input side.
By supplying a signal from the semiconductor device through a coaxial cable 6 and connecting a detector 8 to the output side via the coaxial cable 6 to detect the signal output from this semiconductor device, high-frequency electrical characteristics such as gain can be measured and tested. do. At this time, if the desired electrical characteristics cannot be obtained, the bridge-like wiring 3, which was determined in advance at the time of development and design, is pressurized by a wedge, and the bridge-like wiring 3 is electrically connected to the electrode that it spans. After measuring and testing the high frequency electrical characteristics again and confirming the desired characteristics, a cap 10 is placed on the semiconductor device as shown in FIG. 1(b) to complete the manufacture of this semiconductor device.

第2図は、例えばFET1段の増幅器に於いて、入力の
整合回路を本発明を用いて調整する事を説明する為の回
路図である。
FIG. 2 is a circuit diagram for explaining adjusting the input matching circuit using the present invention in, for example, a single-stage FET amplifier.

例えば、FETIIのゲート長1gの物理的寸法がばら
つき、FET11固有の高周波パラメータにばらつきが
出た際につき説明する。
For example, a case will be explained in which the physical dimensions of the gate length 1g of FET II vary and the high frequency parameters specific to FET 11 vary.

FET11の入力回路は、直列に入った整合用コイル1
2と並列に入った整合用コンデンサから成る。あらかじ
め、整合用コイル12と整合用コンデンサ13−1との
接続を橋状配線3を用いて接続し且つA部の調整用素子
である整合用コンデンサ13−2の開放電極を橋状配線
3が飛び越えるMMICチップの内部レイアウトを取る
。このMM I Cを実装した半導体装置につき、電気
的特性測定試験を行ない、所望の特性が得られない場合
には、橋状配線3を例えばウェッジによる加圧で圧着し
A部を電気的に導通させ、整合回路に於ける整合用コン
デンサの容量値を増大させて不整合を改善し所望の特性
を得る。
The input circuit of FET11 consists of matching coil 1 connected in series.
It consists of a matching capacitor connected in parallel with 2. In advance, the matching coil 12 and the matching capacitor 13-1 are connected using the bridge-like wiring 3, and the bridge-like wiring 3 connects the open electrode of the matching capacitor 13-2, which is the adjustment element of part A. Take the internal layout of the MMIC chip. An electrical characteristic measurement test is performed on the semiconductor device in which this MMI C is mounted, and if the desired characteristics are not obtained, the bridge-like wiring 3 is crimped with pressure using a wedge, for example, to make the A part electrically conductive. By increasing the capacitance of the matching capacitor in the matching circuit, the mismatch is improved and desired characteristics are obtained.

第3図は、本発明の一実施例の変形を説明するための回
路図である。
FIG. 3 is a circuit diagram for explaining a modification of one embodiment of the present invention.

例えば、FET1段の増幅器に於いて、半絶縁性基板1
の主表面に形成されたFETIIの能動層形成の為に行
なったSiイオンの注入ばらつきで生じるFET11の
しきい値電圧Vtずれが出た際の調整方法につき説明す
る。FET11のゲート端子の電位は、バイアス抵抗1
4によって決定される。設計に於けるFETIIのしき
い値電圧が例えばVt−1,OVであったとし、実際(
7) F E T 11 テハV t =  0 、8
 Vであった場合、ゲート・ソース間電圧を小さくしな
くてはならない。あらかじめ、入力端子と接地端との間
にバイアス抵抗14−1を挿入して橋状配線3を用いて
接続し且つB部の調整用のバイアス抵抗14−2の開放
電極上を橋状配線3が飛び越えるMMICチップの内部
レイアウトを取る。このMMICを実装した半導体装置
につき、電気的特性測定試験を行ない、所望の特性が得
られない場合には、橋状配線3を例えばウェッジによる
加圧で圧着しB部を電気的に導通させ、バイアス抵抗値
を変えて最適なバイアス条件を得る。
For example, in an amplifier with one stage of FET, the semi-insulating substrate 1
A method of adjusting the threshold voltage Vt of the FET 11 caused by variations in the implantation of Si ions for forming the active layer of the FET II formed on the main surface of the FET 11 will be described below. The potential of the gate terminal of FET11 is set by bias resistor 1.
4. Suppose that the threshold voltage of FET II in the design is, for example, Vt-1, OV, and in reality (
7) F E T 11 Teha V t = 0, 8
If it is V, the gate-source voltage must be reduced. In advance, a bias resistor 14-1 is inserted between the input terminal and the ground terminal and connected using the bridge-like wiring 3, and the bridge-like wiring 3 is connected to the open electrode of the bias resistor 14-2 for adjustment in part B. Take the internal layout of the MMIC chip that jumps over. The semiconductor device mounted with this MMIC is subjected to an electrical characteristic measurement test, and if the desired characteristics are not obtained, the bridge-like wiring 3 is crimped by pressure using a wedge, for example, to make the B part electrically conductive. Obtain optimal bias conditions by changing the bias resistance value.

以上、調整用素子として整合用コンデンサ、バイアス抵
抗の例を述べたが、整合用コイルを調整用素子にするこ
ともできる。ところで、MMICを構成する為のFET
にとって、最も低雑音増幅が計れるインピーダンスと最
も高出力を得るインピーダンスとは一般に合致せず、例
えばSパラメータでの位相角と絶対値が共に異なる。本
発明によれば、整合用コイルと整合用コンデンサの調整
が可能なところから、低雑音増幅用の整合回路定数と高
出力増幅用の整合回路定数との切換ができ、ひとつのM
MICチップを用いて特性の選択が可能であり、要求性
能に適格に合致させることも可能となる。
Although examples of a matching capacitor and a bias resistor have been described above as adjustment elements, a matching coil can also be used as an adjustment element. By the way, FET for configuring MMIC
For example, the impedance that provides the lowest noise amplification and the impedance that provides the highest output generally do not match, and for example, the phase angle and absolute value of the S-parameter differ. According to the present invention, since the matching coil and the matching capacitor can be adjusted, it is possible to switch between the matching circuit constant for low noise amplification and the matching circuit constant for high output amplification, and one M
It is possible to select the characteristics using the MIC chip, and it is also possible to suitably meet the required performance.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、MMICチップ内に調整
用素子をまたいで橋状配線3を形成し半導体装置の製造
工程中キャップ10をする前に電気的特性を測定試験し
、所望の電気的特性を得る為に橋状配線3に加重をかけ
て調整用素子の開放電極と圧着して電気的導通をとると
いう調整をする事により、半導体装置の歩留りを改善し
低価格化できる効果がある。
As explained above, in the present invention, the bridge wiring 3 is formed across the adjustment element in the MMIC chip, and the electrical characteristics are measured and tested before the cap 10 is attached during the manufacturing process of the semiconductor device, and the desired electrical characteristics are obtained. In order to obtain the characteristics, the bridge-like wiring 3 is applied with a load and is crimped to the open electrode of the adjustment element to establish electrical continuity, which has the effect of improving the yield of semiconductor devices and reducing the cost. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(h)は本発明の一実施例を説明する為
に工程順に示したMMICの製造方法の模式的断面図、
第2図は、入力の整合回路調整を説明する為の回路図、
第3図は、バイアス回路調整を説明するための回路図、
第4図(a)〜(f)は従来のMMICの製造方法を説
明する為に工程順に示した模式的断面図である。 1・・・半絶縁性基板、2・・・表面回路、3・・・橋
状配線、4・・・半導体容器、5・・・ボンディングワ
イヤー 6・・・同軸ケーブル、7・・・信号源、8・
・・検波器、9・・・圧着部、10・・・キャップ、1
1・・・FET、12−1.12−2・・・整合用コイ
ル、13・・・整合用コンデンサ、14−1.14−2
・・・バイアス抵抗。
FIGS. 1(a) to (h) are schematic cross-sectional views of an MMIC manufacturing method shown in order of steps to explain an embodiment of the present invention;
Figure 2 is a circuit diagram for explaining input matching circuit adjustment.
FIG. 3 is a circuit diagram for explaining bias circuit adjustment,
FIGS. 4(a) to 4(f) are schematic cross-sectional views shown in order of steps to explain a conventional MMIC manufacturing method. DESCRIPTION OF SYMBOLS 1... Semi-insulating substrate, 2... Surface circuit, 3... Bridge-like wiring, 4... Semiconductor container, 5... Bonding wire 6... Coaxial cable, 7... Signal source , 8・
...Detector, 9...Crimp part, 10...Cap, 1
1... FET, 12-1.12-2... Matching coil, 13... Matching capacitor, 14-1.14-2
...Bias resistance.

Claims (1)

【特許請求の範囲】[Claims] 化合物半導体からなる半絶縁性基板に電界効果トランジ
スタ、受動素子による整合回路及び少なくとも1つの橋
状配線を含む導体配線からなるマイクロ波回路を形成し
てマイクロ波モノリシック集積回路チップを準備する工
程を含む半導体装置の製造方法において、所定位置に少
なくとも一電極を開放状態にした調整用素子及び前記調
整用素子をまたいで前記橋状配線を設ける工程と、電気
的特性の測定結果に基づいて前記橋状配線を加圧して前
記調整用素子の開放電極に接触させる調整工程とを有す
ることを特徴とする半導体装置の製造方法。
A step of preparing a microwave monolithic integrated circuit chip by forming a microwave circuit consisting of a field effect transistor, a matching circuit using passive elements, and a conductor wiring including at least one bridge-like wiring on a semi-insulating substrate made of a compound semiconductor. In a method for manufacturing a semiconductor device, the step of providing an adjustment element with at least one electrode open at a predetermined position and the bridge-like wiring across the adjustment element; A method for manufacturing a semiconductor device, comprising an adjustment step of pressurizing the wiring to bring it into contact with the open electrode of the adjustment element.
JP1254247A 1989-09-28 1989-09-28 Method for manufacturing semiconductor device Expired - Fee Related JPH088283B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1254247A JPH088283B2 (en) 1989-09-28 1989-09-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1254247A JPH088283B2 (en) 1989-09-28 1989-09-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH03116747A true JPH03116747A (en) 1991-05-17
JPH088283B2 JPH088283B2 (en) 1996-01-29

Family

ID=17262329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1254247A Expired - Fee Related JPH088283B2 (en) 1989-09-28 1989-09-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH088283B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006292996A (en) * 2005-04-11 2006-10-26 Dainippon Printing Co Ltd Information protective sheet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006292996A (en) * 2005-04-11 2006-10-26 Dainippon Printing Co Ltd Information protective sheet

Also Published As

Publication number Publication date
JPH088283B2 (en) 1996-01-29

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