JPH03116725A - Resist peel-off method - Google Patents

Abstract

PURPOSE:To prevent redeposit of insoluble substances upon resist peel-off and deterioration of a peel-off solution by applying a resist after the base pattern on a substrate wafer is etched, and by removing resists through etching at a 1/2-3 ratio of etching rates between a resist and an anti-O2 etching layer and through O2 ashing. CONSTITUTION:A base 2 such as of Al is processed on the base 1 such as of SiO2 deposited on a substrate wafer, and an anti-O2 etching layer 4 is formed on a lower layer resist 3 coating the base 2. Next, another resist 5 is applied to coat the base 2, thereby protecting the base from a next etching. After the solvent of the resist 5 is released by bake, it is etched on an etching condition that the ratio of etching rates between the resist 5 and the anti-O2 etching layer 4 is 1/2-3. After removal of the layer 4, the resists 5, 3 are removed by O2 ashing that is a normal resist removing method.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a resist stripping method for preventing redeposition of insolubilized substances to a wafer and deterioration of stripping flow during stripping of a multilayer resist in LSI manufacturing. It is something.

(Prior Art) With the increasing integration of LSIs, the demand for finer patterns has not stopped. As a result, the limitations of lithography technology have been highlighted as problems, and issues such as the generation of standing waves due to diffraction phenomena and reflection interference effects in photolithography have been discussed, and these problems are particularly noticeable at stepped areas.

A multilayer resist structure was developed as a method to meet these demands. A multilayer resist has a structure in which high sensitivity and high resolution are achieved by using a thin photosensitive layer resist, and at the same time it also serves as a planarization process.

Further, a multilayer resist structure is also essential in EB (electron beam) exposure. The structural process is described in "Submicron Lithography Comprehensive Technical Data Collection" (Science Forum Co., Ltd., published March 20, 1985, pages 302-319)
, Section 4 Multilayer Resist), in particular, the lower layer resist is 0. RT[+ (Reactive・
Three-layer and two-layer resist processes patterned using ion etching (ion etching) can form fine patterns with large aspect ratios and excellent dry etching resistance, so they have been applied to photolithography and EB lithography, and their usefulness has been proven. There is.

Multilayer resist technology using 0zRIH is considered to be very useful for future LSI manufacturing.

(Problems to be Solved by the Invention) However, in multilayer resist technology using etching using 0□ as an etching gas (hereinafter referred to as O2 etching), when stripping the resist, O! In the case of a three-layer resist, which serves as an etching mask during etching, the middle layer, and in the case of a two-layer resist, the upper layer remains as an insoluble in the stripping solution, a mixture of sulfuric acid and hydrogen peroxide, or in the fuming nitric acid, and is reused on the wafer. There was a problem in that it adhered and caused a decrease in yield.

In addition, in the case of normal single-layer resist stripping, most of the resist is removed with 01 ashing before being placed in a mixture of sulfuric acid and hydrogen peroxide, or fuming nitric acid, to prevent the stripping solution from deteriorating too much. This method is not possible with a multilayer resist method with an O2 etch-resistant layer.

On the other hand, if etching is performed using another gas different from 0□, it is possible to remove the 02 etching resistant layer and solve the above-mentioned problem of insoluble matter, but the underlying substrate will also be etched and damaged at the same time. I end up.

This invention eliminates the problems that the prior art has.
! The object of the present invention is to provide a resist stripping method that solves the problem of insolubilized substances re-adhering to a wafer during resist stripping and the problem of deterioration of a stripping solution in a multilayer resist method using etching.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention, in a resist stripping method, coats a resist after etching a base pattern on a substrate wafer, and has a zero resistance with this resist. This method introduces a process of etching the etching layer using gas under etching conditions in which the etching rate ratio is between 1/2 and 3.

(Function) This invention introduces the above-mentioned steps in the resist stripping method, so that after etching the underlying pattern on the substrate wafer, a resist is applied to the substrate wafer, and the etching rate of the resist and the Ot etching resistant layer is increased. Ratio is from 〃 to 3
By etching under conditions between the two, removing the Ot etch-resistant layer, and performing 02 ashing, the resist can be removed, and the above-mentioned problem can therefore be removed.

(Example) Hereinafter, an example of the resist stripping method of the present invention will be described based on the drawings. Figure 1 (a) to Figure 1 (b)
1 is a process sectional view of one embodiment.

First, an overview of the invention will be described. FIG. 1(a) is a cross-sectional view of a substrate wafer in a state before the resist is peeled off when a multilayer resist is used.

1 in FIG. 1(a) is the Sing on the substrate wafer.
etc., and 2 is the AI processed on this base 1.
A lower resist 3 is coated on the base 2, and a 0□ etching resistant layer 4 is formed on the lower resist 3. Here, if the etching conditions are such that the O-resistant etching layer 4 is removed, the underlying layer 2 will be damaged.

Therefore, in the present invention, a resist 5 is newly applied to the substrate wafer in the state shown in FIG. 1(a), as shown in FIG. 1(b). This resist 5 may be of the same type as the lower resist 3, or may be a novolac positive resist.

By applying this resist 5, as shown in FIG. 1(b),
By covering the base 2, the base can be protected from the next etching.

After the solvent of the resist 5 is blown off by baking, the first etching is performed.The O2 etching-resistant layer 4 may be made of a St compound containing 5i-0 bonds or amorphous Si, so the gas used here is, for example, , CI'a
and fluorocarbons such as CHF5 with 0 added to them.

By this etching, as shown in FIG. 1(c), the 08 etching resistant layer 4 is removed.
), 08 ashing, which is a normal resist removal method, can be performed, and the resist 5 and the lower resist 3 are removed.

Next, specific embodiments of the present invention will be described in more detail.

<Example 1> First, the formation of a base substrate will be described. As shown in FIG. 1(a), a base 1 such as a SiO□ film is formed on a 5-inch φS+ substrate by CVD to a thickness of 0.6
．． Underlayer 2 was formed using AI having a thickness of 6 μm by sputtering.

Here, AI becomes the base for pattern formation, and 5i (
The h-film is usually placed below the AI as an LSI structure.

Next, apply a positive resist 0FPR-800 on the AI base 2.
(Tokyo Ohka) was formed by spin coating to a thickness of 1.7 nm, and this was used as the lower resist 3.

Next, perform beta for 3 minutes on a hot plate at 200°C, and then remove the 0□ resistant etching layer 4 from OCD TYP.
E-7Lout% (Tokyo Ohka) was coated to a thickness of 0.3 μm, and subjected to beta heating at 220° C. for 5 minutes on a hot plate.

Next, as a patterning layer by photolithography, TSMR
-V3 (Tokyo Ohka) was formed with a thickness of 0.5 nm (spin coating at 80°C for 1 minute beta), NAo,
150 vaJ/c using a 45 g line stepper
After exposure at 100° C. and post-exposure beta at 110° C. for 1 minute, paddle development was performed for 60 seconds using a developer NMD-W (Tokyo Ohka) to obtain an upper layer pattern.

This was beta-etched at 130°C for 1 minute, and first, in order to transfer the upper layer pattern to the 02 etching-resistant layer 4,
(M Rc) using CI (F3 flow rate 11005
C.C.

0, flow rate 14SCCM, pressure 45mTorr, RF
Etching is performed for 2 minutes under the condition of (high frequency) power of 1500W.

Continue etching the lower layer at a flow rate of 203CCM.

This is carried out for 5 minutes at a pressure of 5 mTorr and RF power of too much to obtain a multilayer resist pattern. At this time, the upper layer photoresist had been etched and disappeared.

Next, use this resist as a mask to etch the underlying AI! , flow rate 145 SCCM, C1z 40
SCCM.

The test was carried out for 8 minutes under the conditions of CHF530 SCCM, pressure of 5QmTorr, bias of 180mm using Erracha manufactured by Abride Materials.

The process according to the present invention starts from the 0th order in which a pattern corresponding to FIG. 1(a) is obtained in this way.

As shown in FIG.
Spin code with pm, hot plate, 120
A 1 minute beta was performed at °C.

The newly applied resist 5 covers the entire surface of the substrate wafer. The resist film thickness in the area without a pattern is 1.7μ.

Next, conditions were set such that the etching rates of the resist 5 and the O2 etching resistant layer 4 were equal, and the CHF2 flow rate was 50 SC.
CM, 0! Flow rate 50SCG? I, pressure 50 mTor
rRF power 1500W? Etching was performed using 1IF710 for 3 minutes as shown in FIG. 1(c).

The etching speed under these conditions was measured using another wafer, and the etching speed for resist 5 was 2,400 etching per minute, and for OCD it was 13
00 people/minute.

Next, C) IF s flow rate is set to 0 and O7 is set to 100 S.
As CCM, under the same conditions, as shown in Figure 1(d),
Etching (0□ etching) was performed for 8 minutes. After etching, a slight etching residue was observed on the surface of the substrate wafer, but the underlying layer 1 was exposed over the entire surface of the substrate wafer.

This was immersed in fuming nitric acid, which is a stripping solution, for 5 minutes, and then
Cleaning with pure water was performed for 0 minutes. When the surface of the substrate wafer was inspected, there were no deposits and the residue from the previous etching was completely removed.

<Comparative Example 1> Same as <Example 1> ^! The wafer with the multilayer resist that had been etched was immersed in fuming nitric acid for 5 minutes, and then washed with pure water for 10 minutes. When the wafer surface was inspected, seven deposits were found within a 20an x 20mm area.

<Comparative Example 2> Similarly to <Example 1>, a wafer with a multilayer resist that had been subjected to AI etching was first subjected to CI (F! style 1100 SCCM) to remove the 0□ etching layer.

Ox 14 SCCM, pressure 50mTorr, RF
With 1500W of power? The test was carried out using IIE710 for 2 minutes. At this time, the exposed base of 5iJWA is 1500
I was being sexually assaulted.

Note that this invention applies to 16-bit DRAM and 64-bit DR.
This method is effective for manufacturing semiconductor integrated circuits such as AM that require patterns of 0.5 n or less.

(Effects of the Invention) As described above in detail, according to the present invention, when removing the multilayer resist, the resist is recoated on top of the multilayer resist and the resist is resistant to oxygen.
, the etching speed ratio of the etching layer and resist layer is % ~
After etching under conditions between 3 and 3, Ot ashing was performed to remove the resist, so after removing the O2 etching resistant layer without damaging the underlying substrate,
A normal single-layer resist stripping method can be applied.

This makes it possible to solve the problems of insoluble matter in the stripping solution and deterioration of the stripping solution, and it is possible to improve fractionation and reduce costs.

[Brief explanation of drawings]

FIGS. 1(a) to 1(dl) are process cross-sectional views of an embodiment of the resist stripping method of the present invention. 1.2... Underlayer, 3... Lower layer resist, 4... Resistance. 0! Etching layer, 5... Resist. Book, Invention I No. 1) Process sectional view 1

Claims (1)

[Claims] (a) a step of applying a resist after etching the patterning of the lower layer of the substrate wafer; (b) an etching rate ratio between the resist and the O_2 etch-resistant layer is between 1/2 and 3; A resist stripping method comprising: a step of etching under etching conditions; and (c) a step of removing the resist by O_2 ashing after this etching.