JPH03116443U - - Google Patents

Info

Publication number
JPH03116443U
JPH03116443U JP2363290U JP2363290U JPH03116443U JP H03116443 U JPH03116443 U JP H03116443U JP 2363290 U JP2363290 U JP 2363290U JP 2363290 U JP2363290 U JP 2363290U JP H03116443 U JPH03116443 U JP H03116443U
Authority
JP
Japan
Prior art keywords
memory
latch
correction circuit
transfer clock
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2363290U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2363290U priority Critical patent/JPH03116443U/ja
Publication of JPH03116443U publication Critical patent/JPH03116443U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
JP2363290U 1990-03-08 1990-03-08 Pending JPH03116443U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2363290U JPH03116443U (enExample) 1990-03-08 1990-03-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2363290U JPH03116443U (enExample) 1990-03-08 1990-03-08

Publications (1)

Publication Number Publication Date
JPH03116443U true JPH03116443U (enExample) 1991-12-03

Family

ID=31526614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2363290U Pending JPH03116443U (enExample) 1990-03-08 1990-03-08

Country Status (1)

Country Link
JP (1) JPH03116443U (enExample)

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