JPH03116442U - - Google Patents
Info
- Publication number
- JPH03116442U JPH03116442U JP2312990U JP2312990U JPH03116442U JP H03116442 U JPH03116442 U JP H03116442U JP 2312990 U JP2312990 U JP 2312990U JP 2312990 U JP2312990 U JP 2312990U JP H03116442 U JPH03116442 U JP H03116442U
- Authority
- JP
- Japan
- Prior art keywords
- access
- memory
- interleave
- storage device
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 17
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
第1図は本考案による可変インターリーブ制御
方式による記憶装置の一実施例を示す図、第2図
は第1図に示すアドレス切り換え部の一実施例を
概略的に示す図、第3図はメモリーの領域の分割
を概略的に説明するための図、第4図は本考案に
よる可変インターリーブ制御記憶装置の初期化処
理を説明するための流れ図である。
1……メモリーバンク選択部、2……アドレス
切換部、3……データバツフア、4……インター
リーブ判定部、5……メモリー制御信号発生部。
FIG. 1 is a diagram showing an embodiment of a storage device using the variable interleave control method according to the present invention, FIG. 2 is a diagram schematically showing an embodiment of the address switching section shown in FIG. 1, and FIG. 3 is a diagram showing a memory FIG. 4 is a flow chart for explaining the initialization process of the variable interleave control storage device according to the present invention. 1...Memory bank selection section, 2...Address switching section, 3...Data buffer, 4...Interleave determination section, 5...Memory control signal generation section.
Claims (1)
クセス可能でメモリー増設可能な複数のバンクを
有する記憶装置において、前記増設されたメモリ
ーに対応するアクセスメモリーアドレス毎にイン
ターリーブアクセスか非インターリーブアクセス
かのいずれか一方を指示する指示手段と、前記指
示手段からの指示に基づいて前記メモリーアドレ
スをインターリーブアクセスアドレス又は非イン
ターリーブアクセスアドレスに変換して実メモリ
ーアドレスとするメモリーアクセス手段とを有す
ることを特徴とする可変インターリーブ制御記憶
装置。 (2) 実用新案登録請求の範囲第1項に記載され
た可変インターリーブ制御記憶装置において、前
記指示手段は前記アクセスメモリーアドレスに基
づいて前記バンクを選択する選択信号を生成する
選択手段と、前記バンク毎に予め設定されたイン
ターリーブ許可信号と前記選択信号とに基づいて
前記インターリーブアクセス可能か否かを判定し
て判定信号を出力する判定手段とを備え、前記メ
モリーアクセス手段は前記判定信号を前記指示と
して受け、前記メモリーアドレスを前記インター
リーブアクセスアドレス又は前記非インターリー
ブアクセスアドレスに変換するようにしたことを
特徴とする可変インターリーブ制御記憶装置。 (3) 実用新案登録請求の範囲第1項に記載した
可変インターリーブ制御記憶装置において、初期
化の際に用いられ、前記メモリーの全てを非イン
ターリーブアクセスによつて初期設定し前記増設
メモリー毎に前記インターリーブアクセスの可否
を設定する設定手段と、前記メモリーの診断を行
い未実装メモリーと動作不良メモリーとを検出し
てメモリー容量を決定する決定手段とを有するこ
とを特徴とする可変インターリーブ制御記憶装置
。[Claims for Utility Model Registration] (1) In a storage device that is equipped with a plurality of memories and has a plurality of banks that can be accessed in an interleaved manner and can be expanded, interleaved access can be performed for each access memory address corresponding to the expanded memory. an instruction means for instructing either non-interleaved access; and memory access means for converting the memory address into an interleaved access address or a non-interleaved access address to obtain a real memory address based on an instruction from the instruction means. A variable interleave control storage device comprising: (2) Utility model registration In the variable interleave control storage device described in claim 1, the instruction means includes a selection means for generating a selection signal for selecting the bank based on the access memory address; determination means for determining whether or not the interleave access is possible based on the interleave permission signal set in advance and the selection signal for each case, and outputting a determination signal, the memory access means converting the determination signal into the instruction A variable interleave control storage device, wherein the memory address is received as the interleave access address or the non-interleave access address. (3) Utility model registration In the variable interleave control storage device described in claim 1, which is used at the time of initialization, all of the memories are initialized by non-interleaved access, and the A variable interleave control storage device comprising: a setting means for setting whether or not interleave access is possible; and a determining means for diagnosing the memory and detecting unimplemented memory and malfunctioning memory to determine the memory capacity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2312990U JPH03116442U (en) | 1990-03-09 | 1990-03-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2312990U JPH03116442U (en) | 1990-03-09 | 1990-03-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03116442U true JPH03116442U (en) | 1991-12-03 |
Family
ID=31526125
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2312990U Pending JPH03116442U (en) | 1990-03-09 | 1990-03-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03116442U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006051779A1 (en) * | 2004-11-10 | 2006-05-18 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile storage device control method, memory controller and nonvolatile storage device |
-
1990
- 1990-03-09 JP JP2312990U patent/JPH03116442U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006051779A1 (en) * | 2004-11-10 | 2006-05-18 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile storage device control method, memory controller and nonvolatile storage device |
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