JPH03116325A - Circuit for multiplication by 2n - Google Patents

Abstract

PURPOSE:To increase the operation speed by using a data memory which divides data to be operated into plural unit data to be operated and stores values obtained by multiplying each unit data to be operated by 2. CONSTITUTION:The product of each unit data C to be operated and 2N is corrected with digit shift value information (g) to obtain a unit operation result (f), and data having the result (f) as lower bits and having digit shift value information (g) as upper bits is stored in a data memory 4. A control part 2 divides data (b) to be operated into unit data (c) to be operated each of which has a prescribed number of digits, and each data (c) is built in an address and is sent to an address lower bit terminal 5b of the data memory 4. Consequently, the unit operation result (f) outputted from the data memory 4 at each time of sending unit data (c) is successively synthesized in serial to obtain the operation result of inputted data (b) to be operated. Since each unit operation result is outputted immediately at the time of input of each unit data to be operated, the operation speed is increased with the required storage capacity of the data memory minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an , relates to an X 2 N arithmetic circuit using a data memory in which arithmetic results are stored in advance at corresponding addresses.

[Prior Art] For example, in a frequency divider or synthesizer, a reference frequency F is output from a reference frequency generator such as a crystal oscillator. Various calculations are performed on the target frequency to obtain the target frequency. In this case, the reference frequency F is generally used to obtain the target frequency. A power-of-2 operation is performed on the value and the number of operations is set. Therefore, in order to improve the response characteristics of frequency dividers and synthesizers, this power of 2 operation (X2N
) must be executed in a short period of time.

Conventionally, this power of 2 operation (X2N) has been executed by a CPU (central processing unit) in software using, for example, an arithmetic program stored in a ROM.

[Problems to be Solved by the Invention] However, as described above, when a power of two operation (X2N) is executed in an arithmetic program, the number of steps in the program increases and the arithmetic processing time becomes longer. If used in frequency generators or synthesizers, the response characteristics will drop significantly.

If it is set to N-3 (X8), the number of program steps will be 30 or more, and the calculation processing time will be very long, about 18 μs.

The present invention was made in view of these circumstances, and
By dividing the operand data into a plurality of unit operand data and storing the value obtained by multiplying each unit operand data by 2N at the location where the unit operand data is the address, the data It is an object of the present invention to provide an X 2 N arithmetic circuit that can greatly improve the arithmetic speed while minimizing the storage capacity required for the memory.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an X 2 N calculation circuit that multiplies operand data consisting of a plurality of digits by 2N (N-integer), and uses calculation type information determined by the N value. The lower bits for the address formed by combining the upper bits indicating the digit shift value information including The unit operand data is multiplied by 2N determined by the operation type information, and the unit operation result is corrected with the digit shift value information.The upper bit is the digit shift value information when the unit operation result is shifted by digits.The synthesized data is A clock signal generator that outputs a clock signal indicating the address sending timing, and a clock signal generator that incorporates each unit of operand data into the lower bits of the address and outputs the lower address of the data memory every time a clock signal is input. In addition to sequentially sending data to the bit terminals, information on the type of operation to be executed is embedded in the upper bits of the address and sent, and a switching signal whose signal level changes only during the address sending period in which the first unit operand data is embedded is sent. The operation type information of the upper bits of the address sent from this control unit and the digit shift value information of the upper bits of the data read from the data memory are input, and in response to the switching signal, the first The operation type information is sent to the address upper bit terminal of the data memory only during the address sending period of the unit operand data, and the digit shift value information is sent to the address upper bit terminal of the data memory after the address sending period of the first unit operand data ends. It is equipped with a switching circuit for transmitting the data, and a latch circuit that is inserted in the transmission path of the digit shift value information to the address terminal of the data memory and holds at least the digit shift value information until the next clock signal is input.

[Operation] In the X 2 N arithmetic circuit configured in this way,
The address input to the data memory is formed by upper bits indicating digit shift value information including operation type information and lower bits indicating unit operand data. Then, corresponding to this address, the unit operation result obtained by multiplying the unit operand data by 2N and corrected with digit shift value information is set as the lower bit, and the digit shift value information when the unit operation result is shifted by digit is set as the upper bit. Data in bits is stored.

Then, the control section divides the operand data into unit operand data having a specified number of digits, incorporates them into an address, and sends them to the address lower bit terminal of the data memory. Digit shift value information outputted from the data memory in the previous clock cycle is applied to the address upper bit terminal of the data memory via a latch circuit and a switching circuit. Therefore, the unit operation result obtained by multiplying the unit operand data from the data memory by 2N and corrected with the digit shift value information in the previous clock signal cycle, and the digit shift value information to be used in the next clock cycle are output. be done.

Note that at the time of sending out the first unit operand data, the digit shift value information obtained in the previous clock signal cycle does not exist, so the operation type information is incorporated into the upper bits of the address from the control unit and switched. It is applied to the address upper bit terminal of the data memory via the circuit.

Therefore, by serially synthesizing the unit operation results output from the data memory each time each unit operand data is sent out, the operation result for the input operand data can be obtained.

[Example code] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a ×2N arithmetic circuit according to an embodiment. In the figure, 1 is a cycle T indicating address sending timing. The clock signal generator 1 outputs a clock signal a having a clock signal a, and the clock signal a output from the clock signal generator 1 is manually inputted to the control section 2. This control section 2 is formed by a kind of microcomputer,
The operand data b inputted from the outside is divided into unit operand data C having a specified number of digits, for example 2. Then, in synchronization with the clock signal a inputted from the clock signal generator 1, each divided unit operand data C is transferred from the lower address terminals A8 to A15 to the data memory 4 via the register 3.
The address is sent to the lower bit terminal 5b of the address. Also, the calculation type information d determined by the input N is sent to the upper address terminal A.
It is sent from O to A7 via the register 6 to the input terminal B of the switching circuit 7. Further, the control section 2 sends a switching signal e to the switching terminal S of the switching circuit 7.

The lower 8 bits of the 16-bit data outputted from the data memory 4 are sent to the receiving section 8 as the unit operation result f for the unit operand data C.

Furthermore, the upper 8 bits of the 16-bit data are the next clock signal period T. It is sent to the latch circuit 9 as digit shift value information g used for the unit operand data C of .

The latch circuit 9 is the upper two of the input digit shift value information g.
The bits are output as an error signal, and the remaining 6 bits are sent to the input terminal A of the switching circuit 7 as new digit shift value information i. Note that the 2-bit value of the error signal is [C]
An error occurs only when H.

The switching circuit 7 is formed of a type of multiplexer, and when a high (H) level switching signal e is applied to the switching terminal S, the digit shift value information i sent from the latch circuit 9 is transferred to the data memory 4. is sent to the address upper bit terminal 5a. Further, when a low (L) level switching signal e is applied to the switching terminal S, the operation type information d sent from the control unit 2 via the register 6 is sent to the address upper bit terminal 5a of the data memory 4. .

In this example, the values of N are N-12), N-2(X4), N-:3(x8), N
=-1 (÷2), N--2 (÷4).

A total of 7 types of calculations are possible: 6 types of N−3 (÷8) and a constant value that outputs the data stored at the specified address as is.

Next, the contents stored in the data memory 4 will be explained using FIGS. 2 and 3.

As shown in FIG. 2, in principle, 16 bits of data are stored for each 16 bit address. Then, each 16-bit address consists of 8 upper bits AD
It is composed of U and 8 lower bits AD, and each 16-bit data is composed of 8 upper bits DO and 8 lower bits DL.

The upper bit ADU of the address indicates digit shift value information i including operation type information d, and the lower bit ADL indicates unit operand data C consisting of two digits. As shown in Fig. 3, the operation type information d is [00] ) I to [01] H is (×2)
, [02] H ~ [05 □ indicates (×4),
[06 CoH ~ [OD] H indicates (x8), [OE]
s~[OF] H indicates (÷2), [lO]□~[
13 pieces H indicates (÷4), [14] H ~ [lB]
H indicates (÷8), and [lC] after H indicates [constant C].

In addition, the lower bit DL of the data is a digit shift in the previous clock signal period To by multiplying the unit operand data C of the corresponding address by 2N times N indicated by the operation type information d specified by the address upper bit ADO. The unit calculation result f of the lower two digits corrected with the value information i is shown. Further, the upper bit DU of the data is digit shift value information g when the calculation value is digit shifted.

Specifically, for an address consisting of the upper bits of [00]H and the lower bits of [581H,
Data consisting of the upper bits of [12] and the lower bits of [12] is set. That is, the upper bit of [00]s indicates that the operation type is N-14', that no digit shift occurred in the operation in the previous clock signal cycle, and the unit operand data C is 56. And the multiplication value is 56X
2-112, so for the lower bit D of the data, [
121H is set as the unit operation result f, and [01]H is set as the digit shift value information g in the upper bit DU of the data. Therefore, the digit shift value information g of this [01]H includes (x2) operation type information d.

Further, in each address after [IC])l in the upper bits of the address, each fixed data as a predetermined constant is stored.

In addition, the lower bit ADL indicating the value of each unit operand data C which is limited to 2 digits or less in decimal notation is ADL in hexadecimal notation.
Since the value -F cannot be taken, an address whose lower bit is the value A-F in hexadecimal notation will contain error data [C
00O] o is stored.

Therefore, when an incorrect unit operand data C is applied to the address lower bit 5b of the data memory 4, this error data [C00O]□ is output, and the upper bit [CO3H of the error data is latched as the digit shift value information g. The signal is sent to the circuit 9, and the latch circuit 9 outputs it as an error signal.

Next, for example, as shown in FIG.
5B×2] will be explained using the time chart of FIG. 4. Since the operand data b has 12 digits, if the specified number of digits is 2, it can be divided into a total of six unit operand data C. Then, each unit calculation data C is sent out in the order of [5B]H.

[41 pieces,, [89 pieces u, [5B]
H, [32] H.

[17] It becomes H. Also, it is N-1. Therefore, the operation type information d output from the control unit 2 becomes [001H.

Incidentally, FIG. 5(b) is a diagram showing the addresses and data of a portion of the data memory 4 necessary for carrying out the above operation. That is, as described above, data [0112]H is stored at address [005B]H, and address [014] formed by the digit shift value information [01co] of this data and the next unit operand data [411H] is stored at address [005B]H.
1] Lower bit obtained by adding digit shift value 1 to H [83]
Data [0083] consisting of digit shift value information of H and [00] without digit shift is stored. Furthermore, the digit shift value information of [00 without digit shift and the next unit operand data [8
9] Address formed by H [0089] Lower bit of the value 178 multiplied by H [78] Data consisting of digit shift value information of [01] which is a digit shift of o and 1 [0178]
is memorized.

In this way, for each data, the unit operand data C of the lower bit of the address is multiplied by 2N, and the value of the lower specified number of digits of the operation value is corrected by the digit shift value information i of the upper bit of the address. It consists of a result f and digit shift value information g when a digit shift occurs.

Therefore, in response to the start of the period To of the clock signal a, the unit operand data C of the first [5B]H and [oo]
)l operation type information d is sent to the data memory 4 and the switching circuit 7 via the respective registers 3 and 6 as the lower bits and upper bits of the address. At the same time, switching signal e
is the L level. Therefore, the switching circuit 7 sends the operation type information d of [00]o input to the input terminal B to the address upper bit terminal 5a of the data memory 4. Therefore, in the first clock signal cycle, the upper bit ADU and lower bit ADL of the address of the data memory 4 are COO □, C56 8, so the data [011
21H is output. And data [0112] H
Among them, the lower bit [i2]H is sent to the receiving unit 8 as the first unit operation result f. Also, the upper bit [
011) 1 is temporarily stored in the latch circuit 9 as digit shift value information g.

Then, when the next clock signal cycle starts, the second unit operand data C of [411o] is sent to the address lower bit terminal 5b of the data memory 4 via the register 3 as the lower bit of the address. Note that the operation type information d of the above [00]H is continuously outputted as the upper bit of the address. At the same time, the switching signal e returns to the original H level. Therefore, in the second clock signal period, the switching circuit 7 changes the C0LE input to the input terminal A.
The H digit shift value information i is sent to the address upper bit terminal 5a of the data memory 4. As a result, in the second clock signal period, the upper bit ADU and lower bit ADL of the address of the data memory 4 are [011H, [4
1] ) 1, so the address [0141] HI:
The stored data [0083] is output. Then, of the data C0 (183]□, the lower bit [8
3 □ is sent to the receiving section 8 as the second unit calculation result f. Furthermore, since no digit shift occurred in the upper bit [00]H, the latch circuit 9 uses it as digit shift value information g of 0.
will be stored once.

When the third clock signal period starts, the unit operation result f for the third unit operand data C and the digit shift value information g to be added to the fourth unit operand data C are calculated. Read from data memory 4.

When the sixth clock signal period ends in a similar manner, six unit operation results f for six unit operand data C are obtained. Then, by combining the six unit operation results in the reverse order, the receiving section 8 obtains the operation result [3465137812] for the operand data b.

Figure 6(a) shows [4B2231
11102.times.4 is a diagram illustrating a calculation procedure, and FIG. 3(b) is a diagram illustrating extracted addresses and data of a portion necessary for carrying out the above operation in the data memory 4. In other words, the operation type information of N-2 is [02]
H ~ [05] Since H, the first unit operation data [
Address [0202] consisting of o and operation type information [02 ko□] [08] as unit operation result f
Data [0208] H consisting of H and digit shift value information [02] H without digit shift is stored. In addition, the address [02B2]H consisting of the fifth unit operation data [62] ) 1 and the digit shift value information [021H without digit shift of the previous clock signal cycle] is set to [4g as the unit operation result f]. ] ) Digit shift value information including digit shift values of 1 and 2 and operation type information [04] Data consisting of H [044
8] H is stored. Digit shift value information of this data [04] Address formed by H and next unit operand data [04] o Unit operation result by adding digit shift value 2 to H [18] □ and digit shift None [u]
Data [0218] H consisting of digit shift value information of H is stored.

The time chart for carrying out the above calculation is almost the same as that shown in FIG. 4, so its explanation will be omitted.

Figure 7(a) shows [123456
78901X8] is a diagram showing the calculation procedure of
b) is a diagram illustrating extracted addresses and data from a portion of the data memory 4 necessary for carrying out the above operation. Calculation procedure and time chart are shown in N-1 and 2 above.
This is almost the same as in the case of .

Figure 8(a) shows [17523
8089713+21, and FIG. 8(b) is a diagram illustrating the address and data of a portion of the data memory 4 necessary for carrying out the above operation. In other words, the operation type information of N--1 is CaE
] H ~ [OF] H, so the address [0E17] H consisting of the first unit operation data [17] H and the operation type information [17] ) I is filled with [08] H as the unit operation result f. Digit shift value information including the digit shift value of 1 and calculation type information [op]) Data consisting of I [0FO8
] H is memorized. Digit shift value information C of this data
OP] □ and the next unit operand data [52] H Address [0P52] Unit operation result obtained by correcting H with digit shift value 1 [781H (=152÷2) and digit shift] Data [0E7B] H consisting of digit shift value information of [OE] H without is stored.

Note that in the case of N x 0, that is, division, the operand data b is divided into two digits from the beginning to obtain each unit operand data C, contrary to the case of N>0. The sending order of each unit operand data C is also reversed for multiplication and arithmetic. However, N
In the case of eo, a correct calculation result can be obtained as in the case of N>0.

Note that FIGS. 9 and 10 are diagrams showing the calculation procedure in the case of N−-2 (÷4) and N−-3 (÷8), and the data necessary to carry out the above calculation in the data memory 4. FIG.

Furthermore, if [Constant] is input as the calculation type to the control unit 2 instead of N, digit movement will not be executed, so [lCO
O] When an address AO to A15 of H or higher is specified, the fixed data stored at the corresponding address in the data memory 4 is read out, and the lower bits of the data are sent to the receiving section 8.

In the X 2 N arithmetic circuit configured in this manner, a unit operation result obtained by multiplying the unit operand data by 2N is stored in the data memory 4 at a position corresponding to the unit operand data. Therefore, a correct operation result can be obtained simply by sequentially sending out each unit operand data obtained by dividing the operand data in synchronization with a clock signal.

That is, the calculation processing speed is the period T of the clock signal a. It is only the time multiplied by the number of divisions of the operand data b. Therefore, compared to conventional arithmetic circuits that perform arithmetic processing using an arithmetic program, the calculation speed can be significantly improved.

In the example circuit, when the setting is N-3, the processing time is about 1 μs, which is significantly shorter than the 18 μs calculated using the calculation program.

Furthermore, it is only necessary to set in the data memory 4 data corresponding to the address where each unit operand data C and the digit shift value information i are combined. Therefore, the required storage capacity of the data memory 4 can be significantly reduced compared to the case where the operation results are stored for each original operand data without dividing it into each unit operand data. Therefore, manufacturing costs can be significantly reduced.

Note that the present invention is not limited to the embodiments described above. As shown in FIG. 11, a latch circuit 9 that stores and holds the digit shift value information g output from the data memory 4 until the next clock signal cycle may be installed between the switching circuit 7 and the data memory 4. .

[Effects of the Invention] As explained above, according to the X 2 N arithmetic circuit of the present invention, the operand data is divided into a plurality of unit operand data, and the value obtained by multiplying each unit operand data by 2N is calculated as follows. A data memory is used that stores unit operand data at a location designated as an address. Therefore, when each unit operand data is input, each unit operation result is immediately output. Therefore,
The calculation speed can be significantly improved while minimizing the storage capacity required for the data memory.

[Brief explanation of drawings]

FIGS. 1 to 10 are X 2 according to an embodiment of the present invention.
Figure 1 is a block diagram showing the overall configuration, Figure 2 is a diagram showing the storage contents of the entire data memory, and Figure 3 is a diagram showing the relationship between operation types and upper addresses. , Figure 4 is a time chart showing the operation, Figure 5 (
a), Fig. 6(a), Fig. 7(a), Fig. 8(a), Fig. 9(a), and Fig. 10(a) are diagrams showing each calculation procedure, and Fig. 5(b). ), FIG. 6(b), FIG. 7(b), FIG. 8(b), FIG. 9(b), and FIG. 10(b) are the parts of the data memory 4 required for the corresponding calculation, respectively. FIG. 11 is a block diagram showing an X 2 N arithmetic circuit according to another embodiment of the present invention. 1... Clock signal generator, 2... Control unit, 3, 6
...Register, 4...Data memory, 7...Switching circuit, 8...Receiving circuit, 9.19...Latch circuit.

Claims (1)

[Scope of Claims] In a ×2^N arithmetic circuit that multiplies operand data consisting of a plurality of digits by 2^N (N = integer), an upper bit indicating digit shift value information including operation type information determined by the N value. and lower bits indicating each unit operand data when the operand data is divided into unit operand data of a specified number of digits, the lower bits are converted into the unit operand data and the operation is performed. Data that stores the combined data in which the unit operation result is multiplied by 2^N determined by the type information and corrected with the digit shift value information, and the upper bit is the digit shift value information when the unit operation result is shifted by digit. a memory; a clock signal generator that outputs a clock signal indicating address sending timing; and a clock signal generator that incorporates each unit operand data of the operand data into the lower bits of the address and generates the lower address of the data memory every time the clock signal is input. In addition to sequentially sending data to the bit terminals, information on the type of operation to be executed is embedded in the upper bits of the address and sent, and a switching signal whose signal level changes only during the address sending period in which the first unit operand data is embedded is sent. a control unit that inputs operation type information of the upper bits of the address sent from the control unit and digit shift value information of the upper bits of the data read from the data memory, and in response to the switching signal, The operation type information is sent to the address upper bit terminal of the data memory only during the address sending period of the first unit operand data, and the digit shift value information is sent to the address sending period of the first unit operand data. A switching circuit that sends data to the address upper bit terminal of the data memory and a transmission path for the digit shift value information to the address terminal of the data memory, and holds at least this digit shift value information until the next clock signal input. ×2^N arithmetic circuit equipped with a latch circuit.