JPH03115468U - - Google Patents
Info
- Publication number
- JPH03115468U JPH03115468U JP2547790U JP2547790U JPH03115468U JP H03115468 U JPH03115468 U JP H03115468U JP 2547790 U JP2547790 U JP 2547790U JP 2547790 U JP2547790 U JP 2547790U JP H03115468 U JPH03115468 U JP H03115468U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- mixing
- video
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Studio Circuits (AREA)
Description
第１図は本考案の一実施例のスーパーインポー
ズ回路の回路図、第２図はそのタイミングチヤー
ト、第３図は従来のスーパーインポーズ回路の回
路図である。
Ａ……ビデオスイツチ回路、Ｂ……混合回路、
１……インポーズ信号の入力端子、２……ビデオ
信号の入力端子、３……出力端子、４……タイミ
ング信号の入力端子、５……ビデオ信号の入力端
子、６……インポーズ信号の入力端子、７……制
御端子。
FIG. 1 is a circuit diagram of a superimpose circuit according to an embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a circuit diagram of a conventional superimpose circuit. A...Video switch circuit, B...Mixed circuit,
1... Input terminal for impose signal, 2... Input terminal for video signal, 3... Output terminal, 4... Input terminal for timing signal, 5... Input terminal for video signal, 6... Input terminal for impose signal. Input terminal, 7...control terminal.
Claims (1)
を混合する混合回路と、該混合回路で得られた混
合信号と上記ビデオ信号とをスイツチングするビ
デオスイツチ回路とを具備し、上記混合回路にお
ける混合比率を制御する手段を設けたことを特徴
とするスーパーインポーズ回路。 A mixing circuit that inputs a video signal and an impose signal and mixes both signals, and a video switch circuit that switches the mixed signal obtained by the mixing circuit and the video signal, and the mixing ratio in the mixing circuit. A superimpose circuit characterized in that it is provided with means for controlling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990025477U JPH0623101Y2 (en) | 1990-03-13 | 1990-03-13 | Superimpose circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990025477U JPH0623101Y2 (en) | 1990-03-13 | 1990-03-13 | Superimpose circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03115468U true JPH03115468U (en) | 1991-11-28 |
| JPH0623101Y2 JPH0623101Y2 (en) | 1994-06-15 |
Family
ID=31528411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990025477U Expired - Lifetime JPH0623101Y2 (en) | 1990-03-13 | 1990-03-13 | Superimpose circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0623101Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5939573U (en) * | 1982-09-06 | 1984-03-13 | 三洋電機株式会社 | Character signal recording circuit |
| JPS63276376A (en) * | 1987-05-07 | 1988-11-14 | Sharp Corp | Superimposing system |
-
1990
- 1990-03-13 JP JP1990025477U patent/JPH0623101Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5939573U (en) * | 1982-09-06 | 1984-03-13 | 三洋電機株式会社 | Character signal recording circuit |
| JPS63276376A (en) * | 1987-05-07 | 1988-11-14 | Sharp Corp | Superimposing system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0623101Y2 (en) | 1994-06-15 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |