JPH03109765A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent drop in a manufacture yield caused by a residual accumulated electrode material by selectively removing an insulation film on a region except a part required for forming a gap under a storage electrode prior to attaching a conductor layer. CONSTITUTION:Prior to patterning of a storage electrode 12, a region which is not needed to form a gap 13 under the electrode 12, for example an SiO2 film 16 for forming the gap on a region A2 for forming a peripheral transistor Tr2, is selectively removed. Therefore at the time of patterning the storage electrode 12, a residual caused by dust at the time of exposing a residual 112B of a polysilicon layer being a material of the electrode 12 to be left and attached to a step on a region other than a memory cell forming region A1 is immediately attached onto an Si3N4 film 10 which does not solve in HF solution. Therefore the device is free from lift-off due to wet etching treatment with the HF solution at the time of forming the gap 13, as well as the Si layer residual 112B, etc., can be prevented from attaching via etching solution to an important part on a substrate such as under the electrode 12. Thus a manufacture yield can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the manufacturing method of semiconductor devices, especially the manufacturing method of DRAM having stacked capacitors, when forming a void part under the storage electrode by wet etching, the storage electrode material is The purpose of this method is to prevent the residue from being mixed into the etching solution and to prevent the reduction in manufacturing yield caused by the accumulation of storage electrode material residue on important parts. a step of sequentially laminating and forming a first insulating film, a second insulating film that does not dissolve in a hydrofluoric acid-based liquid, and a third insulating film that dissolves in a hydrofluoric acid-based liquid; , forming an opening that penetrates the first insulating film and exposes the surface of the semiconductor substrate;
a step of depositing a conductive layer on the third insulating film, patterning the conductive layer so that the conductive layer extends from the semiconductor substrate surface exposed in the opening onto the third insulating film; A step of forming a storage electrode having an end on an insulating film, selectively dissolving and removing the third insulating film with a hydrofluoric acid solution to extend the third insulating film of the storage electrode. a step of forming a dielectric film on the exposed surface of the storage electrode; a step of filling the void under the storage electrode on the second insulating film; In a method for manufacturing a semiconductor device, the method includes the step of forming a counter electrode made of a conductor layer that extends to cover the upper part of the semiconductor device. The third insulating film is configured by adding a step of selectively removing the third insulating film in a region other than a portion necessary for the third insulating film.

[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing a DRAM having a stacked capacitor.

In highly integrated DRAM, in order to improve reliability, a capacitor structure that can obtain large storage capacitance with a small cell size is desired. A stacked capacitor structure is provided in which the lower surface of the storage electrode in addition to the upper surface and side surfaces of the storage electrode also contributes to the capacitance.

FIG. 2 is a schematic side sectional view of a memory cell having a stacked capacitor with the above structure, where ■ is, for example, p-type silicon (
St) substrate, 2 is a field oxide film that isolates elements;
3 is a gate oxide film, 4 is a gate electrode (word line) made of poly-Si, etc., and 5 is a first nI to which a bit line is connected.
6 is the second n0 type source/drain region connected to the capacitor, 7A is the first glabella insulating film made of silicon dioxide (SiOz), etc., and 8 is the first bit line connection. 9 is a bit line made of polycide or the like, 7B is a second glabella insulating film made of 5i02 or the like, 10 is a silicon nitride (SisNa) film, 11
12 is a storage electrode made of poly-Si, etc., and 13 is a storage electrode 12 and Si3.
The void 14 formed between the N4 film 10 and the N4 film 10 is made of, for example, S
t, N, and 5i02, 15 is polyS
Tr indicates a cell transistor having an MO3 structure, and C□ indicates a cell capacitor having a stacked structure in which a storage electrode is embedded in the counter electrode via a dielectric film.

[Conventional technology]

A cell capacitor in a DRAM cell having the above structure has conventionally been formed by the method shown below.

Referring to FIG. 3(a), a cell transistor (T
r) is formed, a first glabellar insulating film 7A is formed to cover this transistor, and a first contact window 8 exposing the first source/drain region 5 is formed in this first glabellar insulating film 7. A bit line 9 made of polycide or the like is formed on this contact window 8, and after forming a second glabellar insulating film 7B on that surface, this first glabellar insulating film 7A and a second glabellar insulating film 7A are formed. 7B, a 5iJn film 10 corresponding to a second insulating film that is not dissolved in hydrofluoric acid (HF)-based liquid, and a third insulating film 7 that is soluble in HF-based liquid. After forming the corresponding 5i02 film 16, the above Sing
Film 16.5iJ4 film 15 and first and second interlayer insulating films 7
A second contact window 11 is formed to penetrate through A and 7B and expose the second source/drain region 6.

Refer to FIG. 3(b) Next, a poly-Si layer is formed on this substrate, and this poly-Si layer is
After introducing conductivity into the i-layer by introducing n-type impurities at a high concentration, patterning is performed to form a storage electrode 12 whose end extends to the top of the word line 4 on the second contact window ll. .

Refer to FIG. 3(C) Next, this substrate was immersed in an HF-based liquid, and the 5in2
Film 16 is selectively etched away. Here 5iOz
A void portion 13 is formed below the storage electrode 12 extending on the film 16 .

See Figure 2 Next, there is a small amount of Si and N on the exposed surface of the storage electrode 12.

A dielectric film 14 made of and SiO□, etc. is formed, and poly 5iJi is vapor-phase grown on this substrate to fill the void 13 under the storage electrode 12, cover the storage electrode 12, and extend over the substrate. A method of forming the counter electrode 15 was used.

[Problem to be solved by the invention]

However, the above conventional method has the following problems.

That is, the patterning of the storage electrode 12 (FIG. 3(b)
In the resist film exposure step (see), the fourth
As shown in Figure (a), foreign matter 19 is attached to, for example, the scribe line 18 where the poly-Si layer in the exposure mask (reticle) 17 is removed, and an unexposed region 21 is formed in the positive resist film 20 below. If this happens, that portion will remain as a resist residue after development, so after patterning the storage electrode using this resist film as a mask, a pattern is formed on the SiO2 film 16 on the scribe line 18 as shown in FIG. 4Cb). Island-shaped poly-Si residues 112A remain attached.

Further, as described above, the patterning of the storage electrode 12 is performed by RIE.
Since this is done by processing, as shown in FIG. 4(b), sidewall-shaped poly-Si residues are formed on the stepped portion of the 5iOz film 16 formed on the stepped portion of the field oxide film 2 that defines the scribe line 18. 112B remains attached.

Therefore, next, a FIF-based etching solution was used to
n. In the step of dissolving and removing the film 16 to form a void 13 under the storage electrode 12 (see FIG. 3(C)), as shown in FIG. 4(C), the polySt residue 112A and 112B is lifted off and mixed into the etching solution, and the poly-Si residues 112A, 112B, etc. infiltrate and adhere to the lower part of the storage electrode 12, and are later removed from the storage electrode 2.
It may deteriorate the performance of the dielectric film 14 formed on the exposed surface of the DRAM, or it may adhere to important parts of the substrate, causing gaps between wirings, disconnection of wiring, poor insulation of the insulating film, etc.
There was a problem in that the manufacturing yield of the product decreased. (In FIGS. 4(a) to (C), l is the Si substrate, 2 is the field oxide film, 7 is the glabella insulating film, 1° is the St J film, 11
2 indicates poly5iJii. ) Therefore, in the present invention, when forming a void under the storage electrode by wet etching,
It is an object of the present invention to prevent residues of storage electrode material from being mixed into an etching solution, thereby preventing a decrease in manufacturing yield due to the residues of storage electrode material.

[Means to solve the problem]

The above problem is to sequentially form a silicon oxide-based first insulating film, a second insulating film that does not dissolve in a hydrofluoric acid-based solution, and a third insulating film that dissolves in a hydrofluoric acid-based solution on a semiconductor substrate. a step of laminating and forming, a step of forming an opening that penetrates the third, second, and first insulating films and exposes the surface of the semiconductor substrate; and a step of forming the third insulating film including the inner surface of the opening. a step of depositing a conductive layer on the film, patterning the conductive layer so that the third insulating film extends from the semiconductor substrate surface exposed in the opening onto the third insulating film; a step of forming a storage electrode having an end portion on top, selectively dissolving and removing the third insulating film with a hydrofluoric acid-based solution, and removing a portion of the storage electrode that extended over the third insulating film; a step of forming a dielectric film on the exposed surface of the storage electrode; a step of forming a dielectric film on the exposed surface of the storage electrode; In a method for manufacturing a semiconductor device, which includes a step of forming a counter electrode made of a conductor layer that covers and extends, prior to depositing the conductor layer,
This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which includes a step of selectively removing the third insulating film in a region excluding at least a portion necessary for forming the void below the storage electrode.

[For production]

That is, in the method of the present invention, in order to form a void in the lower part of the storage electrode, the third layer is dissolved in the OF-based liquid and is formed extending from the lower region of the storage electrode over the entire substrate surface.
After removing in advance the portions of the insulating film that are not necessary for forming the above-mentioned voids and exposing the second insulating film that does not dissolve in the IIF-based liquid in the portions of , a layer for forming storage electrodes is placed on this substrate. A conductive layer is formed, and this conductive layer is patterned to form a storage electrode.

Therefore, when patterning the storage electrode, sidewall-like residues of the conductor layer remaining on step portions in scribe lines and other areas where the storage electrode is not formed, island-like residues caused by dust during exposure, etc., are removed by the IF system liquid. The third insulating film is deposited directly on the second insulating film, which does not dissolve in O2.
The residue of the conductive layer is not lifted off when removing it with an F-based liquid to form a void below the storage electrode.

Therefore, residues of the conductor layer will not adhere to the lower part of the storage electrode or other important parts, preventing performance deterioration of the semiconductor device and improving manufacturing yield.

〔Example〕

The following is an example of the present invention as shown in FIGS. 1(a) to (f).
A detailed description will be given with reference to the process cross-sectional diagram shown in FIG.

DR with stacked capacitors according to the method of the present invention, see FIG. 1(a).
When forming the AM, for example, on the p-type Si substrate 1, there is a memory cell formation area A, a peripheral transistor formation area A!
A field oxide film 2 is formed to separate and expose the gate oxide film 3, a word line 4, and a first n+ type source/drain region 5 in the memory cell formation area A1 using a method similar to the conventional method.
and a second n0 type source/drain region 6 are formed, and a gate oxide film 103, a gate electrode 104, and a gate electrode 104 are formed in the peripheral transistor formation region A2.
On a substrate on which a peripheral transistor Tr consisting of a 1 type source region 105 and an n0 type drain region 106 is formed,
For example, a thickness of about 1,000 0S is produced using the normal vapor phase growth method.
A first interlayer insulating film 7^ made of an iO□ film is formed, and the first interlayer insulating film 7A of the cell transistor Tr is
A first contact window 8 that exposes the source/drain region 5 is formed, and a bit line 9 made of polycide or the like is connected to the contact window 8. The second layer is made of 0SiO2 film.
The first and second interlayer insulating films 7 form a glabellar insulating film 7B.
A and 7B correspond to the first insulating film), and then a discolored Si3N film IO with a thickness of about 500 mm is deposited on the second interlayer insulating film 7B as a second insulating film that is not dissolved in the IP-based liquid. A third insulating film 16 is formed by phase growth, and then, as a third insulating film, which is dissolved in an IP-based liquid, an SiO discoloration film 16 having a thickness of about 500 to 1000 layers is formed by vapor phase growth on the Si, N film 10. Then, the above SiO□ film 16, Si3
A second capacitor connection capacitor penetrating the N4 film IO and the glabella insulating film 7 consisting of the first interlayer insulating film 7A and the second interlayer insulating film 7B to expose the second source/drain region 6 of the cell transistor Trl. A contact window 11 is formed.

Note that the steps up to this point are the same as the conventional method.

Referring to FIG. 1), a gap is then formed on the substrate under the storage electrode, for example, to a memory cell forming area.

A resist mask 22 is formed to cover the Sing film 16, and a wet etching process is performed using an IP-based liquid to selectively remove the Sing film 16 on a region not necessary for forming the above-mentioned void (in the figure, only the formation region At of the peripheral transistor Trt is shown as an example). to be removed.

Refer to FIG. 1(C) Next, after removing the resist mask 22, a 0S poly-Si layer with a thickness of about 1000 layers is grown in a vapor phase on this substrate, and N9 type conductivity is added to this poly-Si layer by, for example, ion implantation. After applying this poly-Si layer, RIB is used as an etching means.
Extending on the Sing film 16 from the second source/drain region 6 surface of the cell transistor Tr exposed in the second contact window 11 by patterning by a normal photolithography process using processing, this Sin, Membrane 1
A storage electrode 12 having an end portion on top of the storage electrode 12 is formed. On this occasion,
For example, sidewall-like poly-Si residues 112B remain directly attached to the step portion of the Si3N4 film 10 on the edge of the field oxide film 2 defining the peripheral transistor formation region Az.

As mentioned above, if there is dust on the mask during exposure, island residues will also remain on the SiJ and film IO, but this will be omitted here.

Referring to FIG. 1(d), the remaining SiO□ film 16 is removed by wet etching using a F-based solution as before, and the storage electrode I
Form a discolored cavity at the bottom of 2 with a height of about 500 to 1000 people. At this time, the side wall-shaped poly-Si residue 112B
Ba5i3N4If! Since it is directly attached to 10, it will not be lifted off and will remain attached.

Referring to FIG. 1(e), the storage electrode 12 is then deposited in a conventional manner, for example, by a vapor phase growth method.
A SiJ film with a thickness of approximately 80 mm is formed on the exposed surface and the upper surface of the substrate, and the surface portion of this SiJ film is thermally oxidized (SiJ4
A dielectric film 14 made of +5 iOz) is formed on the substrate, and then a dielectric film 14 with a thickness of 2 oz.
A layer of about 000 polySt is formed, and this polySiN is given n0 type conductivity by, for example, ion implantation, and then patterned by normal photolithography to extend to and above the memory cell formation area. A counter electrode 15 is formed.

Referring to FIG. 1(f), a first covering insulating film 23 is then formed on this substrate in the conventional manner, and this first covering insulating film 13 and dielectric film 14, S
A third contact window 24 and a fourth contact window 25 penetrating the i3N4 film 10 and the interlayer insulating film 7 to expose the source region 105 and drain region 106 of the peripheral transistor Trz are formed, and the above-mentioned process is performed by normal wiring forming means. A source wiring 26 and a drain wiring 27 are formed on the contact windows 24 and 25.

Thereafter, a second covering insulating film (not shown) is formed, and the RAM is completed by the method of the present invention.

As shown in the above embodiment, in the method of the present invention, prior to patterning of the storage electrode 12, the above-mentioned pattern on the peripheral transistor Trz formation region A2, which is not necessary for forming the cavity 13 under the storage electrode 12, is removed. Since the Sing film 16 for forming the void is selectively removed, the storage electrode 1
Residues of the polySt layer 112B, which is the material of the storage electrode, remaining on the stepped portions of areas other than the memory cell formation area A during patterning in step 2 and residues due to dust during exposure (not shown) are HP-based. Si3N that does not dissolve in liquid
4 is deposited directly on the film lo, so it is not lifted off by the wet etching process using IIF-based liquid when forming the void 13, and therefore the lower part of the storage electrode and other important parts on the substrate are not lifted off. This prevents the poly-SiN residue 112B from adhering to the etching solution via the etching solution.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a lifted capacitor having a configuration in which a storage electrode is embedded in a counter electrode through a dielectric film, and the upper surface, side surface, and lower surface of the storage electrode contribute to capacitance. When manufacturing a DRAM using this method, deterioration of capacitor performance, short circuit between wirings, disconnection of wiring, poor insulation of an insulating film, etc. due to adhesion of residues of the conductor layer constituting the storage electrode are prevented, and the manufacturing yield of the above-mentioned DRAM is improved. .

[Brief explanation of drawings]

FIGS. 1(a) to (f) are process sectional views of an embodiment of the method of the present invention. FIG. 2 is a schematic side sectional view of a stacked capacitor type DRAM cell. FIGS. 3(a) to (C) is a process cross-sectional diagram of the conventional method, the fourth
The figures (a) to (C) are process cross-sectional views showing conventional problems. In the figure, ■ is a P-type Si substrate, 2 is a field oxide film, and 3 is a P-type Si substrate.
is the gate oxide film, 4 is the word line, and 5 is the n9 type first
, 6 is the n3 type second source/drain region, 7^, 7B, 7 is the interlayer insulating film, 8.11 is the contact window, 9 is the bit line, '10 is the 5iJa film, 12 is the storage Electric bridge, 13 is a gap, 14 is a dielectric film,
15 is a counter electrode, 16 is a Si0g film, 22
112B is a resist mask, 112B is a sidewall poly-Si residue, At is a memory cell formation region, and At is a peripheral transistor formation region. Sufu・lkudo temporary yapashida type DRAM / 1 size 1\ip
11 All Sections 2 Ikadake Works I No. 5

Claims (1)

[Scope of Claims] A first insulating film made of silicon oxide, a second insulating film that does not dissolve in a hydrofluoric acid solution, and a third insulating film that dissolves in a hydrofluoric acid solution, on a semiconductor substrate. forming an aperture that penetrates the third, second, and first insulating films and exposes the surface of the semiconductor substrate; a step of depositing a conductive layer on the third insulating film, patterning the conductive layer so that the conductive layer extends from the semiconductor substrate surface exposed in the opening onto the third insulating film; a step of forming a storage electrode having an end on an insulating film, selectively dissolving and removing the third insulating film with a hydrofluoric acid-based solution so that the third insulating film extends over the third insulating film of the storage electrode; a step of forming a dielectric film on the exposed surface of the storage electrode; a step of filling the void under the storage electrode on the second insulating film; A method for manufacturing a semiconductor device comprising a step of forming a counter electrode made of a conductor layer extending to cover the upper part, the gap being formed at least under the storage electrode prior to depositing the conductor layer. 1. A method of manufacturing a semiconductor device, comprising the step of selectively removing the third insulating film in a region other than a portion necessary for the third insulating film.