JPH03109423U - - Google Patents
Info
- Publication number
- JPH03109423U JPH03109423U JP1920290U JP1920290U JPH03109423U JP H03109423 U JPH03109423 U JP H03109423U JP 1920290 U JP1920290 U JP 1920290U JP 1920290 U JP1920290 U JP 1920290U JP H03109423 U JPH03109423 U JP H03109423U
- Authority
- JP
- Japan
- Prior art keywords
- transmission circuit
- adder
- subtractor
- signal
- time constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 9
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図は本考案の圧縮回路を示すブロツクダイ
ヤ図、第２図は従来の圧縮回路を示すブロツクダ
イヤ図である。
３０……第１の伝送回路、３１，３２……時定
数回路Ｒ１，Ｃ１、３３，４５……低域通過フイ
ルタ、３４……第１加減算器、３５……第２加減
算器、４０……第２の伝送回路、４１，４２……
ダイオード振幅制限回路、４３，４４……時定数
回路Ｒ２，Ｃ２、５０……第３の伝送回路、５１
……高域通過フイルタ。
FIG. 1 is a block diagram showing a compression circuit of the present invention, and FIG. 2 is a block diagram showing a conventional compression circuit. 30...First transmission circuit, 31, 32...Time constant circuit R1, C1, 33, 45...Low pass filter, 34...First adder/subtractor, 35...Second adder/subtractor, 40... Second transmission circuit, 41, 42...
Diode amplitude limiting circuit, 43, 44... Time constant circuit R2, C2, 50... Third transmission circuit, 51
...High pass filter.
Claims (1)
数を有し信号の低域成分を通過する低域通過フイ
ルタからなる第１の伝送回路と、前段に振幅制限
器を有し上記第１伝送回路と同一の時定数とフイ
ルタを備えた第２の伝送回路と、信号の高域成分
を通過する高域通過フイルタからなる第３の伝送
回路と、上記第１第２伝送回路出力の差成分を取
り出す第１の加減算器と、該第１の加減算器出力
と上記第３伝送回路出力の差成分を取り出す第２
の加減算器と、を設けたことを特徴とする圧縮回
路。 a first transmission circuit consisting of a low-pass filter connected in parallel to the input signal, each having a time constant and passing a low-frequency component of the signal; and the first transmission circuit having an amplitude limiter at the front stage; A second transmission circuit having the same time constant and filter, a third transmission circuit consisting of a high-pass filter that passes high-frequency components of the signal, and extracting the difference component between the outputs of the first and second transmission circuits. a first adder/subtractor; and a second adder/subtractor for extracting a difference component between the first adder/subtracter output and the third transmission circuit output.
A compression circuit characterized in that it is provided with an adder/subtractor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1920290U JPH03109423U (en) | 1990-02-27 | 1990-02-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1920290U JPH03109423U (en) | 1990-02-27 | 1990-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03109423U true JPH03109423U (en) | 1991-11-11 |
Family
ID=31522336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1920290U Pending JPH03109423U (en) | 1990-02-27 | 1990-02-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03109423U (en) |
-
1990
- 1990-02-27 JP JP1920290U patent/JPH03109423U/ja active Pending
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