JPH03109186U - - Google Patents
Info
- Publication number
- JPH03109186U JPH03109186U JP1780590U JP1780590U JPH03109186U JP H03109186 U JPH03109186 U JP H03109186U JP 1780590 U JP1780590 U JP 1780590U JP 1780590 U JP1780590 U JP 1780590U JP H03109186 U JPH03109186 U JP H03109186U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- reference signal
- phase
- error
- reception system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 4
- 230000010363 phase shift Effects 0.000 claims 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Feedback Control In General (AREA)
- Radar Systems Or Details Thereof (AREA)
- Radio Relay Systems (AREA)
Description
第１図は本考案の一実施例による追尾受信装置
のブロツク図、第２図は第１図のデイジタル移相
器の構成例を示すブロツク図、第３図は従来の追
尾受信装置のブロツク図である。
１……第１中間周波数増幅器、２，２Ａ，１０
……混合器、３……第２中間周波増幅器、４，４
Ｃ……位相検波器、５，１３……ローパスフイル
タ、６……電圧制御発振器、７……第１の基準信
号発振器、８……第２の基準信号発振器、９……
分周器、１１……帯域ろ波器、１２……ＡＧＣ回
路、１４……ＡＣ増幅器、１５Ｃ，１５Ｄ……復
調器、１６……π／２移相器、１７……移相器、
２０……デイジタル移相器、２１……全加算器、
２２……レジスタ、２３……ラツチ回路。
FIG. 1 is a block diagram of a tracking receiver according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the digital phase shifter shown in FIG. 1, and FIG. 3 is a block diagram of a conventional tracking receiver. It is. 1...first intermediate frequency amplifier, 2, 2A, 10
...Mixer, 3...Second intermediate frequency amplifier, 4,4
C... Phase detector, 5, 13... Low pass filter, 6... Voltage controlled oscillator, 7... First reference signal oscillator, 8... Second reference signal oscillator, 9...
Frequency divider, 11...band filter, 12...AGC circuit, 14...AC amplifier, 15C, 15D...demodulator, 16...π/2 phase shifter, 17...phase shifter,
20...Digital phase shifter, 21...Full adder,
22...Register, 23...Latch circuit.
Claims (1)
を所定の基準信号をもとに位相検出し、前記アン
テナを目標方位に指向させるための追尾受信装置
において、 前記和信号から位相検出信号を得るための基準
となる第１の基準信号と第２の基準信号との和の
基準信号を発生し、かつ、前記第１の基準信号が
前記誤差信号から位相誤差検出信号を得るための
基準ともなる基準信号発生手段と、前記位相誤差
検出信号からＸ軸およびＹ軸成分の誤差信号を同
期検出する復調器の基準信号となるそれぞれ第３
の基準信号および第４の基準信号を前記第２の基
準信号をもとに発生するデイジタル移相手段とを
有することを特徴とする追尾受信装置。 (2) 前記デイジタル移相手段が和信号受信系と
誤差信号受信系の移相差情報を記憶しているレジ
スタと、前記第２の基準信号を１／２分周ごとに
分周したＮ（Ｎは整数）個の基準分周信号ならび
に前記レジスタの移相差情報を入力してＮ個の前
記基準分周信号を全加算して前記第３の基準信号
を出力し、さらにＮ−１個の前記基準分周信号を
加算して、第５の基準信号を出力する全加算器と
、前記第５の基準信号をラツチしてπ／２移相さ
れた前記第４の基準信号を出力するラツチ回路と
を有することを特徴とする請求項１記載の追尾受
信装置。[Claims for Utility Model Registration] (1) A tracking receiver for detecting the phase of a sum signal and an error signal obtained from an antenna based on a predetermined reference signal, and for directing the antenna to a target direction, comprising: A reference signal that is the sum of a first reference signal and a second reference signal is generated as a reference for obtaining a phase detection signal from a signal, and the first reference signal is a phase error detection signal from the error signal. a reference signal generation means which also serves as a reference for obtaining the phase error detection signal, and a third third signal which serves as a reference signal for a demodulator that synchronously detects the error signals of the X-axis and Y-axis components from the phase error detection signal.
and digital phase shifting means for generating a reference signal and a fourth reference signal based on the second reference signal. (2) The digital phase shift means has a register storing phase difference information between the sum signal reception system and the error signal reception system, and a register that stores the phase difference information of the sum signal reception system and the error signal reception system, and N (N is an integer) reference frequency-divided signals and phase shift difference information of the register are inputted, the N reference frequency-divided signals are all added together to output the third reference signal, and the N-1 reference frequency-divided signals are outputted. a full adder that adds reference frequency-divided signals and outputs a fifth reference signal; and a latch circuit that latches the fifth reference signal and outputs the fourth reference signal phase-shifted by π/2. The tracking receiving device according to claim 1, characterized in that it has the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1780590U JPH03109186U (en) | 1990-02-22 | 1990-02-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1780590U JPH03109186U (en) | 1990-02-22 | 1990-02-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03109186U true JPH03109186U (en) | 1991-11-08 |
Family
ID=31520986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1780590U Pending JPH03109186U (en) | 1990-02-22 | 1990-02-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03109186U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6363069A (en) * | 1986-09-03 | 1988-03-19 | Hitachi Metals Ltd | Magnet roll |
-
1990
- 1990-02-22 JP JP1780590U patent/JPH03109186U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6363069A (en) * | 1986-09-03 | 1988-03-19 | Hitachi Metals Ltd | Magnet roll |
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