JPH03105615A - Composite arithmetic circuit of multiplication and addition provided with maximum value or minimum value detecting function - Google Patents

Abstract

PURPOSE:To eliminate the unbalance of a load between adders at the time of FIND instruction processing by placing separately a selector circuit and a comparing circuit in primary and secondary adders, respectively. CONSTITUTION:A selector circuit 18 is provided in a primary adder 14, and a comparing circuit 19 is provided in a secondary adder 15. In the adder 15, input data (ai), (bi) are brought to large/small comparison by the comparing circuit 19 of the inside, and a selecting signal 20 for showing whether (ai) is selected or (bi) is selected is outputted, and sent out to the selector circuit 18 of the adder 14. In the selector circuit 18, one of the input data (ai), (bi) determined by the selecting signal 20 is selected, and it is outputted as output data (ci). Accordingly, when respect to each adder 14, 15, a load is dispersed to both of them at the time of executing a FIND instruction. In such a way, the unbalance of the load between primary and secondary adders can be obviated.

Description

[Detailed description of the invention] (1!t W) FIN to find the maximum or minimum value in a series of data
Concerning multiplication and addition complex arithmetic circuits with high-speed processing functions for D instructions. The purpose is to eliminate the load imbalance between the primary and secondary adders during FIND instruction processing. In a multiplication and addition complex operation circuit including a multiplier and two adders, primary and secondary. One of the two adders mentioned above is equipped with a comparison circuit that compares the magnitude of the two input data and outputs the result. Also, above 2
In the other of the two adders. A selector circuit is provided that selects and outputs one of the two input data based on the output of the comparison circuit. When processing an instruction to detect the maximum or minimum value in a series of data, we designed the comparison circuit and selector circuit provided in the two adders mentioned above to be functionalized. The purpose is to improve the addition and decomposition calculation circuit. [Industrial Application Field] The present invention... Regarding vector arithmetic circuits used in information processing devices. In particular, it relates to multiplication and addition complex arithmetic circuits capable of high-speed processing of the FIND command to find the maximum or minimum value in a series of data. The process of finding the maximum or minimum value in a series of data is. Attempting to implement this using software would take a considerable amount of time and would be inefficient. on the other hand. This processing is realized using a dedicated hardware circuit.
In order to increase the speed, this processing is not performed very often, so the cost performance is poor. There's a problem. Multiply there. Addition. In order to process mixed operations of multiplication and addition at high speed, the pipeline mechanism of the multiplication and addition complex operation circuit provided in the information processing device is utilized, and the minimum circuit required for processing the FIND instruction is added to this pipeline mechanism. Add. This allows them to be functionalized when necessary. The present invention solves such multiplication and [prior art] as shown in FIG. A conventional example of a pipeline horizontal multiplication and addition complex arithmetic circuit with a FIND instruction processing function, which is the object of the present invention, is shown below. In Figure 3, 1 is the same circuit for multiplication and addition compound operations. 2
is a vector register. The data in vector register 2 is . The data is read out in parallel from each port of register 2M, register 3M, and register 2A and input to the multiplication and addition complex operation circuit l. Multiplication and addition 3￥Compound operation circuit 1 (7) Basic operation J
If the data is represented by port registers of 2M, 3M, and 2A, the a function will be as follows. 2M*3M, 2M (3M)+2A, 2M13
The purpose is to perform operations such as M+2A, but in addition, FIN
A function for processing D instructions is added. The multiplication and addition complex operation circuit 1 is . Multiplier 3 and . A carry lookahead adder (denoted as CPA) 4, which constitutes the primary adder, and . Carry look-ahead addition that constitutes the secondary adder'JT. vessel (represented by CPA) 5 and. Normal type adder (S
It is composed of 6 (represented by UM). Here, two primary and secondary adders are provided for l multipliers. This is to increase the speed by operating the addition stage in parallel. The two inputs of multiplier 3 are connected to registers 2M and 3M, respectively. The output is commonly connected to the human power of each of CI3A4 and CPA5. In addition, each other input of CPA4.5 is commonly connected to register 2A.
Furthermore, a path is provided from each output of CPA4.5 to vector register 2, allowing the output of CPA to be written. Note that the output of CPA4 is also connected to the input of SUM6. When performing complex operations such as multiplication and addition using these rules. Multiplier 3 for data in registers 2M and 3M
Multiply by The result (2M*3M) is half clock (
By alternately transmitting data from CPA4 and CPA5 (τ/2) to each human power of CPA4 and CI) A5 and synchronizing with this, data from register 28 of ζ5 is alternately supplied to the other human power of CPA4 and CPA5. )A, 1.5 are added in parallel with each clock τ, and the compound operation (2M*3M+2
person) can be moved to the next line at high speed. Next, we will explain the circuit and functional operation when processing the F I N +) command. The basic circuit structure for performing addition in CPA4 is well known, so a description thereof will be omitted. Inside adder 8. A comparison circuit 9 that compares the magnitude of two input data ai and bi, and a select circuit lO that selects one of the two input data; >i and bi according to the output of the comparison circuit 9 are added. When executing the FIND instruction, two vector data (a61a++...
・air m, all), (be, bl+ +++
, bl+ +・b, l) from one of registers 2M and 3M and register 2A. Each is input to the multiplication and addition complex operation circuit 1. Multiplier 3 receives one vector data a@+al+...
a1. ..., make an through bus to CPA4. The other vector data be, b+,..., bi,...b
n is input directly to CPA4. Each vector data is .
They are respectively input in parallel to the comparison circuit 9 and the selector circuit IO. The comparison circuit 9 is. Each pair of elements (as.b.). (a
,,bl )+ ...+ (a i+ b i
). ”・Compare (an, bn) with each other, for example, FIN
When the D command specifies that the maximum value is to be found. a
A selection signal indicating the larger of l and bi is sent to the selector circuit 10. The selector circuit 10 operates according to the selection signal given from the comparison circuit 9. Select either input data ai or bl. Output this to SUMG as ci. This allows the SUMG input. Vector data C@+CI+
..., ci, ...cn are input sequentially. SLJM6 is. Each time these vector data elements are input sequentially from the beginning, they are compared with the previously input elements. Select the one element with the largest value, always leaving the largest element. Output as the result. [Invention tries to solve it! ! Problem I] In the conventional circuit shown in Fig. 3, when executing the FIND instruction. Only the primary adder is loaded, the secondary adder is idle, and if each adder is implemented with an LSI, the secondary adder 37. This is because the configuration of the primary adder is more complex than that of the adder. The degree of integration and circuit pattern changed, which caused design problems. The present invention is. Addition of primary and secondary IF during FIND instruction processing. The purpose is to eliminate the load imbalance between devices. [! ! ! Means for Solving the Problems] The present invention is as follows. Of the comparison circuit and selector circuit in the primary adder in the conventional circuit shown in Figure 3, the comparison circuit is moved to the secondary adder, and the two adders work together to create an FI.
It is designed to process ND instructions. Figure 1 is a horizontal diagram of the principle of the present invention. 11 is a multiplication and addition complex operation circuit. 12 is a vector register, 13 is a multiplier. 14 is the primary adder. l5 is a secondary adder, 18 is a selector circuit provided in the adder 2314, and 19 is a comparison circuit provided in the adder 15. Reference numeral 20 denotes a selection signal which instructs one of the input data to be selected as a result of the comparison circuit 19 in terms of magnitude. [Operation] According to the principle of the present invention shown in FIG. Each primary and secondary addition i1114.15 includes FIN
When executing the D instruction, the load can be distributed to both sides, and the unevenness of the amount of hardware circuitry in both adders is also improved. [Embodiment] Figure 2 shows the main part structure of an embodiment of the multiplication and addition complex operation circuit of the present invention. The figure shows only the primary and secondary adder parts in Figure 1. Also. The construction and operation of other circuit parts can be applied as is as explained in the conventional circuit shown in Figure 3. In Fig. 2. 14 is a primary adder, l5 is a secondary adder. 16 and 17 are Adder. 18 is a selector circuit. 19 is a comparison circuit, and 20 is a selection signal sent from comparison circuit 19 to selector circuit 1B. 21 to 30
is a latch, ai, bl are two input data (1-
1.2. ...i, ..., n). Note that adder 14.1
In 5. Addition II. of FIG. 3, respectively. Same as vessels 4 and 5. A carry look-ahead adder CPA capable of high-speed operation is used. When processing the FIND command, input data at,
The b-th signal is input in parallel to two adders 14 and 15. In this case, the maximum value of al and bl is determined. In the adder 14, the input data al is applied to one input of the adder 16 and the selector circuit l8. adder l6
It is not incorporated into the system, and there is no manpower required here. Also, input data bl is added to the other input of adder 1G,
Added to the above 0 manpower, the result is input data b
i is output as is from the adder 16 and added to the other input of the selector circuit 1B. Adder for this! In No. 5, input data al and bl are each input to an adder l7, and compared in magnitude by an internal comparison circuit l9, and a selection signal indicating whether to select al or b1 according to whether al≧b1 or al<b1 is generated. 20
Output. It is sent to the selector circuit 18 of adder l4. The selector circuit l8 selects one of the input data ai and bI determined by the selection signal 20 and outputs it as CI (1-1.2, . . . It, . . n). This output data cl is. As explained with SUM6 in the conventional circuit in Figure 3. The output data is successively compared in size with the preceding output data, and the larger one is always retained (when determining the II largest value) to prepare for comparison with the next output data, and finally the output data with the maximum value is left and output as the result. do. The above explanation is for finding the maximum value.
J! When finding the smallest value, essentially the same operation is performed, except that the data selection based on the size comparison result is reversed. (Effects of the Invention) In the multiplication and addition complex arithmetic circuit having a maximum value or minimum value detection function according to the present invention, the selector circuit and the comparison circuit are arranged separately in the primary and secondary adders, so that the load is reduced. Distribution is achieved, and one input of the selector circuit is taken from the Agoo output. Since the adder can be used as a through path, the number of circuit patterns and signal timings in common with the adder with the comparison circuit increases, which is advantageous in LSI design.

[Brief explanation of drawings]

Figure 1 shows the basic structure of the present invention. Figure 2 shows the present invention! Main part configuration diagram of the example circuit. Figure 3 shows the configuration of the conventional circuit. 11 in Figure 1: Multiplication and addition complex arithmetic circuit l2: Vector register 131 multiplication 'IE unit 14; Primary adder 15: Secondary adder l8: Selector circuit 19 + comparison circuit 20: Selection signal

Claims (1)

[Claims] In a multiplication and addition complex arithmetic circuit including a multiplier and two adders, primary and secondary, one of the two adders is configured to compare the magnitude of two input data. A comparison circuit is provided to output the result, and the other of the two adders is provided with a selector circuit that selects and outputs one of the two input data based on the output of the comparison circuit, and selects and outputs one of the two input data. A multiplication device equipped with a maximum value or minimum value detection function, characterized in that when processing an instruction to detect a maximum value or minimum value, the comparison circuit and selector circuit provided in the two adders are functionalized. and addition complex arithmetic circuit.