JPH0310430A - Demodulating clock correction device - Google Patents

Abstract

PURPOSE:To improve a radio data system (RDS) data reception rate and to collect information in a short time by correcting an RDS clock after the demodulation of a received error RDS signal in an RDS receiver. CONSTITUTION:A shift register enable duty ratio control circuit (SREGEN DUTY ratio control circuit) is constituted of a counter (1) 1, a multiplexer (1) 2, a pulse generator (1) 3, a counter (2) 4, a counter (2) 4, a multiplexer (2) 5, and a pulse generator (2) 6, and generates a basic clock synchronously with the received RDS clock and whose pulse width is properly modulated by the duty ratio control. An internal clock generating circuit generates an internal clock based on the basic clock and a demodulates RDS clock. Since the demodulates RDS clock is corrected into an accurate clock as the internal clock, the reception rate of the receiver RDS data after demodulation is improved and the information is collected in a short time.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a device for managing the reception status of a receiver in data broadcasting, and particularly relates to an FM multiplex data broadcasting system (radio data system, hereinafter abbreviated as RDS), etc. in a serial communication system receiver.

This invention relates to an RDS clock correction circuit that corrects a received demodulated clock (hereinafter referred to as RDS clock).

[Prior art 1] In RDS broadcasting, a broadcasting station encodes and transmits information using a generating polynomial, and the receiving side uses RDS broadcasting from a modulated signal.
Clock and data signals (hereinafter referred to as RDS data)
and decode the encoded information (bit information) from that data.

We are restoring that information.

The most faithful RDS clock %RDS data has a constant phase as shown in Figure 3 (a) and (b).
RDS data is sampled at the rising edge of the RDS clock, and bit information is decoded.

However, noise due to the reception environment and the strength of radio waves tend to cause reception errors, making it extremely difficult to obtain 100% bit information, and worsening the reception condition of RDS.

Although it is not directly related to the RDS broadcast receiving device, a method for detecting an abnormality in the reproduced clock is to detect the loss of the audio signal as described in Japanese Patent Application Laid-Open No. 172440/1983. There is a device to detect it.

In addition, as described in Japanese Patent Application Laid-Open No. 6-41243, a phase-locked loop (Phase-rocke
A receiving device that delays the output of the D Loop/PLL) circuit and uses a D flip-flop 5 and a retrigger type monostable multivibrator to detect abnormalities in the reproduced clock caused by noise, etc., and provides muting control to other circuits. There are some that are aimed at.

1 Problem to be solved by the invention J In RDS broadcasting, 1.1875kHz from the modulated signal
The RDS clock and RDS data of z are reproduced, and bit information is decoded from the data. However, as mentioned above, this RDS clog is prone to errors due to the strength of radio waves during reception.

As a general device for detecting abnormalities in recovered clocks,
The device described in the above-mentioned Japanese Patent Application Laid-Open No. 61-41243, or the device described in the Japanese Patent Application Laid-Open No. 61-17244
There is a device described in Publication No. 0, but Japanese Patent Laid-Open No. 61
The device described in Japanese Patent Application Laid-Open No. 61-172443 is completely unable to receive data in the event of an abnormality, so it merely detects an abnormality.
The device described in the publication also merely detects abnormalities, and cannot be used to improve the reception rate of RDS data.

The purpose of the present invention is to solve the problems of these conventional techniques and to
An object of the present invention is to provide an RDS clock correction circuit that improves the reception rate of received demodulated RDS data and enables information collection in a short time in a receiver of S.S.

(Means for Solving the Problems 1) In order to achieve the above object, the RDS clock correction device of the present invention decodes the received data signal using the received RDS clock to determine the reception state of a data broadcasting receiver that obtains information. In the device to be managed, a shift register enable duty ratio control circuit generates a clock that is synchronized with the RDS clock and is pulse width modulated as appropriate, and a clock generated by the shift register enable duty ratio control circuit and the RDS clock. Based on this, an internal clock generation circuit is provided that generates an internal clock corrected to a more accurate demodulated clock, and the received data signal is latched and sampled using the internal clock generated by the internal clock generation circuit. do.

[Operation] The shift register enable duty ratio control circuit (hereinafter abbreviated as 5REGEN DUTY ratio control circuit) in the present invention generates a basic clock that is synchronized with the received RDS clock and whose pulse width is appropriately modulated by duty ratio control. do. The internal clock generation circuit (hereinafter 1 n
teral clock generation circuit) generates an internal clock (hereinafter referred to as T internal clock) based on its basic clock and the demodulated RDS clock.

In this way, the demodulated RDS clock is:

The internal clock is corrected to be more accurate and locked.

The RDS receiver according to the present invention decodes RDS data using this I-port internal clock instead of the demodulated RDS clock.

In the case of RDS, if even one clock is missing, the information after 61 will be distorted, making it difficult to convert it into information.

However, the 5REGEN DUTY ratio control circuit and f n
By providing an internal clock generation circuit, when a clock drop or the like actually occurs, an internal clock is generated in the added state. The bit information changed by noise is then generated as an internal clock in a form similar to the transmitted clock, thereby facilitating error correction (parity check using a generator polynomial) during decoding.

In this way, the RDS receiver corrects the demodulated RDS clock and improves the reception rate of the received RDS data after demodulation.

example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a 5REGEN DUTY ratio control circuit of the present invention.

Counter (1) l, multiplexer (1) 2, pulse generator (1) 3, counter (2) 4. It is composed of a multiplexer (2) 5 and a pulse generator (2) 6.

First, the demodulated RDS clock is
When correcting the clock, the internal clock must be synchronized with the demodulated RDS clock, which means that if the phases are different, the RDS data and T n
The phase relationship with the internal clock is shifted, and R
This is because the DS data cannot be decoded correctly. In this embodiment, the counter (IN), multiplexer (1) 2, and pulse generator (1) shown in FIG.
)3, phase matching is performed.

Counter (1) 1 is the system clock 3.8MHz (
(hereinafter abbreviated as PH12) is frequency-divided and output to multiplexer (1) 2 as a basic clock.

At multiplexer (1) 2, the user
Select S[EL2.5EL based on the actual reception status of
The frequency division value of the basic clock of the counter (1) l is changed by the select signal No. 3, and the frequency division ratio is manipulated so that accurate phase matching can be achieved.

Pulse generator (1) 3 is multiplexer (1)
R which demodulated the frequency division value from 2 with the adjusted basic clock
DS clock (hereinafter abbreviated as EXCLK), EX
A reference clock that is in phase with CLK is generated and output to counter (2) 4.

Counter (2) 4 sets PH12 to 1.0 of the RDS clock.
It is frequency-divided to 1875 KHz, synchronized with a reference clock that is in phase with EXCLK transmitted from pulse generator (1) 3, and transmitted to multiplexer (2) 5.

The multiplexer (2) 5 controls the pulse width (duty ratio) of the reference clock transmitted from the counter (2) 4 based on the 5ELI and 5ELO signals selected by the user according to the actual reception state of the RDS, and A shift register enable (hereinafter abbreviated as 5REGEN) signal is generated via a generator (2) 6.

FIG. 2 is a block diagram of an internal clock generation circuit that generates an internal clock.

Multiplexer (3) 7 and pulse generator (3) 8
5REGEN DU in Figure 1
5REGEN signal generated by the TY ratio control circuit and E
The internal clock is generated based on the XCLK.

Below, based on the time chart in Figure 3,
The process of generating l clock will be explained.

FIG. 3(C) shows an RDS clock whose phase has shifted due to interference such as noise.

Note that the mark (book) indicates missing clocks and excessive clocks due to phase shift.

? If the RDS clock in Figure J3 (C) is received, the expected transmitted RDS clock is as shown in Figure 3 (d).
). However, correction based on the expected transmitted RDS clock cannot prevent the RDS clock from dropping or increasing because it is out of phase with the received RDS data, and the received RDS data is not decoded correctly, resulting in a loss of breath. becomes.

In order to correct the RDS clock omission and increase shown in FIG. 3(C), it is necessary to synchronize with the demodulated RDS clock using 5EL2 and 5EL3, and to
It is necessary to change the pulse width (duty ratio) of 5REGEN (No. 8) by l to realize an InLernal clock that is approximated by the demodulated RDS clock.

Figures 3(e) and (f) show 5ELl=L, 5ELO;H
3 is a time chart showing internal clock generation in mode (1) under the conditions of FIG. .

The 5RE (EEN signal) generated by the 5REGEN DUTY ratio control circuit in Fig. 1 is output with a duty ratio of 1%. The internal clock generation circuit corrects the demodulated RDS clock based on this signal (e). Then, an internal clock (f) is generated.

That is, when the rising edge of the RDS clock is detected during the "H" period of the 5REGEN signal, the internal clock rises and goes low at the same time as the RDS clock. If S.R.
If the rising edge of the RDS clock cannot be detected during the ``H'' period of the EG EN signal, the internal clock is started at the falling edge of the 5REGEN signal (Figure 3 (C) - Book 1. When the RDs clock drops out). handle).

Also, when the 5REGEN signal is in the “L” period, the RDS
Even if a rising edge of the clock is detected, the RDS clock is ignored (corresponding to the case where there are many RDS clocks in FIG. 3(C)-2).

(g) to (j) in Figure 3 are 5ELl=H, 5ELO=
internal based on the 5REGEN signal in mode 2.3 under the conditions of L, 5ELl=H, 5ELO=H, and the demodulated RDS clock in FIG. 3(C).
3 is a time chart showing an operation in which a clock is generated. It operates in the same way as in mode l, and the duty ratio is
Internal clock generation is realized with 50% and 99%, respectively.

In this way, the received and demodulated RDS clock is
5REGEN DUTY ratio control circuit and I n
Internal clock generation circuit
It is corrected as l clock.

FIG. 4 is a block diagram showing the operation of the shift register (26 bits) 9 which decodes the received RDS data using the clock thus corrected as the internal clock (j).

For example, when the received RDS data in FIG. 3(b) is sampled using the internal clock (j) in FIG. 3(j), the received RDS data in FIG. Since it is latched in the shift register (26 bits) 9 and sampled as 0110110, the normal RD in Fig. 3(a)
This is the same as normal sampling using the S clock. However, if sampling is performed using the conventionally demodulated RDS clock (c) in FIG. 3(C), it will be sampled as 011010, resulting in incorrect information.

In this way, by using the present invention, demodulated bit information that has changed due to noise is corrected to a form close to the transmitted data, and error correction during decoding (using a generator polynomial) is performed as an internal clock. parity check).

Incidentally, it is also possible to select the I nLernal clock generated in FIG. 2 and the received EXCLK via a multiplexer etc. depending on the reception condition, and use whichever one improves the actual reception condition as the RDS clock. .

[Effects of the Invention] According to the present invention, in an RDS receiver, it becomes possible to correct the RDS clock after demodulating the received error RDS signal, improving the reception rate of RDS data, and collecting information in a short time. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the 5REGEN DUTY ratio control circuit of the present invention, FIG. 2 is a block diagram of the internal clock generation circuit of the present invention, and FIG. 3 is a block diagram of the 5REGEN DUTY ratio control circuit of the present invention.
FIG. 4 is a time chart diagram showing the operation of each clock of the RDS clock correction device in the figure, and FIG. 4 is a block diagram showing the operation and configuration of the shift register in the RDS receiver. I: Counter (1), 2: Multiplexer (1). 3: Pulse generator (1), 4: Counter (2). 5: Multiplexer (2), 6: Pulse generator (2), '7: Multiplexer (3), 8 Pulse generator (3), 9: Shift register (26 bits)
.

Claims (1)

[Claims] (1) In a device that manages the reception status of a data broadcasting receiver that obtains information by decoding a received data signal using a received demodulated clock, the clock is synchronized with the demodulated clock and is pulse width modulated as appropriate. shift register enable duty ratio control means for generating;
Based on the clock generated by the shift register enable duty ratio control means and the demodulated clock,
The present invention is characterized in that an internal clock generating means for generating an internal clock corrected to a more accurate demodulated clock is provided, and the received data signal is latched and sampled using the internal clock generated by the internal clock generating means. Demodulation clock correction device.