DE4018136A1 - DEMODULATION CLOCK CORRECTION DEVICE - Google Patents

Description

The invention relates to a demodulation clock correction direction according to the preamble of claim 1 and relates in particular a device for controlling a signal temperature initial state of a receiver during data transmission. In addition, the invention relates to an RDS clock correction circuit for correcting a demodulation clock signal (This is also called an RDS clock in the following description signal), which is used by a receiver in a serial communication or transmission system, such as egg an FM multi-data transmission system. (In the following, a radio or radio data system becomes the On referred to as an RD system for the sake of simplicity).

In an RDS transmission, a broadcast encodes and transmits provide information with the help of a generation function. A receiver reproduces an RDS clock signal and data signal (which in the following description as an RDS-Da tens signal), from a modulation signal and decodes the encoded information (bit information) this data so as to restore the information.

The most ideal RDS clock or data signals have constant ones Phases. The RDS data is increased when the RDS Clock signal sampled or broken down into sections, and the Bit information is decoded. However, a signal temp catching errors like by a noise, which by a Sig reception environment, etc., and by the Change in intensity of a radio or radio wave. Therefore, it is very difficult to get the bit information To get 100% so that the receiving state of the RDS signal  bad is.

There is a general method of detecting an anomaly a reproducing clock signal, although this method do not rely directly on the recipient of the RDS transmission pulls. In Japanese Patent Application (Kokai) No. 61- 1 72 440 is an omission detection device a sound signal and this detection method. As in a Japanese Patent Application (Kokai) No. 61-41243 describes an output of a phase-locked loop (PLL-) Circuit is delayed, and the abnormality of the reprodizing Clock signal caused by noise, etc. is through a receiver using a D flip-flop and a monostable multivibrator Post-trigger type so as to have a noise reduction control with respect to the other circuits.

In the RDS transmission, the RDS clock and data signals reproduced from the modulation signal at 1.1875 kHz, and the bit information is decoded from this data. However becomes, as already mentioned above, an error in this RDS clock signal like by changing the intensity of the radio or radio wave, etc. at the time of signal reception called.

A general facility for determining abnormality of the reproducing clock signal is, for example, in the Japanese Patent Application (Kokai) Nos. 61-41 243 and 61- 1 72 440 is shown. In the Japanese patent application (Ko kai) No. 61-41 243 facility shown can store data can only be received at the abnormal time, and consequently, only an abnormality is found. More like that Manner is described in Japanese Patent Application (Kokai) No. 61-1 72 440 illustrated and described facility just found an abnormality, so this facility cannot be improved to a signal reception ratio to improve the RDS data.

According to the invention, therefore, an RDS clock correction on direction for improving a signal reception ratio of RDS data are created, which are in a recipient of the RDS signal have been received and demodulated, so receive information in a short time. According to the invention this is in a demodulation clock correction device according to the preamble of claim 1 by the features in preserved its characteristic part. Advantageous next education is the subject of the subclaims.

In the device according to the invention, the slide valve produces register enable duty ratio control direction or circuit, (what in the description below also as a SREGEN usage ratio controller or Circuit is called) a base clock signal, which with synchronized with the received RDS clock signal and by the Duty cycle control with respect to the pulse width ent has been modulated speaking. One internal clock generating device or circuit generates the internal Clock signal based on this basic clock signal and that demodulated RDS clock signal.

Consequently, the demodulated RDS clock signal like the inter ne clock signal corrected to a more accurate clock signal. The RDS signal receiver in the present invention decodes the RDS data using this internal clock signal nals instead of the demodulated RDS clock signal.

Even if only one clock signal in the case of the RDS signal is omitted, the information before and after one Object information obtained inaccurately, making it difficult is to provide correct information. However, if at the invention, for example, the clock signal actually the internal clock signal is left by the Opera tion of the SREGEN duty cycle control circuit and the internal clock generating circuit generated in a state in which the clock signal is added in the device  becomes. Bit information that has been changed by noise is corresponding to the transmitted clock signal as that internal clock signal generated, thereby collecting errors (a parity check using a generating function) to facilitate when the data is decoded.

As a result, the demod. In the receiver of the RDS signal lated RDS clock signal corrected so that a signal reception ratio is improved after the received RDS-Da are demodulated.

The invention based on preferred from management forms with reference to the attached drawing explained in detail. Show it:

Fig. 1 is a block diagram of a SREGEN duty cycle control circuit in a demodulation clock corrector according to the invention;

Fig. 2 is a block diagram of a circuit for reproducing an internal clock signal in the demodulation clock correction circuit according to the invention;

Fig. 3 is a timing diagram showing the effect of each of the clock signals in the RDS clock correction circuit in Figs. 1 and 2, and

Fig. 4 is a block diagram of the operation and execution of a shift register in an RDS receiver.

Preferred embodiments of a demodulation clock correction circuit according to the invention are described below in an individual with reference to the drawings. In a block diagram of Fig. 1, the structure of a SREGEN duty cycle control circuit in the demodulation clock correction circuit according to the invention is shown. As shown in Fig. 1 Darge, this control circuit has a first counter 1 , a first multiplexer 2 , a first pulse generator 3 , a second counter 4 , a second multiplexer 5 and a second pulse generator 6 .

When a demodulated RDS clock signal is corrected with an internal clock signal, the internal clock signal must be synchronous with the demodulated RDS clock signal, because if the phases of these signals differ from each other, the phases of an RDS data signal and the internal clock signal are shifted to each other so that the RDS data can not be decoded correctly. In this embodiment, the phases of the internal clock signal and the demodulated RDS clock signal by the first counter 1 , the first multiplexer 2 and the first pulse generator 3 in FIG. 1 are in agreement with each other. The first counter 1 divides a system clock frequency of 3.8 MHz (which will be referred to as PH12 for the sake of simplicity in the following description) and outputs a signal with the divided frequency to the first multiplexer 2 as a base clock signal. In the first multiplexer 2 , the frequency partial value of the base clock signal of the first counter 1 is changed by selecting signals SEL 2 and SEL 3 , which have been selected by a user on the basis of a current reception state of the RDS signal. Consequently, a frequency division ratio is set so that the phases of the above signals exactly match each other.

The first pulse generator 3 generates a reference clock signal by the base clock signal, which has the set frequency division value, from the first multiplexer 2 and the demodulated RDS clock signal (which in the following description is referred to as an EXCLK signal for the sake of simplicity), so that the phase of the reference clock signal is in accordance with that of the EXCLK signal. This reference clock signal is given to the second counter 4 .

The second counter 4 divides the frequency PH12 into 1.1875 kHz with respect to the RDS clock signal. A signal with this divided frequency is synchronized by the second counter 4 with the reference clock signal, which has the same phase as that of the EXCLK signal, which has been transmitted by the first pulse generator 3 , and is transmitted to the second multiplexer 5 .

The second multiplexer 5 controls a pulse width (a duty cycle) of the reference clock signal, which has been transmitted from the second counter 4 , on the basis of selector signals SEL 1 and SEL 0 , which are selected by a user in accordance with the actual reception state of the RDS signal has been. Then the second multiplexer 5 generates the second pulse generator 6 a shift register enable signal (which will be referred to as a SREGEN signal in the following description for the sake of simplicity).

In Fig. 2 is a block diagram of a circuit is shown for generating the internal clock signal. This circuit is formed by a third multiplexer 7 and a third pulse generator 8 and generates the internal clock signal on the basis of the SREGEN and EXCLK signals which have been generated with the aid of the SREGEN duty cycle control circuit in FIG. 1.

Generation of the internal clock signal will be described next with reference to the timing chart in FIG. 3. The most ideal RDS clock or data signals have, for example, constant phases, as shown by the designations RDS clock A and RDS data in FIG. 3. The RDS data is sampled by a rising edge of the RDS clock signal and the bit information is decoded.

However, a signal reception error is often caused by noise, caused by a signal reception environment, etc. has been, and the intensity change of a radio or  Causes radio wave. Therefore, it is very difficult To obtain bit information to 100%, so that the reception zuzu the RDS signal is bad.

With the designation RDS clock B in Fig. 3, an RDS clock signal is designated, which is shifted in phase by noise, etc. The RDS clock signal has been skipped and has become excessively larger due to the phase shift, as shown by a marker ().

When the RDS clock signal shown with the designation "RDS clock B" in Fig. 3 is received, a known or expected transmitted RDS clock signal will be created as by the designation "transmitted clock" in Fig. 3 is shown. However, it is not possible to prevent the RDS clock signal from being skipped and becoming moderately larger, since the phase of this transmitted RDS clock signal is shifted with respect to that of a received RDS data signal. Therefore, the received RDS data is not decoded correctly, so the correction for skipping and excessive enlargement based on the previously known, expected transmitted RDS clock signal is meaningless.

In order to correct the omission and excessive enlargement of the RDS clock signal which is represented by RDS clock B in FIG. 3, the internal clock signal must be synchronized with the demodulated RDS clock signal by means of the selection signals SEL 2 and SEL 3 , and the pulse width (duty cycle) of the SREGEN signal must be changed by the selection signals SEL 0 and SEL 1 so as to approximate the internal clock signal to the demodulated RDS clock signal.

Designations "SREGEN in Mode 1 and internal clock in Mode 1" of FIG. 3 are timing diagrams showing the generation of the in-internal clock signal in Mode 1 sheep under a condition fen in which the voltage level of the selection signals SEL 1 and SEL 0 is low and are high.

The SREGEN signal, which has been produced by means of the SREGEN duty cycle control circuit in FIG. 1, is emitted at a usage ratio of 1%. The circuit generating the internal clock corrects the demodulated RDS clock signal on the basis of this SREGEN signal, which is represented by the designation SREGEN in mode 1 of FIG. 1, and generates the internal clock signal, which is designated by the designation "internal clock in Mode 1 "of FIG. 3 represents Darge.

Namely, if an increase in the RDS clock signal is found in a period in which the voltage level of the SREGEN signal is high, the internal clock signal increases simultaneously with the RDS clock signal. If the rise of the RDS clock signal cannot be detected in the period in which the voltage level of the SREGEN signal is high, the internal clock signal rises as the SREGEN signal decreases. This case corresponds to a case in which the RDS clock signal is omitted, as shown by a mark 1 in the "RDS clock B" of FIG. 3.

If the rise of the RDS clock signal is detected in a period in which the voltage level of the SREGEN signal is low, this RDS clock signal is neglected. This case corresponds to a case in which the RDS clock signal has become excessively large, as shown by a marker 2 in the "RDS clock B" of FIG. 3.

The designations "SREGEN" and "Internal clock in mode 2 and 3 " of FIG. 3 are timing diagrams which show an operation of the device for generating an internal clock signal which is based on the demodulated RDS clock signal which is denoted by the designation "RDS- Clock B "in Fig. 3 and" SREGEN signals in mode 2 "on the condition that the voltage level of the selection signals SEL 1 and SEL 0 are equally high, and in mode 3 are provided that the Voltage levels of the selection signals SEL 1 and SEL 0 are the same. The operation of the device in each of these modes 2 and 3 is similar to that in mode 1 , and the internal clock signals are generated with duty ratios of 50% and 99%, respectively.

As mentioned above, the received and modulated RDS clock signal as the internal clock signal by the Opera tion of the SREGEN duty cycle control circuit and corrected the internal clock generating circuit.

In Fig. 4, a block diagram is shown, the mode of operation of a shift register 9 (which is formed by 26 bits) to decode the received RDS data with the aid of a clock signal, which consequently as the internal clock signal (internal clock in Mode 3 of Fig. 3) corrected what is.

If, for example, the received RDS data, which for example are represented by the designation (b) of FIG. 3, are sampled using the internal clock signal which is represented by the designation "internal clock in mode 3 " in FIG. 3, These data are held in the shift register 9 in FIG. 4 by the rise in the internal clock signal (internal clock in mode 3 ) and are sampled as 0110110. Consequently, this sampled data is equal to the normal sampled data created by the normal RDS clock signal in the "RDS clock A" of FIG. 3. However, when the above data is sampled using the RDS clock signal which has been conventionally demodulated in the "RDS clock B" of FIG. 3, this data is sampled as 011010, thereby providing incorrect information.

As mentioned above, according to the invention, the demo dulated bit information changed by noise  has been corrected so that the data of this information the transmitted data can be approximated to thereby Error collection (parity check with a generating Function) if the data as the internal Clock signal to be decoded.

The received EXCLK signal and the internal clock signal which have been generated as shown in Fig. 2 by a multiplexer, etc. in accordance with the signal reception state can be selected so that either the received EXCLK signal or the internal one Clock signal can be used as the RDS clock signal to improve the actual signal reception state.

According to the invention can in the receiver of the RDS signal the RDS clock signal will be corrected after a receive an incorrect RDS signal is demodulated. So that's it Signal reception ratio of the RDS data improved, and it it is possible to collect information for a short time.

Claims (4)

1. Demodulation clock correction device for controlling a signal reception state of a receiver in data transmission, in which a received data signal is decoded by a received demodulated clock signal in order to obtain information, characterized by
a shift register enable duty control device for generating a clock signal which is synchronized with the modulated clock signal, modulated accordingly and controlled with respect to the pulse width;
internal clock generating means for generating an internal clock signal corrected with a more accurate demodulated clock signal based on the demodulated clock signal and the clock signal generated by the shift register enable duty cycle control circuit, and
means for holding and sampling the received data signal using the internal clock signal generated by the internal clock generating circuit. 2. Correction device according to claim 1, characterized ge indicates that the recipient has the data with Using the internal clock signal instead of the demodulated clock signals decoded. 3. Correction device according to claim 2, characterized ge indicates that when the clock signal is omitted and has become excessively large, the internal clock signal by the operations of the shift register enable keys Ratnis control device and the internal clock generating device is generated.   4. Correction device according to claim 3, characterized ge indicates that bit information, which by Noise has been changed as the internal clock signal is generated in accordance with the transmitted clock signal.