GB2235610A

GB2235610A - Demodulated clock correcting apparatus

Info

Publication number: GB2235610A
Application number: GB9012724A
Authority: GB
Inventors: Masahiro Sakai
Original assignee: Ricoh Co Ltd
Current assignee: Ricoh Co Ltd
Priority date: 1989-06-07
Filing date: 1990-06-07
Publication date: 1991-03-06
Also published as: FR2649564B1; FR2649564A1; JP2676919B2; GB9012724D0; JPH0310430A; DE4018136A1

Abstract

In a demodulated clock correcting apparatus for controlling a signal receiving state of a receiver in data broadcast, a received data signal is decoded by a received demodulated clock signal to obtain information. The correcting apparatus has a shift register enable duty ratio control circuit 1 to 6 for producing a clock signal synchronized with the demodulated clock signal and suitably modulated and controlled with respect to pulse width; an internal clock producing circuit 7, 8 for producing an internal clock signal corrected to a more accurate demodulated clock signal based on the demodulated clock signal "EXCLK" and the clock signal "SREGEN" produced by the shift register enable duty ratio control circuit; and a device (9) Fig 4, (not shown) for latching and sampling the received data signal by using the internal clock signal produced by the internal clock producing circuit 7, 8. <IMAGE>

Description

1

TITLE OF THE INVENTION

DEMODULATING CLOCK CORRECTING APPARATUS BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to an apparatus for controlling a signal receiving state of a receiver in data broadcast. More particularly, the present invention relates to an RDS clock correcting circuit for correcting a demodulating clock signal (which is called an RDS clock signal in the following description) received by a receiver in a serial communication system such as an FM multiple data broadcasting system (a radio data system which is simply called RDS in the following description). 2. Description of the Related Art

In the RDS broadcast, a broadcasting station encodes and transmits information by using a generating function. A receiver reproduces an RDS clock signal and a data signal (which are called an RDS data signal in the following description) from a modulating signal and decodes the encoded information (bit information) from these data so as to restore the information.

The most ideal RDS clock and data signals respectively have constant phases. The RDS data are sampled by a rise of the RDS clock signal and the bit information is decoded.

However, a signal receiving error tends to be caused by a noise caused by a signal receiving environment, etc. and the change in intensity of a radio wave. Therefore, it is very difficult to obtain the bit information at 100 % so that the receiving state of the RDS signal is bad.

There is a general methodfor detecting abnormality of a reproducing clock signal although this method does not directly relate to the receiver of the RDS broadcast. Japanese Patent Application Laying Open (HOKAI) No. 61172440 shows a device for detecting omission of a sound signal as this detecting method.

As described in Japanese Patent Application Laying Open (KOKAI) No. 6141243, an output of a Phase-Locked Loop (PLL) circuit is delayed and the abnormality of the reproducing clock signal caused by a noise, etc. 'Is detected by a receiver using a D-flip flop and a monostable multivibrator of a retrigger type so as to perform muting control with respect to the other circuits.

In the RDS broadcast, the RDS clock and data signals at 1.1875 kHz are reproduced from the modulating signal and the bit information is decoded from these data. However, as mentioned above, an error in this RDS clock signal tends to be caused by the change in intensity of the radio wave, etc. at the signal receiving time.

A general device for detecting the abnormality of the reproducing clock signal is shown in e.g., Japanese Patent Application Laying Open (KOKAI) Nos. 61-41243 and 61-172440. In the device shown in Japanese Patent Application Laying Open (KOKAD No. 61-41243, data cannot be received at all at the abnormal time and therefore only abnormality is detected. Similarly, in the device shown in Japanese Patent Application Laying Open (KOKAD No. 61172440, only abnormality is detected so that this device cannot be used to improve a signal receiving ratio of the RDS data.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an RDS clock correcting apparatus for improving a signal receiving ratio of RDS data received and demodulated in a receiver of the RDS signal so as to obtain information for a short time.

The above object of the present invention can be achieved by a demodulating clock correcting apparatus for controlling a signal receiving state of a receiver in data broadcast in which a received data signal is decoded by a received demodulated clock signal to obtain information, the apparatus comprising shift register enable duty ratio control means for producing a clock signal synchronized with the modulated clock signal and suitably modulated and controlled with respect to pulse width; internal clock producing means for producing an internal clock signal corrected to a more accurate demodulated clock signal based on the demodulated clock signal and the clock signal produced by the shift register enable duty ratio control means; and means for latching and sampling the received data signal by using the internal clock signal produced by the internal clock producing means.

In the present invention, the shift register enable duty ratio control means or circuit (which is simply called a SREGEN DUTY ratio control means or circuit in the following description) generates a basic clock signal synchronized with the received RDS clock signal and suitably modulated by the control of duty ratio with respect to pulse width. The internal clock producing means or circuit (which is called an INTERNAL clock producing means or circuit in the following description) produces the internal clock signal (which is called an INTERNAL clock signal in the following description) based on this basic clock signal and the demodulated RDS clock signal.

Thus, the demodulated RDS clock signal is corrected to a more accurate clock signal as the INTERNAL clock signal.

The receiver of the RDS signal in the present invention decodes the RDS data using this INTERNAL clock signal instead of the demodulated RDS clock signal.

In the case of the RDS signal, even when only one clock signal is omitted, the - 6 information before and after object information are incorrectly provided so that it is difficult to provide correct information. However, in the present invention, for example, when the clock signal is really omitted, the INTERNAL clock signal is produced by the operations of the SREGEN DUTY ratio control circuit and the INTERNAL clock producing circuit in a state in which the clock signal is added to the apparatus. Bit information changed by a noise is produced as the INTERNAL clock signal approximate to the transmited clock signal, thereby facilitating error collection (parity check using a generating function) when the data are decoded.

Thus, in the receiver of the RDS signal, the demodulated RDS clock signal is corrected so that signal receiving ratio is improved after the received RDS data are demodulated.

Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the present invention as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of a SREGEN DUTY ratio control circuit in a demodulating clock correcting apparatus of the present invention; Fig. 2 is a block diagram of a circuit for reproducing an INTERNAL CLOCK signal in the demodulating clock correcting apparatus of the present invention; Fig. 3 is a time chart showing the operation of each of clock signals in the RDS clock correcting apparatus in Figs. 1 and 2; and Fig. 4 is a block diagram showing the operation and construction of a shift register in an RDS receiver.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of a demodulating clock correcting apparatus in the present invention will next be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram showing the construction of a SREGEN DUTY ratio control circuit in the demodulating clock correcting apparatus of the present invention.

As shown in Fig. 1, this control circuit is constructed by a first counter 1, a first multiplexer 2, a first pulse generator 3, a second counter 4, a second multiplexer 5 and a second pulse generator 6.

When a demodulated RDS clock signal is corrected to an INTERNAL clock signal, the INTERNAL clock signal must be in synchronization with the demodulated RDS clock signal. This is because, when the phases of these signals are different from each other, the phases of an RDS data signal and the INTERNAL clock signal are shifted from each other so that the RDS data cannot be correctly decoded. In this embodiment, the phases of the INTERNAL clock signal and the demodulated RDS clock signal are in conformity with each other by the first counter 1, the first multiplexer 2, and the first pulse generator 3 in Fig. 1.

The first counter 1 divides a system clock frequency 3.8 MHz (which is simply called PH12 in the following description) and outputs a signal having the divided frequency to the first multiplexer 2 as a basic clock signal.

In the first multiplexer 2, the frequency dividing value of the basic clock signal of the 9 - first counter 1 is changed by selecting signals SEL 2 and SEL 3 selected by a user on the basis of an actual receiving state of the RDS signal. Thus, a frequency dividing ratio is adjusted such that the phases of the above signals are accurately in conformity with each other.

The first pulse generator 3 makes a reference clock signal by the basic clock signal having the adjusted frequency dividing value from the first multiplexer 2 and the demodulated RDS clock signal (which is simply called an EXCLK signal in the following description) such that the phase of the reference clock signal is in conformity with that of,the EXCLK signal. This reference clock signal is outputted to the second counter 4.

The second counter 4 divides the frequency PH12 into 1.1875 KHz with respect to the RDS clock signal. A signal having this divided frequency is synchronized by the second counter 4 with the reference clock signal having the same phase as that of the EXCLK signal transmitted from the first pulse generator 3 and is transmitted to the second multiplexer 5.

The second multiplexer 5 controls a pulse 1 width (a duty ratio) of the reference clock signal transmitted from the second counter 4 on the basis of selecting signals SEL 1 and SEL 0 selected by a user in accordance with the actual receiving state of the RDS signal. Then, the second multiplexer 5 produces a shift register enable (which is simply called SREGEN in the following description) signal through the second pulse generator 6'.

Fig. 2 is a block diagram of a circuit for producing the INTERNAL clock signal.

This producing circuit is constructed by a third multiplexer 7 and a third pulse generator 8 and produces the INTERNAL clock signal based on the SREGEN and EXCLK signals produced by the operation of the SREGEN DUTY ratio control circuit in Fig. 1.

A producing process of the INTERNAL clock signal will next be described with reference to the time chart of Fig. 3.

The most ideal RDS clock and data signals as an example respectively have constant phases as shown in items RDS CLOCK A and RDS DATA of Fig. 3. The RDS data are sampled by a rise of the RDS clock signal and the bit information is decoded c p However, a signal receiving error tends to be caused by a noise caused by a signal receiving environment, etc. and the change in intensity of a radio wave. Therefore, it is very difficult to obtain the bit information at 100 %. so that the receiving state of the RDS signal is bad.

Item RDS CLOCK B of Fig. 3 shows an RDS clock signal shifted in phase by a noise, etc.

The RDS clock signal is omitted and excessively increased by the shift in phase as shown by mark When the RDS clock signal shown in item RDS CLOCK B of Fig. 3 is received, an anticipated transmitted RDS clock signal is provided as shown in item TRANSMITTED CLOCK of Fig. 3. However, it is impossible to prevent the RDS clock signal from being omitted and excessively increased since the phase of this transmitted RDS clock signal is shifted from that of a received RDS data signal. Therefore, the received RDS data are not correctly decoded so that the correction for the omission and excessive increase based on the anticipated transmitted RDS clock signal is meaningless.

12 - To correct the omission and excessive increase of the RDS clock signal shown in the item RDS CLOCK B of Fig. 3, it is necessary to synchronize an INTERNAL clock signal with the demodulated RDS clock signal by the selecting signals SEL2 and SEL3 and change the pulse width (duty ratio) of the SREGEN signal by the selecting s-ignals SELO and SEL1 so as to provide the INTERNAL clock signal more approximate to the demodulated RDS clock signal.

Items SREGEN in Mode 1 and INTERNAL CLOCK in Mode 1 of Fig. 3 are time charts showing the production of the INTERNAL clock signal in mode 1 under a condition i:h which the voltage levels of the selecting signals SELl and SELO are respectively equal to low and high.

The SREGEN signal made by the SREGEN DUTY ratio control circuit in Fig. 1 is outputted at duty ratio 1 %. The INTERNAL clock producing circuit corrects the demodulated RDS clock signal based on this SREGEN signal shown by the item SREGEN in Mode 1 of Fig. 3 and produces the INTERNAL clock signal shown by the item INTERNAL CLOCK in Mode 1 of Fig. 3.

Namely, when a rise of the RDS clock signal is detected in a period in which the voltage level of the SREGEN signal is high, the INTERNAL . 13 clock signal simultaneously rises together with the RDS clock signal. When the rise of the RDS clock signal cannot be detected in the period in which the voltage level of the SREGEN signal is high, the INTERNAL clock signal rises by a fall of the SREGEN signal. This case corresponds to a case in which the RDS clock signal is omitted as shown by mark 1 in the item RDS CLOCK B of Fig. 3.

When the rise of the RDS clock signal is detected in a period in which the voltage level of the SREGEN signal is low, this RDS clock signal is neglected. This case corresponds to a case in which the RDS clock signal is excessively increased as shown by mark 2 in the i tem RDS CLOCK B of Fig. 3.

Items SREGEN and INTERNAL CLOCK in Mode 2, 3 of Fig. 3 are time charts showing an operation of the apparatus for producing the INTERNAL clock signal based on the demodulated RDS clock signal shown by the item RDS CLOCK B, of Fig. 3 and SREGEN signals in mode 2 under a condition in which the voltage levels of the selecting signals SELl and SELO are respectively equal to high and low, and in mode 3 under a condition in which the voltage levels of the selecting signals SELl and SELO are respectively 14 - equal to high and high. The operation of the apparatus in each of these modes 2 and 3 is similar to that in the mode 1 and the INTERNAL clock signals are respectively produced at duty ratios 50 % and 99%.

As mentioned above, the received and demodulated RDS clock signal is corrected as the INTERNAL clock signal by the operations of the SREGEN DUTY ratio control circuit and the INTERNAL clock producing circuit.

Fig. 4 is a block diagram showing the operation of a shift register (constructed by 26 bits) 9 for decoding the received RDS data using a clock signa.1 thus corrected as the INTERNAL clock signal (INTERNAL CLOCK--lin Mode 3 of Fig. 3).

For example, when the received RDS data shown by the item (b) of Fig. 3 are sampled by using the INTERNAL clock signal shown by the item INTERNAL CLOCK in Mode 3 of Fig. 3, these data are latched to the shift register 9 in Fig. 4 by the rise of the INTERNAL clock signal(INTERNAL CLOCK in Mode 3)and are sampled as 0110110.

Accordingly, these sampled data are equal to the normal sampled data provided by the normal RDS clock signal in the itme RDS CLOCK A of Fig. 3.

However, when the above data are sampled by 1 1 . 15 1.

using the RDS clock signal conventionally demodulated in the item RDS CLOCK B of Fig. 3, these data are sampled as 011010, thereby providing incorrect information.

As mentioned above, in accordance with the present invention, the demodulated'bit information changed by a noise is corrected such that the data of this information are approximate to the transmitted data, thereby facilitating error collection (parity check using a generating function) when the data are decoded as the INTERNAL clock signal.

It is possible.to select the received EXCLK signal and 'the INTERNAL'clock signal produced as shown in Fig. 2 through a multiplexer, etc. in ac cordance with the signal receiving state such that either the received EXCLK signal or the INTERNAL clock signal is used as the RDS clock signal to improve the real signal receiving state.

In accordance with the present invention, in the receiver of the RDS signal, it is possible to correct the RDS clock signal after a received error RDS signal is demodulated. Therefore, signal receiving ratio of the RDS data is improved and it is possible to collect information for a short time Manv widelv different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

17 -

Claims

WHAT IS CLAIMED IS:

A demodulating clock correcting apparatus for controlling a signal receiving state of a receiver in data broadcast in which a received data signal is decoded by a received demodulated clock signal to obtain information, said apparatus comprising: shift register enable duty ratio control means for producing a clock signal synchronized with said modulated clock signal and suitably modulated and controlled with respect to pulse width; internal clock producing means for producing an internal clock signal corrected to a more accurate demodulated clock signal based on said demodulated clock signal and the clock signal produced by the shift register enable duty ratio control means; and means for latching and sampling said received data signal by using the internal clock signal produced by the internal clock producing means.
2. A demodulating clock correcting apparatus 18 - as claimed in claim 1. wherein the receiver decodes the data using the internal clock signal instead of the demodulated clock signal.
3. A demodulating clock correcting apparatus as claimed in claim 2, wherein, when the clock signal is omitted and excessively increased, the internal clock signal is produced by the operations of the shift register enable duty ratio control means and the internal clock producing means.
4. A demodulating clock correcting apparatus as claimed in claim 3, wherein bit information changed by a noise is produced as the internal clock signal approximate to the transmitted clock signal.
5. A demodulating clock correcting apparatus substantially as hereinbefore described with reference to Figures 1, 2 and 4, or Figures 1 to 4 of the accompanying drawings.

Publ shed 1991 at The Patent Office. State House. 66171 H h Holborn. London WC1R47P. Further copies may he obtained from Sales Branch. Unit 6, Nine Mile Point Cwmfelinfach. Cross Keys. inewport. NPI 7HZ. Printed by Multiplex techniques lid. St Mary Cray, Kent k