JPH03104249U - - Google Patents
Info
- Publication number
- JPH03104249U JPH03104249U JP1031390U JP1031390U JPH03104249U JP H03104249 U JPH03104249 U JP H03104249U JP 1031390 U JP1031390 U JP 1031390U JP 1031390 U JP1031390 U JP 1031390U JP H03104249 U JPH03104249 U JP H03104249U
- Authority
- JP
- Japan
- Prior art keywords
- image
- image memory
- data
- memory
- image data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000005429 filling process Methods 0.000 description 1
Landscapes
- Image Generation (AREA)
Description
第１図は本考案に係る画像処理装置の一実施例
の構成図、第２図は塗りつぶしパターン生成回路
の構成例を示す図、第３図はイメージメモリに記
憶されているイメージデータの一例を示す図、第
４図はＲＯＭに入力するデータとＲＯＭから出力
されるデータとの関係を説明するための図、第５
図は特異データを説明するための図、第６図は第
１図の画像処理装置における塗りつぶし処理の処
理流れを示すフローチヤートである。
１……ＣＰＵ、２……イメージメモリ、３……
ＤＲＡＭ制御回路、４……データバス、５……デ
ータ入力用バス、６……データ出力用バス、７…
…データバス制御回路、８……塗りつぶしパター
ン生成回路、９……ＲＯＭ、１０……フリツプ・
フロツプ。
Fig. 1 is a block diagram of an embodiment of an image processing device according to the present invention, Fig. 2 is a block diagram showing an example of the structure of a fill pattern generation circuit, and Fig. 3 is a diagram showing an example of image data stored in an image memory. FIG. 4 is a diagram for explaining the relationship between data input to the ROM and data output from the ROM, and FIG.
The figure is a diagram for explaining specific data, and FIG. 6 is a flowchart showing the processing flow of the filling process in the image processing apparatus of FIG. 1. 1...CPU, 2...Image memory, 3...
DRAM control circuit, 4...data bus, 5...data input bus, 6...data output bus, 7...
...Data bus control circuit, 8...Fill pattern generation circuit, 9...ROM, 10...Flip
Flop.
Claims (1)
、該イメージメモリをアクセスし、該イメージメ
モリから所定ビツト数分のイメージデータを読出
可能なＣＰＵと、ＣＰＵによつて読出された所定
ビツト数分のイメージデータに対して塗りつぶし
処理を行なつて前記イメージメモリに再書込みさ
せる塗りつぶしパターン生成手段とを備えている
ことを特徴とする画像処理装置。 an image memory in which image data is stored; a CPU that can access the image memory and read a predetermined number of bits of image data from the image memory; 1. An image processing apparatus, comprising a fill pattern generating means for performing a fill process on the image and rewriting it in the image memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1031390U JPH03104249U (en) | 1990-02-05 | 1990-02-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1031390U JPH03104249U (en) | 1990-02-05 | 1990-02-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104249U true JPH03104249U (en) | 1991-10-29 |
Family
ID=31513887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1031390U Pending JPH03104249U (en) | 1990-02-05 | 1990-02-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104249U (en) |
-
1990
- 1990-02-05 JP JP1031390U patent/JPH03104249U/ja active Pending
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