JPH0310418A - Reference clock controller for clock regenerating pll circuit - Google Patents

Abstract

PURPOSE:To prevent spurious radiation due to the effect of a reference clock by stopping the oscillation of an oscillation circuit in response to the operating clock of a phase locked loop(PLL) circuit. CONSTITUTION:A crystal oscillator 22 oscillating a reference clock is oscillated only when the reference clock from the crystal oscillator 22 is required at the start of a clock recovery PLL circuit 3. On the other hand. The oscillation of the crystal oscillator 22 is stopped when the PLL circuit 3 is locked requiring the reference clock for the PLL circuit 3. Thus, spurious radiation due to the effect of the reference clock is prevented in the steady state of a demodulation circuit when an inputted digital signal is demodulated by the demodulation circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a reference clock control device that controls a reference clock in a clock regeneration PLL circuit that regenerates a clock for demodulating an input digital signal. .

(b) Conventional technology Recently, CD players, DAT (digital
Many digital audio source devices that handle audio information as digital signals, such as tape recorders) or BS tuners (satellite broadcast reception tuners),
A digital output function is provided to output the audio information as a digital signal. The digital signal output from the digital audio source device is EIAJ (
The digital audio interface standard (EIAJ standard CP) standardized by the Electronics Industries Association of Japan)
-340), and the signal format is defined. Therefore, with the advent of digital audio source devices equipped with the digital output function, some audio devices, including audio amplifiers, have functions to demodulate and process digital signals in the signal format, and 2. Description of the Related Art Digital signal compatible audio devices that are capable of directly inputting digital signals from audio source devices have been commercialized.

By the way, in order to capture a digital signal, a clock synchronized with the input digital signal is required, and generally, that clock is a PLL (phase locked loop) as shown in Japanese Patent Application Laid-Open No. 62-47873.
It is reproduced from an input digital signal using a circuit.

Therefore, audio equipment that supports digital signals is also generally equipped with a PLL circuit to reproduce the clock, and when demodulating the input digital signal, the PLL circuit is
It uses a clock that is reproduced by a circuit.

Incidentally, as such a PLL circuit, a digital PLL circuit composed of digital circuits is sometimes used, but in this PLL circuit, operation is started using a reference clock generated from a crystal oscillator at startup. be done. Here, the oscillation frequency of the reference clock is set according to the sampling frequency of the input digital signal, and by using the reference clock, even if the digital signal has a different sampling frequency, the PL
It is designed to be pulled into the capture range of the L circuit. Therefore, depending on the input digital signal, the P
The operation of the LL circuit can be locked, and the PLL circuit can reproduce a clock synchronized with the digital signal.

(c) Problems to be solved by the invention The reference clock mentioned above becomes unnecessary after the operation of the PLL circuit is locked, but noise is mixed into the signal path due to unnecessary radiation generated by the reference clock when it is not needed. There were other problems. Further, the reference clock is not necessary even when no digital signal is input, and in this case as well, unnecessary radiation due to the reference clock is a problem.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a PLL circuit for clock regeneration that regenerates a clock for demodulating a digital signal input to an input terminal. an oscillation circuit that is configured to be able to stop its oscillation operation and that generates a reference clock when starting up the PLL circuit;
It consists of a lock detection circuit that detects that the operation of the L circuit is locked, and a stop signal generation circuit that generates a stop signal for stopping the oscillation operation of the oscillation circuit in accordance with the detection output of the lock detection circuit, The oscillation operation of the oscillation circuit is stopped in response to locking of the operation of the PLL circuit.

Also, an input detection circuit that detects that a digital signal is input to an input terminal, and an oscillation operation of an oscillation circuit that generates a reference clock of a PLL circuit for clock reproduction according to the detection output from the input detection circuit. A stop signal generation circuit is provided to generate a stop signal for stopping the oscillation circuit, and the oscillation operation of the oscillation circuit is stopped when no digital signal is input to the input terminal.

(f) Effect The present invention focuses on the fact that the reference clock of the PLL circuit is not required after the operation of the PLL circuit for clock regeneration is locked, and when no digital signal is input, the PLL circuit Focusing on the fact that the reference clock of the circuit is unnecessary, in such cases, the oscillation operation of the oscillation circuit that generates the reference clock is stopped to suppress unnecessary radiation caused by the reference clock.

(To) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (1) is an input terminal into which a digital signal is input, and (2) is a digital signal input into the input terminal (1). A demodulator (4) includes a PLL circuit (3) for regenerating a clock from the PLL circuit (3) and demodulates the digital signal using the clock regenerated by the PLL circuit (3); ) locks, the lock detection terminal changes from rH level to rL level, (5) is the inverter connected to the lock detection terminal (4), and (6) the output of the inverter (5) becomes rL. , a one-shot multi-vibrator (hereinafter referred to as one-shot multi) that is triggered by the rising edge from the level to "rH" level (7
) consists of a resistor (8) and a capacitor (9), and a time constant circuit (10) sets the time period during which the state of the one-shot multi (6) changes to an unstable state; ) and the output of the inverter (5>) are the inputs of the first NAND circuit, (11) is composed of a diode (12), a capacitor (13) and a resistor 14), and is input to the input terminal (1). (15) is a second NAND circuit whose inputs are the output of the rectifying and smoothing circuit (11) and the output of the first NAND circuit (10); (16) is a collector; is connected to one end of a crystal oscillator (17) for generating a reference clock used when starting up the PLL circuit (3) of the demosimulator (2), and the base is connected to the second NAND circuit via the base resistor (18). (15) is a common emitter type transistor connected to the output terminal.

By the way, in the demosimulator (2), for example, the 0 phase difference detection circuit (20) configured as shown in FIG. It detects the phase difference with the detected clock and generates a phase difference output according to the phase difference. From the clock selection circuit (21), a controlled oscillator (23) whose oscillation frequency is controlled according to the reference clock generated from the crystal oscillator (22) or the phase difference output of the phase difference detection circuit (20) is provided. ) is selectively output. Therefore, the phase difference detection circuit (20) outputs a phase difference according to the phase difference between the digital signal input to the input terminal (1) and the reference clock from the crystal oscillator 22, or outputs the digital signal. A phase difference output corresponding to the phase difference between the clock signal and the clock from the controlled oscillator (23) is selectively generated.

By the way, the lock detection circuit (24) detects that the phase difference detection circuit (20) eliminates the phase difference output between the digital signal input to the input terminal (1>) and the clock from the controlled oscillator (23). and the phase difference detection circuit (20
), a clock selection circuit (21) and the controlled oscillator (2
It is detected that the operation of the PLL circuit (3) consisting of (3) is locked. The lock detection circuit (24) causes the P
When the lock of the operation of the LL circuit (3) cannot be detected, the clock selection circuit (21) supplies the phase difference detection circuit (20) with the reference clock from the crystal oscillator (22) and the control oscillator (23). The clock from Here, when the reference clock from the crystal oscillator (22) is supplied to the phase difference detection circuit (20), the phase difference detection circuit (20) detects the digital signal input to the input terminal (1) and the reference clock from the crystal oscillator (22). Since the controlled oscillator (23) generates a phase difference output corresponding to the phase difference with the reference clock, the controlled oscillator (23) operates at an oscillation frequency corresponding to the phase difference between the digital signal and the reference clock. Therefore, the controlled oscillator (
The oscillation frequency of 23) is brought close to the sampling frequency of the digital signal, and falls within the range in which the phase difference detection circuit (20) operates with the digital signal and the clock generated from the controlled oscillator (23).

Since the phase difference detection circuit (20) is also supplied with a clock generated from the controlled oscillator (23), the input terminal (1
) will generate a clock synchronized with the digital signal input. Therefore, the phase difference detection circuit (20)
The lock detection circuit (24) detects that the phase difference output is no longer present.

When the lock detection circuit (24) detects that the phase difference output of the phase difference detection circuit (20) has disappeared, the lock detection circuit (24) generates a lock detection signal indicating this, and The lock detection signal fixes the clock selection circuit (21) in a state in which it selects the clock generated from the controlled oscillator (23). Therefore, the operation of the PLL circuit (3) is locked in accordance with the digital signal input to the input terminal (1), and the controlled oscillator (23) continues to generate a clock synchronized with the digital signal. The clock generated from the controlled oscillator (23) is used to demodulate the digital signal input to the demodulation circuit (25), but since the clock is synchronized with the digital signal, the input terminal The digital signal input to <1) is reliably demodulated by the demodulation circuit (25>) and output from the output terminal (19).

In FIG. 2, the parts shown in FIG. 1 are given the same figure numbers as in FIG. 1.

Next, the operation of the circuit shown in FIG. 1 will be explained.

When a digital signal is input to the input terminal (1), the digital signal is demodulated by the demodulator (2), but as explained in FIG. PLL circuit (
3>, a clock synchronized with the digital signal is regenerated. In a state where the operation of the PLL circuit (3) is locked, a lock detection signal is generated from the lock detection terminal (4), and the lock detection terminal (4) is r
The level changes from H level to L level. Here, when the digital signal input to the input terminal (1) is shown in Figure 3 (A), the lock detection terminal (4) ), at the time t when the digital signal is input to the input terminal (1), and the time tl when a shorter time has elapsed, rL
, become the level.

When the lock detection terminal (4) goes to the "L" level, the inverter (5) generates an "H" level output, so the Q output of the one-shot multi (6) is rH in the stable state. level to "L" level in an unstable state. Here, since the unstable state of the one-shot multi (6) continues for a predetermined time T set by the time constant circuit (<7), the output of the one-shot multi (6) is The result will be as shown in Figure (c).

The Q output of the one-shot multi (6) is input to the first NAND circuit (10). On the other hand, the output from the inverter (5) is input to the first NAND circuit (10). Therefore, the first NAND circuit (10) generates an output as shown in FIG. 3(d).

By the way, the digital signal input to the input terminal (1) can be supplied to the rectifying and smoothing circuit (11) in addition to being supplied to the demosulator 2). Here, the input terminal (1)
The digital signal input to the rectifying and smoothing circuit (11
), an appropriate DC voltage is obtained from the rectification and smoothing circuit (11) while a digital signal is input to the input terminal (1), as shown in FIG. 3 (N). Therefore, the second NAND circuit (15) whose inputs are the DC voltage obtained by the rectifying and smoothing circuit (11) and the output from the first NAND circuit (10) outputs as shown in FIG. is generated. Therefore, the transistor (
16) remains in the on state until a digital signal is input to the input terminal (1) and after the one-shot multi (6) returns from the unstable state to the stable state. Here, the crystal oscillator (22) (shown in Figure 2) that generates the reference clock when starting up the PLL circuit (3) starts oscillating when one end A to which the crystal resonator (17) is connected is grounded. It is designed so that the operation is stopped. Therefore, the oscillation operation of the crystal oscillator (22) is stopped when the transistor (16) is turned on. Therefore, the crystal oscillator (22) has an input terminal (
The oscillation operation starts at time t when the digital signal starts to be input to 1>, and after the lock detection terminal (4) reaches the r L level, the one-shot multi (6) unstable state continues. The oscillation operation is stopped at time t after the elapse of time.

By the way, from time t4 when the lock detection terminal (4) becomes the "LJ level" and the operation of the PLL circuit (3) is considered to be locked, the one-shot multi (6) is activated for a predetermined time T.
The reason why the crystal oscillator (22) continues to oscillate during this period is because the locking operation of the PLL circuit (3) is unstable immediately after the lock detection terminal (4) reaches the level rL. This is to prevent the oscillation operation of the crystal oscillator (22) from being stopped at this time. Therefore, the crystal oscillator<22)
After the digital signal is completely input to the input terminal (1), the operation of the PLL circuit (3) is locked and the oscillation operation is performed until the locked state is stabilized.

Therefore, the crystal oscillator (22) is connected to the PLL circuit (3)
The oscillation operation is performed when the reference clock from the crystal oscillator (22) is required at startup, and the operation of the PLL circuit (3) is performed when no digital signal is input to the input terminal (1). Oscillation operation is stopped when locked.

(g) Effects of the invention As described above, according to the present invention, the clock regeneration PL
Since the operation of the PLL circuit when the L circuit does not require a reference clock stops the oscillation operation of the oscillation circuit that generates the reference clock when the PLL circuit is locked, the input digital signal is demodulated by the demodulation circuit. In the steady state of the demodulation circuit, unnecessary radiation due to the reference clock can be prevented.

Further, according to the present invention, when no digital signal is input, the oscillation operation of oscillating the reference clock is stopped.1.
Therefore, in audio equipment that supports digital signals, the audio information to be played is not digital signals, but
When an analog signal is input, it is possible to prevent the negative influence of the reference clock.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 1 is a block diagram showing an example of the internal circuit of the demosimulator in FIG. 1, and FIG. 3 is a waveform diagram for explaining FIG. Explanation of main drawing numbers (1)...Input terminal, (2)...Demosimulator, (3)...PLL circuit, (4)...Lock detection terminal, (6)...One shot multivibrator,
(10) (15)... NAND circuit, (11)...
Rectifier and smoothing circuit, (16)...transistor, (2
2)...Crystal oscillator, (24)...Lock detection circuit. Figure 1

Claims (2)

[Claims] (1) An input terminal into which a digital signal is input, a PLL circuit for clock regeneration that regenerates a clock for demodulating the digital signal input to the input terminal, and an oscillation operation that can be stopped. Also, an oscillation circuit that generates a reference clock when the PLL circuit is activated, a lock detection circuit that detects that the operation of the PLL circuit is locked, and an oscillation circuit that generates oscillation of the oscillation circuit in accordance with a detection output of the lock detection circuit. A PLL for clock regeneration, comprising a stop signal generation circuit that generates a stop signal for stopping the operation, and the oscillation operation of the oscillation circuit is stopped in response to locking of the operation of the PLL circuit. Reference clock control device for the circuit. (2) An input terminal into which a digital signal is input, a PLL circuit for clock regeneration that regenerates a clock for demodulating the digital signal input to the input terminal, and an oscillation operation that can be stopped. In addition, an oscillation circuit that generates a reference clock when starting up the PLL circuit, an input detection circuit that detects that a digital signal is input to the input terminal, and an oscillation circuit that detects that a digital signal is input to the input terminal; and a stop signal generation circuit that generates a stop signal for stopping the oscillation operation of the oscillation circuit, and the oscillation operation of the oscillation circuit is stopped when no digital signal is input to the input terminal. A reference clock control device for a PLL circuit for clock reproduction.