JPH03102441A - Storage device - Google Patents

Abstract

PURPOSE:To improve the overall processing efficiency of a system by providing an exception processing part which monitors the presence or absence of a state where no access grant is returned to the access request signal of a prescribed preference level for a prescribed period and makes a basic processing means neglect another access request signal having a preference level higher than the first access request signal when the state is detected. CONSTITUTION:A logic circuit part consisting of the combination of AND gates 13 - 15 and inverters 18 - 20 serves as a basic processing part which produces the access grant signals Aa - Ac that are outputted to the output terminals Oa - Oc according to the preference levels of the access request signals Ra - Rc emerging at the input terminals 1a - 1c. A logic circuit part consisting of AND gates 11, 12, 16 and 17, inverters 21 and 22, counters 23 and 24, etc., serves as an exception processing part which performs an exception processing by invalidating a part of the function of the basic processing part. In such a constitution, the defects of a conflict solving method using only the preference levels are eliminated and the overall system processing ability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to
! 1 device.

(Prior art) A storage device installed in a computer system is connected to various processing devices such as a central processing unit and an input/output processing unit via a common bus, and is accessed by each processing device. ing.

In order to solve the problem of contention that occurs when each processing unit accesses a common storage device, each processing unit is given an access priority, and when access requests conflict, In some cases, a priority conflict resolution method is used, in which one person is given permission to do so.

(Problems to be Solved by the Invention) Under the conventional access conflict resolution method based on priority, as the access requests from each processing device become more crowded, the waiting time for access requests with lower priority becomes longer. There is a problem in that the processing efficiency of the system as a whole is rather reduced.

(Means for Solving the Problems) A storage device of the present invention receives access request signals with different priorities from a plurality of processing devices, and selects (1) (2) an access request to be granted according to each priority. In addition to the basic processing unit that returns an access permission signal to the request source processing device, it monitors whether or not an access permission is not returned for a predetermined period of time in response to an access request signal of a predetermined priority, and if this state is detected, the priority By providing an exception handling unit that causes the basic processing means to ignore access request signals with a higher priority than the priority level, the drawbacks of the conflict resolution method based only on priorities are eliminated and the processing efficiency of the entire system is improved. It is structured like a sea urchin.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

(Example of ability) FIG. 1 is a block diagram showing the structure of an access request processing section constituting a storage device according to an embodiment of the present invention.

This access request processing unit receives an access request R a '' R c from a common lot terminal using human power terminals Ta to b, an l, game l, 11 to 17, inharters 18 to 22, counters 23, 24, and registers 25, 26. , -Oc is sent to the output which returns the access permission signal Ab-Ac to the common lot.

The storage device including this access change processing unit is connected to three processing units AA, BB, and CC (all of which are not shown) via a common bus, and the processing unit AA has the highest priority access. The processing device BB is given the next highest priority access right, and the processing device CC is given the lowest priority access right. The highest priority access request signal R. from processing device AA. , 1 is the input end] a, the next highest priority access request signal Rb from the processing equipment BB is sent to the manual terminal 1b, and the lowest priority access request signal Rc from the processing device CC is sent to the input terminal IC. Appears in In addition, a cycle busy signal CY is input to the input terminal 1d.
C appears.

A logic circuit portion consisting of a combination of three AND gates 13, 14, 1.5 and three inharters 18, 1.9.20 receives access request signals Ra-Rc appearing at input terminals 1a to IC. Output terminal O a according to the priority of
= Access permission signal A a − A outputted to O c
The basic processing unit that issues c.

(3) (4) Also, and game-1-11. 12, 16.
1'7, inverters 21, 22, counters 23, 24, and other parts, the ri'iI path part is -I.
An exception handling unit is configured that performs exception handling by disabling a part of the functions of the base tree processing unit.

First, assuming the initial state immediately after system startup,
Both counters 23 and 24 do not overflow and maintain their respective output levels. For this reason,
Ant' game 1-1 1 output is access request signal R
The output of AND gate 12 is determined only by the presence or absence of access request signal Rb. Therefore, even if the outputs of AND gates 111 and 12 and Rc simultaneously rise to high level due to competition among access request signals Ra, Rb, and Rc, the low output of inharter 19 causes The outputs of AND gates 1 and 14 and 15 are held low, and only the access permission signal Aa based on the rise of the output of AND gate 13 to high is issued with priority.Furthermore, the outputs of AND gates 1 and 12 are {It is supplied to the two input terminals of the Antogame i.
If there is a conflict between b and R, the access permission signal Ab
is the access permission signal A. It will be published in advance of c.

As shown in the waveform diagram in Figure 2, when the highest priority access request Ra and the lowest priority access request R appear simultaneously in the initial state immediately after system startup, the output of 11 to ANDG-1 goes high. cycle busy signal C
After waiting for YC to fall, the outputs of ANDG-1 and 13 rise to high. The outputs of the AND game 1 and 13 are sent out onto the common lotus via the output terminal Qa as an access permission signal Aa in response to the access request signal Ra. The processing unit WAA, which has received the access permission signal Aa, lowers the access request signal Ra on the common lot to low, and then starts accessing the main body of the storage device. Access request signal R. During the period when a is high, the output of the AND gate 115 is fixed to low due to the low output of the inverter 19, and the access permission signal AC to the low priority processing device CC is not issued.

As illustrated in FIG. 2, when the access request signal Rb from the processing device BB is generated after the access request signal Ra from the processing device AA disappears, the access permission signal Ab goes high and the inverter 20 goes low. The outputs of the AND games 1 to 15 are fixed to low, and the issuance of the access permission signal Ac to the lowest priority processing device CC is further postponed. When the access request signal Ra is generated after the access request signal Rb disappears, the access permission signal A
1' of inverter 19 as 'a rises high again.
7=Issuance of the access punch signal to the processor CC is further postponed by the output.

The three-man power AND game 1-17 receives the clock signal CK at one human terminal, and receives the access request signal Rc inputted to the AND gate 15 and the output from the ant gate 15 at the remaining two input terminals. The access permission signal AC and the inverted borrow sign Re are received. Therefore, the clock signal CK passes through the AND gate 17 during the period in which the access permission signal Ac is not issued even though the access request signal Rc appears, and the counter 2
It is supplied to the count input terminal C of No. 4. This counter 2
4, when the cross signal CK is counted a predetermined number of times, it overflows and the output falls from high to low. In addition, this counter 24 is connected to the input terminal R when the system is started up.
When either the reset signal or the access permission signal AC supplied from ST is received via the or game I/28 to the load command terminal L, the predetermined first j! held in the register 26 is received. Load Jl value. Therefore, by changing the initial value set in the register 26, the number of chronograph signals CK supplied can be varied until the counter 24 produces an overflow.

In the example of FIG. 2, when six cross signals CK pass through the AND gate I.17 and are supplied to the count terminal C of the counter 24, this counter overflows and the AND gates 11 and 12 are combined. The two inputs (7) and (8) forces, and therefore their respective outputs, are fixed low.

As a result, neither access permission signals Aa nor AC are issued regardless of the presence or absence of access request signals Ra and Rb. That is, as illustrated in FIG. 2, even though the access request signal Rb is appearing, the output of the AND gate 15 is pulled high by the access request signal Rc of the lowest priority, and the access permission signal is raised. Ac is issued and output on the common lotus via the output terminal OC. Counter 2 receives this access permission signal Ac at load command terminal L.
At 4, the initial value in register 26 is I-coded to end the overflow condition and its output goes high. As a result, the low fixation of the outputs of AND games 1-11 and 12 is released, and the access request signal Ra
and Rb can be accepted. In the example shown in FIG. 2, both access request signals Ra and Rb appear at the same time, and the access permission signal Aa is first accessed in descending order of priority.
is issued and after this access is completed, the access permission signal A
b is issued.

Similarly, the logic circuit portion controlled by the inverter 21, the ant gate 16, the counter 23, the register 25, and the OR gate 27 has higher priority when the access permission signal Ab is not issued for a predetermined period after the access request signal Rb appears. It constitutes an exception handling unit for disabling acceptance of highly frequent access requests Ra. The operation of this exception handling unit is similar to the operation of the exception handling unit that responds to the access request Rc, which has already been explained, and therefore, a redundant explanation will be omitted.

The present invention has been described above using an example of a system in which there are three access source processing devices. However, 2
Suitability: The storage device of the present invention can be incorporated into a general system in which a large number of processing units η exist as access sources.

(Effects of the Invention) As explained in detail above, the storage device of the present invention has a basic processing unit based on the priority level, and also has the advantage that access permission is not issued for a predetermined period of time in response to an access request with a predetermined priority level. In this case, the basic processing unit is equipped with an exception handling unit that causes the basic processing unit to ignore access requests with a higher priority than this (9) (1 0) priority, thereby eliminating the drawbacks of the conflict resolution method based only on priorities. Therefore, the processing of the entire system is facilitated, and the processing capacity is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of an access request processing section constituting a storage device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of FIG. 1. Ia, Ib, Ic... Access request signal Ra. from the processing device. Rb. Rc manual terminal, Qa, ob, ○C
. . . Access permission signal Aa. to the request source processing device. Ab
, Ac output terminal, 13.14, 15; 18.19.2
0...AND gate and inverter forming a basic processing unit that issues access permission signals Aa-Ac according to the priority of access request signal RaxRc, 11.12.
16, 17; 21.22i23.24; 25, 26...
- AND gate, inheriter, counter, and initial value holding register that loads the counter for the exception handling section.

Claims (1)

[Claims] A basic processing unit receives access request signals with different priorities from a plurality of processing devices, selects an access request to be granted access according to each priority, and returns an access permission signal to the requesting processing device; an exception handling unit that monitors whether or not an access permission signal is not returned for a predetermined period of time in response to an access request signal, and when this status is detected, causes the basic processing unit to ignore an access request signal having a higher priority than the access request signal; A storage device characterized by comprising: