JPH03101375A - Halftone image estimating device - Google Patents

Abstract

PURPOSE:To simplify constitution by providing cascade-connected (n-1) line memories, offering an address in common to respective line memory, and writing read out image data on the line memory at the next stage as one-line delayed image data. CONSTITUTION:The read out image data is written on the line memory at the next stage as the one-line delayed image data. Since the address for the line memories 45a-45g is used in common, data 0 is written on another line memories 45b-45g until the image data of one line is written on the line memory 45a at an initial stage. However, at the next line, the image data read out from the line memory 45a is outputted, and the image data is written on the line memory 45b at the next stage, and simultaneously, the image data of one line supplied to a terminal 2a is written on the line memory 45a. In such a way, the number of line memories can be reduced, and selectors to be provided at the input/output stages of the line memory can be omitted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a halftone image estimating device that can satisfactorily estimate an original halftone image from, for example, two halftone images, and in particular, This allows the number of line memories required for processing to be reduced.

[Background of the Invention] Currently, many of the output devices such as display devices and printing devices that are in practical use are capable of representing only binary values of white and black.

A dither method, which is a type of area gradation method, is known as a method of expressing a halftone image in a realistic manner using such an output device.

As shown in Figure 5, the dither method uses a threshold matrix that has a predetermined threshold value and size (approximately 8x8 pixels) as shown in Figure 5 (B) for the original halftone image (Figure 5 (A)). (In this example, a Bayar type dither matrix) is used to perform binarization to create a dither image which is a pseudo halftone image as shown in FIG.

By the way, if the original halftone image can be estimated from such a dithered image, it will be possible to perform various data processing based on the estimated halftone image, and it will also be possible to have more freedom in image conversion. It's convenient.

To estimate a halftone image from a dithered image, a matrix of a predetermined size (hereinafter referred to as a scanning aperture) is prepared, and the number of white or black pixels existing within this scanning aperture and the number of pixels that satisfy the predetermined requirements are calculated. As a condition, the halftone level of the pixel of interest is estimated, and this is performed sequentially for each pixel. At this time, estimation is performed by moving the scanning aperture pixel by pixel in the row and column directions, and this is executed up to the last pixel to estimate a pseudo halftone image relative to the original halftone image.

When estimating a halftone image using a scanning aperture in this way, rather than using scanning apertures of the same area, the most suitable scanning aperture is selected according to the frequency characteristics of the original dither image, and By estimating the tone image (halftone level), it is possible to estimate a halftone image that is closer to the original halftone image.

This has a high pixel level gradation discrimination ability in the low spatial frequency region (region with few pixel level changes), but only a low pixel level gradation discrimination ability in the high spatial frequency region (region with many pixel level changes). The scanning aperture is selected such that a large scanning aperture is used in the low spatial frequency region and a small scanning aperture is used in the high spatial frequency region.

A specific example of estimating a halftone image based on such a principle has already been proposed by the applicant (for example, in Japanese Patent Laid-Open No. 63-267571, etc.), so a detailed explanation thereof will be omitted. As shown in FIG. 6, scanning apertures A to G and Z having eight different aperture areas can be used.

The black circles shown in each scanning aperture from A to Z are the centers of movement when moving on the dithered image in FIG. 5(c). Although the scanning aperture 2 is selected at the upper left pixel with respect to the center of movement, it may be selected at any position at the lower left, upper right, or lower right. By specifying the position of the scanning aperture in this manner, the estimated pixel position is also specified.

When a halftone image is estimated from the dithered image shown in FIG. 5(c) using such a scanning aperture, a halftone image as shown in FIG. 7(a) is obtained. This is very close to the original halftone image shown in FIG. 5(a).

The scanning aperture for each pixel used when estimating a halftone image is shown in FIG. 7(b). The pixel in the 1st row and 1st column is the scanning aperture, the pixel in the 1st row and the 2nd column is the scanning aperture, 1
It is as if the scanning aperture C is used for each pixel in row 3 and column 3.

A specific example for achieving such estimation processing is shown in FIG. 8 and subsequent figures.

In FIG. 8, an image reading device lfl reads an original image and converts it into binary data.

The original image is read using a photoelectric conversion element such as a CCD and converted into an electrical signal. The converted electrical signal is converted to digital data, and after applying shading correction (correction for equalizing CCD output) to this digital data,
A series of data processing is performed to convert the data into binary data (binary data constituting a dithered image) as shown in FIG. 5(C).

The digitized binary data can be supplied to the halftone image estimating means 2 and, if necessary, to the image memory unit 6. The halftone image estimating means 2 is a means used when reading binary data that has already been binarized from the image memory unit 6 and reprocessing it. In the case of binary data from the image reading device 1, since it has already become halftone data after being digitized, it is output to the subsequent stage without any particular processing. In addition to the binary data, the halftone image estimating means 2 can also be supplied with timing signals necessary for estimation processing.

Halftone image No. 48 is supplied to the image processing means 3 along with timing (No. 8), and image processing corresponding to the designated processing mode, such as enlargement/reduction and filtering processing, is executed.

The image-processed halftone image signal is supplied to the binarization means 4, and is binarized using the threshold selected by the threshold selection signal.
Value conversion processing is performed. Threshold selection No. 48 is designated from the control terminal or keyboard. 2
The value data is supplied to the recording device 5 via a selector 7, which will be described later, or is supplied to the image memory unit 6 and stored therein.

The selector 7 is used when performing halftone image estimation and image processing using the binary data stored in the image memory unit 6, and recording or storing the binary data that has been re-binarized. Ru.

That is, if the image size is re-binarized, the image size will decrease, so in that case, the reduced amount can be replenished by using the binary data in the image memory unit 6 used for the re-binarization. In this example, the binary data of the original dithered image stored in the image memory unit 6 for three rows above and below and three columns left and right can be reused as re-binarized binary data.

FIG. 9 shows an example of the configuration of FIG. 8 as an image processing system.

The image reading device 1, the halftone m-image estimation means 2, the image processing means 3, the binarization means 4 and the recording device 5 are connected to the control terminal 13 via first and second interfaces 11 and 12, respectively. Further, the image memory unit 6 is configured to be connected to the first interface 11 via a system path 14. 15 indicates an external device.

FIG. 10 shows an example of the halftone image estimation means 2.

Since the configuration disclosed in the above-mentioned publication can also be used for this, detailed explanation thereof will be omitted.

Binary data from the image reading device 1 is supplied to the terminal 2a. The binary data is supplied to the line memory section 22 via the first selector 21.

The line memory section 22 is for receiving the binary data sent from the first selector 21 and storing the binary data for each line. Consists of line memory. Then, the first selector 21 sequentially selects and stores binary data corresponding to each line in each of these nine line memories L1 to L9.

The line memory for 9 lines is prepared here because the maximum number of lines of the scanning aperture G to be used is 8 lines, and one more line memory is required for real-time processing. be.

Therefore, the second selector 23 can select eight line memories necessary for the current image processing out of nine line memories. When using eight line memories, these can be combined with a latch@path. At this time, the input binary data is supplied to the latch circuit. In such a case, eight lines of binary data can be obtained using the latch circuit output and the outputs of seven line memories excluding the line memory currently being written.

The binary data of each of the eight selected line memories is supplied to the halftone image estimating section 30, and based on this binary data, a unique scanning aperture is selected from among the plurality of types of scanning apertures.

Data indicative of the selected scan aperture is provided to a selection circuit 24 to estimate the value of the halftone image determined by the pixel level and gain within that scan aperture. Here, the gain corresponds to the area ratio of the scanning aperture, and the gain corresponds to the area ratio of the scanning aperture G.
When the gain of is 1, the scanning apertures E and F have a gain of 2,
The scan aperture has a gain of 4, scan apertures B and C have a gain of 8, scan aperture A has a gain of 16, and scan aperture Z has a gain of 64.
becomes. In the same figure, 8-g, Z are each scanning aperture A-G.
, indicates the number of white pixels at Z.

Various timing signals obtained from the timing generation circuit 25 are supplied to the above-mentioned selectors 21 and 23, as well as the line memory section 22, halftone image estimation section 30, and selection circuit 24, and the data is processed at the necessary timing. Selection and address sending are controlled.

Timing signals are synchronized clocks, horizontal effective area signals)
1-VALID, refers to vertical valid area No. 48 V-VALID.

The halftone image estimation section 30 is provided to perform the following processing.

In other words, this estimating unit 30 sets a plurality of scanning apertures including the pixel of interest whose halftone level is to be estimated, counts the number of white or black pixels within a specific scanning aperture, and based on the counting result of this specific scanning aperture. The binary image created by the process is compared with the binary image of the original scanning aperture of this specific scanning aperture.

If the determination result is not established, a unique scanning aperture is determined by performing the above-mentioned counting and comparison determination for each scanning aperture.

When the determination is true, it is determined whether the number of white or black pixels within each scanning aperture satisfies a predetermined condition;
Determine the unique scanning aperture.

[Problems to be Solved by the Invention] As described above, when estimating a halftone image using an 8×8 matrix, image data for a minimum of 8 lines is required.

In order to perform real-time processing, the line memory unit 22 uses nine line memories L1 to L9, and selectors 21 and 23 for selecting input and output image data are used in the input and output stages. Ru.

Therefore, in addition to an increase in the number of line memories used, selectors 21, 23, etc. are required, and the configuration becomes complicated.

Therefore, the present invention solves these problems and proposes a halftone image estimation device that reduces the number of line memories used and achieves the initial objectives with a simple configuration.

[Means for Solving the Problems 1] In order to solve the above-mentioned problems, in this invention, a matrix-shaped scanning aperture consisting of a plurality of pixels is sequentially moved pixel by pixel in the row and column directions, and the central pixel is In a halftone image estimation device that estimates the level of a halftone image, n-1 line memories are provided in order to estimate a halftone image using n lines of image data (n is an integer), and these line memories are They are connected in cascade and each line memory is supplied with a common address.
The image data read from each line memory is used for halftone image estimation processing, and the read image data is written to the next line memory as image data delayed by one line. , the above image data that has been output from each line memory, and
This method is characterized in that a halftone image is estimated using image data of the current line.

[Function] When processing a halftone image using 8 lines, 7 lines
The line memories 45a to 45g can be used completely.

The image data read from each is written into the next stage line memory as image data delayed by one line.

Before the estimation process is executed, initial settings are performed so that the data in all line memories becomes O.

Next, since the addresses of the line memories 45a to 45g have been shared, the first line memory (the n-1 line memory if the current line is n lines)
Until the line worth of image data (D00 to D in) is written, data 0 is written to the other line memories 45b to 45g (FIGS. 2A and 2B).

However, in the next line, the image data (D00 to D in) read from the line memory 45a is output, and this image data (D00 to D In) is transferred to the next line memory (line n-2). line memory) 45b (C in the same figure). At the same time, one line of image data (DIO-1) 20) is supplied to the terminal 2a.
is written to line memory 45 part 1; it is broken (C in the same figure).

Since such operations are repeated in sequence, the state shown in FIG. 2E will be reached after 7 ins, and the image data will be written in all the line memories 45a to 45g. Therefore, from the scan of the next line, all the image data from line n to line n-7 can be simultaneously output one pixel at a time from this line memory section 40.

Since the image data written to each of the line memories 45a to 45g is updated line by line, the input/output stages of the line memories 45a to 45g do not require selectors like the conventional ones.

[Example] Hereinafter, a halftone image estimation device according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

FIG. 1 shows an example of the halftone image estimating means 2, which is the main part of the present invention, in which binary image data completely supplied to the terminal 2a is stored in the line memory section 40 as image data for eight lines. After that, the image is supplied to the halftone image estimating section 30. The line memory used in the line memory section 40 can be a RAM having addresses for one line.

As mentioned above, when estimating a halftone image using an 8x8 matrix, at least 8 lines (n is the number of pixels on one side of the estimation matrix; in this example, n = 8
) image data is required. Therefore, the line memory section 40 has n-1=7 line memories 45a to 45.
g is used.

Seven line memories 45a to 45g are connected in cascade as shown in the figure, and latch circuits 43a to 43g are provided at each input/output stage.
, 44a to 44g are provided.

A latch circuit 43 connected to the first stage line memory 45a
Input image data is supplied to the terminal 2a from the terminal 2a.

The input image data can be directly supplied to the halftone image estimating section 30 via the latch circuits 41 and 42, and each latch output of the line memories 45a to 45g is supplied to the halftone image estimating section 30.
It is designed to be supplied to

Therefore, if the current line supplied to the terminal 2a is n lines, the line memories 45a to 45g each contain seven lines delayed by one line (line n-1 to n-
7 lines) of image data is output.

When the line memories 45a to 45g are configured with RAM as described above, an address is commonly supplied to each of them.

Now, the operation when the line memory section 40 is configured in this manner will be described next. The line memories 45a to 45g are designed to be able to perform read and write operations within one cycle of the clock supplied thereto.

Therefore, initially each line memory 45a to 45g
No image data is written to (Figure 2A)
.

In the first line, the image data (
DOO-Don) is written into the first stage line memory 45a. At this time, since there is no image data written immediately before in this line memory 45a, all image data of O is written in the line memories 45b to 45g in the next stage and subsequent stages (FIG. 2B).

This remains the same until writing of image data for one line is completed. This is because the line memories 45a to 4
This is because although an address is commonly supplied to 5g, the address is sequentially updated in the horizontal direction.

In the next line, a new line of image data (D10 to Dln) supplied to the terminal 2a is stored in the line memory 45a.
At the same time, the line memory 45
The image data (DOQ-Don) read from a is written pixel by pixel onto the same address in the next stage line memory 45b. Therefore, when writing of one line of image data is completed, the result will be as shown in FIG. 2C.

Similar read and write processing is executed on the next line, resulting in a new line of image data (D20 to D2n) supplied to the terminal 2a as shown in the second diagram.
is written into the line memory 45a, and at the same time, the image data (DIO to D
in) is written on the same address of the next stage line memory 45b, and the image data (D00 to Don) read from the line memory 45b is written on the same address of the next stage line memory 45C.

Therefore, ultimately all line memories 45a to 4
Immediately before image data (D6
0~D6n)~(DOO-Don) is written (
Figure 2E). Therefore, from the next line, image data is sequentially read out one pixel each from all of the line memories 45a to 45g (seven lines) and from all eight lines in total, including the current line.

Note that the latch circuits 43a to 43g provided before the line memories 45a to 45g are connected to the line memories 45a to 45g.
This is a latch circuit for adjusting the write timing for g, and the latch circuits 44a to 44g at the subsequent stage are for adjusting the timing for read outputs 01 to 08. The latch circuits 41 and 42 provided on the current line are also used for timing adjustment.

Since the line memory section 40 is configured in this manner to sequentially shift the image data supplied to the terminal 2a, a selector at the previous stage is not required.

Roughly speaking, since the outputs of the line memories 45a to 45g are supplied as they are to the halftone image estimating section 30, a selector at the subsequent stage is also unnecessary.

Next, the above-mentioned read and write operations for the line memory will be explained in detail using FIGS. 3 and 4.

In FIG. 3, the previous stage latch circuits 41, 43a, 43
b is a clock CK synchronized with the pixel.

(Fig. 4A) is supplied. Image data is read at the high level and written at the low level. and,
Write enable signal WT supplied to this (C in the same figure)
The image data latched in can be read out.

The subsequent latch circuits 42, 44a, 44b receive a clock CKI(
B) in FIG. 4 is fully supplied, and an output of 0 for each line is obtained at its output terminal.

The above-mentioned write enable signal Tτ and output enable signal σ are supplied to the line memories 45a and 45b constituted by RAM. The output enable signal σπ is the clock CK.

is synchronized with. Each of the line memories 45a and 45b is driven by a common address signal (D in the same figure).

In FIG. 3, the operation will be explained using only two line memories 45a and 45b.

Line memory 45a synchronizes with the rising edge of clock CKo.
, 45b has been read out completely, and this is latched by the latch circuits 41, 43 (43a, 43b) in the previous stage (FIG. 4F). Then, in synchronization with the rising edge of the latch clock CKI, which is delayed by a predetermined time from the clock CKo,
This time, the latch circuits 42, 44 (44a, 44b) in the latter stage
) The image data read out is latched (G in the same figure).
.

The image data latched by the latch circuit 43 at the subsequent stage is written in synchronization with the fall of the write enable signal τT applied to the line memories 45a and 45b.

Here, the write enable number 8 τ is the clock CKo.
Since the period is selected to be the same as that of the clock CKo, reading and writing of the image data is completed within one period of the clock CKo (E in the same figure). Moreover, since the address is common, the fourth
When image data at address AO is read out as shown in FIG. E, writing processing is performed at the same address Ao.

The line memory 45b includes the previous line memory 4.
The image data read out in step 5a is transferred to the previous stage latch circuit 43.
Since the image data is latched at Ao, the image data written to the same address Ao is stored in the line memory 45 located at the previous stage.
This is the image data written to the same address AO of a. Image data written to the same address AO is 1
Since it is not referenced again until after the line has passed, the delay time between the preceding and following line memories 45a and 45b is exactly one line, and it is possible to provide one line of delay time between the preceding and following line memories. In total, a delay time of 7 lines is given.

In the above example, a binary dither image was used as the original image, but instead of a binary dither image, a multi-value image (
It is easy to understand that the present invention can also be applied to the case where a ternary dither image, etc.) is used and the halftone image level is estimated.

[Effect of the invention] As explained above, in this invention, continuously connected n
- It has one line memory, and a common address is supplied to each line memory, and read image data is written to the next line memory as image data delayed by one line. It is composed of

According to this, in addition to the feature that the number of line memories can be reduced, the selector provided at the input/output stage of the line memory can be omitted, so that the structure can be simplified accordingly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the essential parts of a halftone image estimation device according to the present invention, FIG. 2 is a diagram for explaining memory operation, and FIG. 3 is used for explaining memory operation in detail. Figure 4 is a partial diagram of the line memory section, and Figure 5 is its waveform diagram.
The figure is an explanatory diagram when creating a dithered image from an original halftone image, FIG. 6 is a diagram showing an example of the scanning aperture used, and FIG. 7 is an illustration of the estimated halftone image obtained when the scanning aperture is selected. - A diagram showing an example and a diagram showing an example of the selection of the aperture used thereafter, FIGS. 8 and 9 are system diagrams showing a specific example of the halftone image estimation device, and FIG. 10 is a diagram showing the example of the halftone image estimation means. It is a system diagram. 1 ・ 2 @ 3 ・ 4 ・ 5 Fist 24 ・ ・Image reading device・Halftone image estimation means・Image processing means・Z value conversion means・Recording device・Selection circuit 25 ・ ・ 30 ・ ・ 40 ・ ・ 41.43 ・・ 42.44 ・ ・ 45a to 45g ・Timing generation circuit・Halftone image estimation section・Line memory section・Previous stage latch circuit・Later stage latch circuit・Line memory

Claims (1)

[Claims] (1) In a halftone image estimation device that estimates the level of the center pixel by sequentially moving a matrix-like scanning aperture consisting of a plurality of pixels one pixel at a time in the row and column directions, In order to estimate a halftone image using image data, n-1 line memories are provided, these line memories are connected in cascade, each line memory is supplied with a common address, and
The image data read from each line memory is used for halftone image estimation processing, and the read image data is written to the next line memory as image data delayed by one line. , the above image data output from each line memory,
A halftone image estimating device characterized in that a halftone image is estimated using image data of a current line.