JPH03100734A - Controller interruption control system - Google Patents

Abstract

PURPOSE:To eliminate the hungry state of a control system which uses plural interruption levels by varying an interruption level according to the frequency of an interruption of the same classification. CONSTITUTION:The frequencies of respective interruption classifications are counted by interruption frequency counters 9-11 by the respective interruption classifications. The counting results are transferred to a bus arbitor and interruption level varying circuit 4, which varies the level of an interruption to a central processing unit (CPU) according to a predetermined rule. Here, outputs A-C of a 3X3 switch 8 correspond to the interruption levels and input/output devices 5-7 normally correspond to the outputs A-C, but when the frequency of the interruption from, for example, an input/output device 5 increases, the switch 8 makes a reconnection to the output C to vary the interruption level. Consequently, the hungry state wherein an interruption of low interruption level is not accepted by the processing unit at all is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method for a control device that controls a plurality of input/output devices using a central processing unit (CPU).

[Conventional technology]

FIG. 5 shows an example of the configuration of a control device using a conventional interrupt control method, and includes three central processing units (CPU
) is an example of a multiprocessor configuration using

In the figure, 51 to 53 are central processing units (CPUs);
Reference numeral 54 represents a bus arbitration circuit, 55 represents an input/output device (1), 56 represents an input/output device 1 (2), and 57 represents an input/output device (3).

In this example, it is assumed that the input/output devices (1) to (3) have different interrupt levels, and the central processing units (CPUs) 51 to
53 has, for example, three interrupt level terminals, and processes the input from the terminals as if an interrupt request of the corresponding market level has occurred.

The bus arbitration circuit 54 includes a plurality of central processing units (CPUs) 5
When there is a request to use the bus from 1 to 53 at the same time, one of the central processing units (C
PU) is permitted to use the path.

As this algorithm, for example, there is a method of granting permission to the central processing unit (c p u ) that made the earliest request.

Here, it is assumed that, for example, the interrupt level of the input/output device (i) ss is the highest, and the interrupt level of the input/output device (3) 57 is the lowest.

In such a control device consisting of a plurality of input/output devices 55 to 57 and a central processing unit (CPU) 5 to 53, when a signal from the input/output device is processed by the central processing unit (CPU) by interrupt processing, If multiple interrupt levels are set and processing with a high interrupt level is being performed, interrupts with a low interrupt level will not be accepted, but if processing with a low interrupt level is being performed, interrupts with a high interrupt level will not be accepted. Accepts interrupts and assigns a fixed priority to the processing order depending on the type of interrupt.

For example, when an input/output device (1) 55 receives an interrupt, the central processing unit (CPU) that has received permission to use the path from the path arbitration circuit 54 receives an interrupt at the interrupt level of the input/output device (1) 55. interrupt processing.

During the above processing, even if an interrupt request is received from the input/output device (3) 57, if the same central processing unit (CPU) has received permission to use the path, then the central processing unit (CPU)
does not accept this interrupt request because it is processing a higher level interrupt; if another central processing unit <c p u > is not in use, that central processing unit (CPU) accepts the interrupt.

In other words, whichever of the three central processing units (CPU) you look at, if there is a higher level interrupt, it will process it, but it will not process lower level interrupts. Don't do it.

[Problem to be solved by the invention]

In such a control device, if signals with a high interrupt level occur frequently, interrupts with a lower interrupt level will not be accepted by the processing device at all (
starvation).

The present invention is intended to prevent such processing equipment from starving.

(Means for solving n!1) According to the present invention, the above object is achieved by the means described in the claims.

That is, the present invention is equipped with one or more central processing units and a plurality of input/output devices, and can handle a plurality of interrupt types that require different processing by the central processing unit from the input/output devices.
Central processing 1i with multiple interrupt levels with different priorities
means for measuring the number of interrupts for each interrupt type in a control device that is received by the ta and performs interrupt processing;
This is a control device interrupt control method that has means for changing the interrupt level to the central processing unit, and changes the interrupt level according to the frequency of interrupts of the same type.

[For production]

In the present invention, when the interrupt frequency of an interrupt type with a high ts9 interrupt level increases, the interrupt level of the interrupt type with a high interrupt frequency is lowered, or the interrupt level of the interrupt type with a high IRQ interrupt frequency is This is a method of temporarily disabling interrupts, etc., so that processing is performed starting with interrupt types that have a low frequency of interrupts.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention, and shows an example of the configuration of a control VC device that implements the interrupt control method of the present invention.

In the figure, 1 to 3 are central processing units (CPUs), 4 is a path arbitration/interrupt level change circuit, and 5 is an input/output device [
(1), 6 is input/output device (2), 7 is input/output device (3)
, 8 is a 3x3 switch, 9 to 11 are counters (COU(
1)~C0U(3)), 12 is Tie W (Tiger
).

In this embodiment as well, a case will be described in which three central processing units (CPU) are provided, as in the case of the conventional example.

The central processing units (CPUs) 1 to 3 and input/output devices 5 to 7 are the same as those of the conventional ones, and the bus arbitration/interrupt level change circuit 4 has the same path arbitration function as the conventional one. 1
A new function has been added to generate a change signal for changing the mixing level.

Counters (COU(1) to COU(3)) 9 to 11 are counters for counting the number of interrupts at each interrupt level, and a timer 12 is used to set a time for measuring the number of interrupts w4'.

Here, it is configured using 3X3 switches, and these 3
The ×3 switch 8 is the circuit portion that actually changes the interrupt level, and the outputs A, B, and C of the 3×3 switch 8 correspond to the interrupt level.

Normally, input/output devices (1) to (3) correspond to outputs A-C, respectively, but for example, when the number of interrupts from input/output device (1) increases, this can be changed to the switch of 3X3 switch 8. Depending on the operation, the interrupt level is changed by changing the connection to output C.

In this way, the path arbitration/interrupt level change circuit 4 controls the switching operation of the 3X3 switch 8.

Although an example in which the interrupt level differs for each input/output device is shown here, other cases can be implemented in the same manner. The interrupt frequency for each interrupt type is calculated using the interrupt frequency counter (COU) for each interrupt type.
(1) to C0U(3)) 9 to 11. The interrupt count counters 9 to 11 are reset by the timer 12 at regular intervals;
A value of ~11 represents the frequency of interruptions during a certain period of time.

The results measured by the counters 9 to 11 are transferred to the bus arbitration/interrupt level change circuit 4, and as shown in FIG. The Ii9 interrupt level change circuit changes the interrupt level for the central processing unit (CPU). Here, the output A of 3X3 switch 8
-1゜For example, in state ■, counter (1) is within the set value and counter (2) and counter (3) exceed the set value.
The input/output device (1) is set to the highest interrupt level, the input/output devices (2) and (3) are set to the next interrupt level, and no output is output to the lowest interrupt level (output C).

Also, as in state ■, all input/output devices (1).

When the number of interrupts (2) and (3) increases, all input/outputs 8111 (1), (2), and (3) are set to output A, and outputs B and C are not output.

In this way, according to the present invention, an input/output device that has a large number of interrupts is set to a low interrupt level, and when a plurality of input/output devices have an increased number of interrupts, they are all set to a low level.

In the above example, multiple central processing units (CPUs)
This was a case where the interrupt level was changed all at once, but next, in another embodiment of the present invention, the processing device changes the interrupt level individually.
FIG. 3 shows an apparatus configuration for changing the embedding level.

In the figure, 20 is a central processing unit (CPU);
1.22 is the changeover switch, 23 is the 7th date, 24 is the inverter, 25.26 is the counter (COU (1)
, COU (2)'), 27 is a timer (Ti theory
).

In this example, the interrupt level of interrupt types (1) and (2) for the central processing unit (CPU) 20 is set by the switch 2.
This is an example of changing using 1.22. FIG. 4 shows the correspondence between the states of counters (1) and (2) in this circuit and the inclusion types for inputs A and B of the central processing unit F[ffi.

Here, the interrupt type with a large number of interrupts is set to a lower interrupt level, but if all interrupt types have a large number of interrupts, the interrupt level is not changed.

In the circuit configuration of the embodiment described above, the interrupt level for the interrupt type is changed, but the interrupt is not transmitted to the central processing unit for a specific interrupt type (1!l
Another option is to prohibit access.

〔Effect of the invention〕

By using the present invention, it is possible to eliminate starvation in a control system that uses multiple interrupt levels.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram explaining the interrupt level changing operation, FIG. 3 is a diagram showing another embodiment of the present invention, and FIG. 4 is a diagram showing the counting of the counter. FIG. 5 is a diagram showing the correspondence between states and types of 111 interrupts to the central processing unit. FIG. 5 is a diagram showing an example of the configuration of a control device using a conventional interrupt control method. 1 to 3...Chuoro m device (CPU), 4 ・
...pass 10% -119 included level change circuit,
5 ... Input/output device (1), 6 ・
...Input/output device (2), 7...
・Input/output device (3), 8...3x3 switch, 9-11...Counter (COU(1)~
CoU(3)), 12... Timer,
20...Central processing unit (CPU),
21.22...Switch, 23-...
...7nd date, 24 ...Inverter, 2526 ...Counter (COU)
(1), COU (2)), 27... Timer

Claims (1)

[Scope of Claims] Equipped with one or more central processing units and a plurality of input/output devices, a plurality of interrupt types that require different processing from the input/output devices in the central processing unit can be handled by a plurality of interrupt types having different priorities. The control device receives and processes interrupts at an interrupt level of the central processing unit, the control device having means for measuring the number of interrupts for each interrupt type, and means for changing the interrupt level to the central processing unit,
A control device interrupt control method characterized by changing an interrupt level depending on the frequency of interrupts of the same type.