JPH03100472A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To improve detection response and accuracy by making the charging speed for a peak hold fast and making the charging speed slow in the vicinity of the peak value. CONSTITUTION:The peak value of an input signal is held by a capacitor 5 and the value held by the capacitor 5 is made to have different magnifications respectively by a comparing level generating circuit 6 to generate plural comparing levels R(1)-R(n). The input signal is compared with the levels R(1)-R(n) by comparators 7(1)-7(n), and a charging current to the capacitor 5 is made ON/OFF by charging circuits 8(1)-8(n) in accordance with the output signals of corresponding comparators. When the setting is being made as R(1)<R(2)-<R(n) at this time, the capacitor 5 is charged with all of the charging currents at the initial time when the input signal is inputted, thereby the charging speed of capacitor 5 is accelerated and the response or peak value detection is improved. When the holding voltage is boosted, the comparing level becomes high and the charging circuit corresponding to the comparator with higher level is turned OFF resulting in the slow charging speed, and the detection accuracy can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a peak hold circuit that detects the peak value of an input signal, the purpose of this invention is to improve both the response and accuracy of peak value detection, and to provide a capacitor that holds the peak value of the input signal. , a comparison level generation circuit that generates a plurality of comparison levels by multiplying the hold value of the capacitor at different rates, a plurality of comparators that respectively compare the input signal with each comparison level of the comparison level generation circuit, and a plurality of comparators that respectively compare the input signal with each comparison level of the comparison level generation circuit. A plurality of charging circuits are provided corresponding to each comparator and turn on/off the charging current to the capacitor according to the output signal of the corresponding comparator.

[Industrial Application Field] The present invention relates to a peak hold circuit that detects the peak value (crest value) of an input signal.

A peak hold circuit is used, for example, in a communication system.
It is used for purposes such as detecting the peak value of the input signal in order to set the optimal reception threshold value when receiving high-speed signals input with different peak values depending on the system configuration.

This peak hold circuit is required to be able to follow changes in the peak value of the human input signal at high speed and to detect the peak value with high accuracy.

[Prior Art] A conventional example of a peak hold circuit is shown in FIG. This peak hold circuit includes a comparator 10 and a constant current source 20.
, a switch circuit 30, a capacitor 1, a constant current source 2, and the like.

The capacitor 1 is for holding the peak value of the input signal having the peak value Vin. The comparator 10 compares the peak hold voltage Vpk stored in the capacitor 1 with the input voltage Vin, and depending on the result, the capacitor 1
This circuit outputs a signal that controls whether or not to charge the battery. Further, the constant current source 20 is a circuit that generates a charging current of a constant value for charging the capacitor 1, and the switch circuit 30 controls the charging of the capacitor 1 from the constant current source 20 according to the output signal from the comparator 10. This is a circuit that performs ON10FF switching. Note that the constant current source 2 is a current source for discharging the capacitor 1, and its discharging current is set to be sufficiently smaller than the charging current of the constant current source 20.

The operation of this conventional circuit will be explained below with reference to the time chart of FIG. Figure 5 shows the peak value V of AMI, etc.
The input signal in and the peak hold voltage Vpk of capacitor 1 when this input signal is input are shown, respectively.

First, when the input signal Vin shown in FIG. 5 is input to the peak hold circuit, the peak hold voltage V of the capacitor 1 is
pk changes as shown. That is, from time To to time TI, peak hold voltage Vpk is equal to input voltage V.
Since the output signal of comparator 10 is greater than °
As a result, the switch circuit 3 is turned off and the capacitor 1 is not charged from the constant current source 20. Therefore, the peak hold voltage Vpk is slowly discharged by the constant current source 2 and lowered. Except for the minutes,
is kept at a constant value.

Next, from time TI to T2, since the peak hold voltage Vpk is smaller than the input voltage Vin, the output signal of the comparator 10 becomes "H", and the switch circuit 30 turns OFF.
N, the constant current source 20 charges the capacitor l, and the peak hold voltage Vpk gradually increases. Furthermore, from time T2 to T3, the switch circuit 30 is OF in the same way as from time To to TI described above.
F, and the peak hold voltage Vpk is kept almost constant.

From time T3, the switch circuit 30 is turned on again to resume charging, and the peak hold voltage Vpk increases again. Then, at time T4, the peak hold voltage V
When pk exceeds the input voltage Vin, the output signal of the comparator 10 becomes L" and the charging current is stopped. From then on, the peak hold voltage Vpk gradually increases and decreases around the peak value Vin of the input signal, and This means that the peak value of the signal has been detected.

[Problems to be Solved by the Invention] A peak hold circuit is required to be able to follow changes in the peak value of an input signal at high speed and to be able to detect the peak value with high accuracy.

In order to improve the former response, it is necessary to reduce the peak hold time, which can be achieved by increasing the value of the charging current from the constant current source 20. However, in that case, after the peak hold voltage Vpk becomes the input voltage Vin, the comparator lO senses it and turns off the switch circuit 30.
Since it takes a certain amount of time to reach the peak hold voltage, if the charging current flowing during that time is large, the peak hold voltage Vpk will greatly exceed the input voltage Vin, that is, the overvoltage valve will become large, and as a result, the peak hold voltage The detection accuracy of the circuit deteriorates.

Conversely, in order to increase detection accuracy, constant current source 20
It would be better to reduce the charging current from the sensor, but in that case, of course, the peak hold time becomes longer and the responsiveness of detection deteriorates.

As described above, in conventional circuits, there is a trade-off relationship between responsiveness and accuracy.

Therefore, an object of the present invention is to improve both the responsiveness and accuracy of peak value detection.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

The peak hold circuit according to the present invention includes a capacitor 5 that holds the peak value of an input signal, and a comparison level generation circuit that generates a plurality of comparison levels R■ to R■ by multiplying the hold value of the capacitor 5 at different magnifications. 6, a plurality of comparators 7■ to 7@ for comparing the input signal with each of the comparison levels R■ to R@ of the comparison level generation circuit 6, and a plurality of comparators 7■ to 7@, respectively, provided corresponding to the plurality of comparators 7■ to 7@. The charging current J to the capacitor 5 is determined according to the output signal of the corresponding comparator.
It is equipped with a plurality of charging circuits 8■ to 8■ for turning on/off J■.

In the above-described peak hold circuit, the plurality of charging circuits can be set so that the charging currents of the plurality of charging circuits increase in descending order of the comparison level value of the corresponding comparator.

[Function] For example, if the comparison level R■~R@ is set to R■<R■...kuR■, all charging circuits 8■~8■ will be in The comparators 7■-7■ are turned on, and the capacitor 5 is charged with all the charging currents J■-J■. Therefore, the charging speed of the capacitor 5 becomes faster, and the responsiveness of peak value detection becomes better.

When the hold voltage of the capacitor 5 rises as it is charged, the comparison levels R2 to R@ also rise, and eventually the corresponding charging circuits are turned off in order from the comparator with the higher comparison level. As a result, the charging current to the capacitor 5 becomes only the charging current J■ in the vicinity of the peak value, and the charging speed becomes slow, thereby improving the detection accuracy.

It is more effective to set the magnitude of the charging current in descending order of the comparison level of the corresponding comparator.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

A peak hold circuit as an embodiment of the present invention is shown in FIG. In the figure, 11.12.13 are comparators,
21.22.23 is a constant current source for charging, 31.32.3
3 is a switch circuit, l is a capacitor for peak hold, 2 is a constant current source for discharging, and 3 is a peak voltage level conversion circuit.

Here, a comparator 11, a constant current source 21. The switch circuit 31, the capacitor l, and the constant current source 2 form one peak hold circuit similar to that explained in the conventional example,
Also, a comparator 12, a constant current source 22, a switch circuit 3
The comparator 13, the constant current source 23, the switch circuit 33, etc. form another peak hold circuit.

Here, the first peak hold circuit is used as a basic circuit, and the latter two peak hold circuits are used as auxiliary circuits.

Each comparator 11, 12, 13 receives the input signal Vin at its inverting input terminal, and receives comparison voltages Vpk1, Vpk2, Vp from the peak voltage level conversion circuit 3 at its non-inverting input terminal.
k3 are respectively input. This comparison voltage V pk 1
, Vpk2, and Vpk3 are the peak hold voltage Vpk output from the capacitor 1 and the peak voltage level conversion circuit 3.
The comparison voltage V pk 1 is made equal to the peak hold value Vpk, and the other comparison voltages Vpk2 and Vpk3 are each made larger than the peak hold value Vpk. That is, Vpkl=Vpk Vpkl <Vpk2 <Vpk3.

Further, the current value J1 of the constant current source 21 is set to a fairly small value, and the current values J2 and J3 of the constant current sources 22 and 23 are each set to be larger than the current value J1. That is, Jl<J2<J3.

The operation of the above-described embodiment circuit will be explained below with reference to the time chart of FIG. This figure 3 shows the output signals Sl, S2, S from each comparator, 11.12.13.
3. Input signal Vin, each comparison voltage Vpkl, Vpk2,
A Vpk3(7) time chart is shown.

It is now assumed that the hold voltage of the capacitor 1 is Vo at time TO when the input signal Vin is -L''. This hold voltage Vo is level-converted by the peak voltage level conversion circuit 3 and sent to each comparator 11, 12, 13. They are supplied as comparison voltages Vo 1, Vo 2, and Vo 3. As a result, in the period To to TI, each comparator 11.12
．． 13 is "L", and each switch circuit 31
．． 32 and 33 are both OFF. Therefore, since the capacitor l is not charged, the peak hold voltage V
pk remains approximately constant.

Next, a period T1 to T2 during which the peak value of the input signal becomes Vin
In , each comparator 11.12.1 at time TI
The output signal of 3 becomes "H" and each switch circuit 31.3
2.33 is turned ON, thereby constant current sources 2I, 22.
23, charging currents J1, J2, and J3 are simultaneously charged to the capacitor 1. As a result, the peak hold voltage Vpk of capacitor 1 rises rapidly.

Eventually, at time T2, the value of the comparison voltage Vpk3 exceeds the input voltage Vin, and as a result, the output signal of the comparator 13 becomes "L", turning off the switch circuit 33.
The charging current J3 from the constant current source 23 is cut off. As a result, in the remaining period T2-T3, the capacitor l is charged only by the charging currents J1 and J2, and the charging speed is slower than that in the period T1-T2.

Continuing (In the period T3 to T4, the peak hold value Vpk of the capacitor 1 is kept at a nearly constant value as in the period To-Tl, and charging of the capacitor 1 is resumed at time T4 when the peak value of the human power signal becomes Vin again. In this case, since the comparison voltages smaller than the input voltage Vin are vpkl and Vpk2, the current values J1 and J
2, charging is performed.

When the comparison voltage Vpk2 eventually exceeds the input voltage Vin,
The switch circuit 32 is turned off by the comparator 126B, and the charging current J2 is cut off, and the current that charges the capacitor 1 becomes only the charging current Jl, which has the smallest value.

As a result, the charging speed becomes slow, so even when the peak value is detected at time T6 (that is, when the comparison voltage Vpk and the input voltage Vin match), as shown in FIG. Overvoltage due to delay is suppressed to a small level, making it possible to detect peak values with high accuracy.

Various modifications are possible in implementing the invention. For example, in the above embodiment, a total of three peak hold basic circuits and auxiliary circuits were prepared, but the present invention is not limited to this. Also, in the above embodiment, the magnitudes of the charging currents J1, J2, and J3 were made different, but it is of course possible to construct a circuit by making these current values equal. .

[Effects of the Invention] According to the present invention, by increasing the charging speed of the capacitor for peak hold, the responsiveness of detecting the peak value of the input signal can be improved, and at the same time, the charging speed near the peak value can be increased. By slowing down the speed, more accurate peak value detection can be achieved. Further, the peak hold circuit of the present invention is suitable for LSI implementation, and has the advantage that it can be implemented without worrying too much about the influence of variations in capacitance values.

30-33...Switch circuit

Claims (1)

[Claims] 1. A capacitor (5
), a comparison level generation circuit (6) that generates a plurality of comparison levels (R[1] to R[n]) by multiplying the hold value of the capacitor (5) at different rates, and converts the input signal into the comparison level. a plurality of comparators (7[1] to 7[n]) that respectively compare the comparison levels (R[1] to R[n]) of the generation circuit (6); ] to 7[n]), and turns on/off the charging current (J[1] to J[n]) to the capacitor (5) according to the output signal of the corresponding comparator. A peak hold circuit comprising a plurality of charging circuits (8[1] to 8[n]). 2. The plurality of charging circuits (8[1] to 8[n]) charge their charging currents (J[1] ] to J[n]) is set to be large.