JPH029937U - - Google Patents

Info

Publication number
JPH029937U
JPH029937U JP8572288U JP8572288U JPH029937U JP H029937 U JPH029937 U JP H029937U JP 8572288 U JP8572288 U JP 8572288U JP 8572288 U JP8572288 U JP 8572288U JP H029937 U JPH029937 U JP H029937U
Authority
JP
Japan
Prior art keywords
probe
cpu
emulation
target circuit
mounting terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8572288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8572288U priority Critical patent/JPH029937U/ja
Publication of JPH029937U publication Critical patent/JPH029937U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは、本考案のエミユレータモジユ
ールを示す図、第2図、及び第3図は、各々従来
のエミユレータモジユールを示す図である。 1……ターゲツト回路、1a……CPU取付端
子、3……エミユレータモジユール、3a……プ
ローブ、3b……ポツド(POD)、3c……信
号ライン、3d……ケーブル、3e……CPU、
3f……CPU端子。
FIGS. 1a and 1b are views showing an emulator module of the present invention, and FIGS. 2 and 3 are views showing conventional emulator modules, respectively. 1...Target circuit, 1a...CPU mounting terminal, 3...Emulator module, 3a...Probe, 3b...POD, 3c...Signal line, 3d...Cable, 3e...CPU ,
3f...CPU terminal.

Claims (1)

【実用新案登録請求の範囲】 ターゲツト回路1のCPU取付端子1aにプロ
ーブ3aを接続することによりポツド3bを介し
てターゲツト回路の各種試験を行なうためのエミ
ユレーシヨンモジユール3であつて: 前記プローブ3aの至近にエミユレーシヨン用
のCPU3eを配置し、エミユレーシヨン用のC
PUの電源は、ターゲツト回路のCPU取付端子
1aからプローブを介して供給されることを特徴
とするエミユレーシヨンモジユール。
[Claims for Utility Model Registration] An emulation module 3 for performing various tests on a target circuit via a pot 3b by connecting a probe 3a to a CPU mounting terminal 1a of the target circuit 1, comprising: A CPU 3e for emulation is placed close to the probe 3a, and a CPU 3e for emulation is placed close to the probe 3a.
An emulation module characterized in that power for the PU is supplied from a CPU mounting terminal 1a of a target circuit via a probe.
JP8572288U 1988-06-30 1988-06-30 Pending JPH029937U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8572288U JPH029937U (en) 1988-06-30 1988-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8572288U JPH029937U (en) 1988-06-30 1988-06-30

Publications (1)

Publication Number Publication Date
JPH029937U true JPH029937U (en) 1990-01-23

Family

ID=31310373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8572288U Pending JPH029937U (en) 1988-06-30 1988-06-30

Country Status (1)

Country Link
JP (1) JPH029937U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0295446U (en) * 1989-01-17 1990-07-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0295446U (en) * 1989-01-17 1990-07-30

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