JPS63140647U - - Google Patents
Info
- Publication number
- JPS63140647U JPS63140647U JP1987032972U JP3297287U JPS63140647U JP S63140647 U JPS63140647 U JP S63140647U JP 1987032972 U JP1987032972 U JP 1987032972U JP 3297287 U JP3297287 U JP 3297287U JP S63140647 U JPS63140647 U JP S63140647U
- Authority
- JP
- Japan
- Prior art keywords
- mounting component
- connection terminals
- basic circuit
- circuit
- electrical connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の実施例を示す図（基本回路搭
載部品）、第２図は本考案の実施例を示す図（応
用回路搭載部品）、第３図は本考案の作用説明図
、第４図は従来技術の説明図である。
第１図ないし第３図において、１は基本回路搭
載部品、２は応用回路搭載部品、３はプリント板
、２２，２３，・・・２７，３２，３３，・・・
３７は電気的接続端子、１８は基本回路、２８は
応用回路である。
Fig. 1 is a diagram showing an embodiment of the present invention (basic circuit mounted parts), Fig. 2 is a diagram showing an embodiment of the present invention (applied circuit mounted parts), and Fig. 3 is an explanatory diagram of the operation of the present invention. FIG. 4 is an explanatory diagram of the prior art. In Figures 1 to 3, 1 is a basic circuit mounting component, 2 is an applied circuit mounting component, 3 is a printed board, 22, 23, . . . 27, 32, 33, . . .
37 is an electrical connection terminal, 18 is a basic circuit, and 28 is an applied circuit.
Claims (1)
数本の電気的接続端子３２，３３，３４，３５，
３６，３７が上方に突出している基本回路搭載部
品１と、 応用回路２８を搭載し該応用回路２８に対し上
記基本回路１８の電気的接続端子３２，３３，３
４，３５，３６，３７に対応して複数本の電気的
接続端子２２，２３，２４，２５，２６，２７が
下方に突出している応用回路搭載部品２とから成
り、上記相対応する電気的接続端子どうし（３２
と２２，３３と２３，３４と２４，３５と２５，
３６と２６，３７と２７）を嵌着せしめることに
より上記基本回路搭載部品１の上に重ねて応用回
路搭載部品２を接合しプリント板３に実装可能と
したことを特徴とする高密度複合部品。[Claims for Utility Model Registration] A basic circuit 18 is mounted, and a plurality of electrical connection terminals 32, 33, 34, 35,
A basic circuit mounting component 1 with 36 and 37 protruding upward, and an applied circuit 28 are mounted thereon, and electrical connection terminals 32, 33, 3 of the basic circuit 18 are connected to the applied circuit 28.
4, 35, 36, 37, and an applied circuit mounting component 2 in which a plurality of electrical connection terminals 22, 23, 24, 25, 26, 27 protrude downward in correspondence with the above-mentioned electrical connections. Connection terminals (32
and 22, 33 and 23, 34 and 24, 35 and 25,
36 and 26, and 37 and 27), so that the applied circuit mounting component 2 can be bonded over the basic circuit mounting component 1 and mounted on the printed board 3. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987032972U JPS63140647U (en) | 1987-03-06 | 1987-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987032972U JPS63140647U (en) | 1987-03-06 | 1987-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63140647U true JPS63140647U (en) | 1988-09-16 |
Family
ID=30840145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987032972U Pending JPS63140647U (en) | 1987-03-06 | 1987-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63140647U (en) |
-
1987
- 1987-03-06 JP JP1987032972U patent/JPS63140647U/ja active Pending
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