JPH0295918U - - Google Patents
Info
- Publication number
- JPH0295918U JPH0295918U JP352389U JP352389U JPH0295918U JP H0295918 U JPH0295918 U JP H0295918U JP 352389 U JP352389 U JP 352389U JP 352389 U JP352389 U JP 352389U JP H0295918 U JPH0295918 U JP H0295918U
- Authority
- JP
- Japan
- Prior art keywords
- mos
- fet
- pair
- push
- pull type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案の一実施例を示す接続図、第
２図は第１図のＭＯＳ―ＦＥＴの特性を示す特性
図。
１…信号入力端子、２…信号出力端子、３…特
性曲線、４…動作点、５…ゲートバイアス電圧に
重畳した入力信号電圧、６…ドレイン電流、ＴＲ
１，ＴＲ２…一対のＭＯＳ―ＦＥＴ、Ｒｖ…可変
抵抗、ＶＢ…バイアス電源。
FIG. 1 is a connection diagram showing an embodiment of this invention, and FIG. 2 is a characteristic diagram showing the characteristics of the MOS-FET shown in FIG. 1...Signal input terminal, 2...Signal output terminal, 3...Characteristic curve, 4...Operating point, 5...Input signal voltage superimposed on gate bias voltage, 6...Drain current, TR
1, TR2...pair of MOS-FET, Rv...variable resistor, VB...bias power supply.
Claims (1)
シユプル形に入力されるプツシユプル形電力増幅
器において、 上記一対の半導体素子として一対のＭＯＳ―Ｆ
ＥＴを用い、 この一対のＭＯＳ―ＦＥＴの各ＭＯＳ―ＦＥＴ
のゲートに上記入力信号をプツシユプル形に入力
し、 上記各ＭＯＳ―ＦＥＴのゲートに供給する直流
バイアス電圧をそれぞれ調整して上記一対のＭＯ
Ｓ―ＦＥＴの等価利得を互いに同一にする手段を
備えたことを特徴とするプツシユプル形電力増幅
器。[Claim for Utility Model Registration] In a push-pull type power amplifier in which an input signal to be amplified is input to a pair of semiconductor elements in a push-pull type, a pair of MOS-F as the pair of semiconductor elements.
Using ET, each MOS-FET of this pair of MOS-FET
The above input signal is inputted in a push-pull type to the gate of each MOS-FET, and the DC bias voltage supplied to the gate of each MOS-FET is adjusted respectively.
A push-pull type power amplifier comprising means for making the equivalent gains of S-FETs the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP352389U JPH0295918U (en) | 1989-01-18 | 1989-01-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP352389U JPH0295918U (en) | 1989-01-18 | 1989-01-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0295918U true JPH0295918U (en) | 1990-07-31 |
Family
ID=31205231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP352389U Pending JPH0295918U (en) | 1989-01-18 | 1989-01-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0295918U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6175609A (en) * | 1984-09-21 | 1986-04-18 | Nippon Gakki Seizo Kk | Power amplifier circuit |
-
1989
- 1989-01-18 JP JP352389U patent/JPH0295918U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6175609A (en) * | 1984-09-21 | 1986-04-18 | Nippon Gakki Seizo Kk | Power amplifier circuit |