JPH029488B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] By using a latch type memory as the memory element of the path metric memory of a Viterbi decoder that uses addition, comparison, and selection circuits in time division, and by changing the multiplexing method, a path metric memory can be realized. The circuit scale can be reduced by omitting part of the circuit.

[Industrial application field]

The present invention relates to a path metric memory circuit, and particularly to an LSI that uses addition, comparison, and selection circuits in a time-sharing manner.
The present invention relates to a Viterbi decoder.

As the constraint length increases in the Viterbi decoder, the circuit scale of the path metric memory increases.

This has the disadvantage that the device becomes larger,
This improvement was strongly desired.

[Conventional technology]

The Viterbi decoder is used for transmission paths with a lot of random noise, such as satellite communications, and in order to prevent errors from occurring due to noise coming from the transmission path, the Viterbi decoder This is a decoder that performs decoding by selecting the sequence that most closely matches the received code sequence from among all transmission code sequences that may exist for the received code sequence and determines information symbols. Regarding the Viterbi decoder, please refer to the following materials.

"Coding Theory - co-authored by Hiroshi Miyagawa, Yoshihiro Iwadare, and Hideki Imai - published by Shokodo" In the Viterbi decoder, addition and
Repeat the compare/select (ACS-add compare select) operation many times.

The Viterbi decoder requires the same number of ACS circuits as the internal states of the encoder, but in order to reduce the circuit scale, one ACS circuit is provided, and there are also write circuits for each state before and after this ACS circuit. A memory and a read memory (referred to as a path metric memory) are provided to perform arithmetic processing in a time-division manner.

FIG. 3 is a diagram showing an example of a conventional Viterbi decoder.

FIG. 4 is a time chart of FIG. 3.

In the figure, 1 is an ACS circuit, 2 is a path metric memory, W0 to W6 are write memories, and R0 to W6 are write memories.
R7 is a read memory, 3, 4, 6, and 7, respectively.
are each selectors.

In Figures 3 and 4, the restraint length K = 4
An example is shown below.

As can be seen from FIG. 3, the path metric memory 2 is composed of write memories W0 to W6 and read memories R0 to R7, both of which use D-type flip-flops as memory elements in this example.

Since the constraint length K=4, the ACS circuit 1 performs ACS calculation eight times during one symbol clock.

That is, at the beginning of one symbol clock, the branch metric information is calculated and read into the ACS circuit 1 via the selectors 6, 7 depending on the internal state.

The ACS circuit 1 reads a predetermined path metric value from the read memories R0 to R7 via the selectors 3 and 4, performs ACS calculation, and writes the calculation result (path metric value) to the write memory in the corresponding state. The above operation is in state 000, state 001,
This is performed for states 010, . . . (hereinafter referred to as states 0 to 7).

The conventional ACS calculation will be explained below with reference to FIGS. 3 and 4.

8 clock CLKs between 1 symbol clock
0 to CLK7 are sequentially applied to perform the following operations.

Reading memory R of path metric memory 2
It is assumed that data D10 to D17 have already been written to 0 to R7.

The clock CLK0 reads the data D10 written in the memory R0 via the selector 3 and the data D14 written in the memory R4 via the selector 4. After the ACS circuit 1 performs the ACS operation, the output data D20 is Write to memory W0.

The clock CLK1 reads the data D10 written in the memory R0 via the selector 3 and the data D14 written in the memory R4 via the selector 4. After the ACS circuit 1 performs the ACS operation, the output data D21 is Write to memory W1.

By performing the same operation below, Data D20 goes to memory W0, Data D21 goes to memory W1, Data D22 goes to memory W2, Data D23 goes to memory W3, Data D24 goes to memory W4, Data D25 goes to memory W5, Data D26 is written to memory W6.

The clock CLK7 reads out the data D13 written in the memory R0 via the selector 3 and the data D17 written in the memory R4 via the selector 4. After the ACS circuit 1 performs the ACS operation, the output data D27 is At this time, the data D20 of the memory W0 is transferred to the memory R7.
0, Data D21 in memory W1 goes to memory R1, Data D22 in memory W2 goes to memory R2, Data D23 in memory W3 goes to memory R3, Data D24 in memory W4 goes to memory R4, Data D25 in memory W5 goes to memory Data D26 in memory W6 is transferred to R5 and memory R6, respectively.

Therefore, new data D20 to D27 are written to the read memories R0 to R7 of the path metric memory 2.

1 using path metric memory 2 like this
Performs 8 ACS calculations between symbol clocks,
Store in path metric memory 2.

[Problem that the invention seeks to solve]

As can be seen from the above description of the conventional method, when using the ACS circuit in time division multiplexing, twice the memory capacity is required for reading and writing, and as the constraint length increases, the number of states also increases dramatically.

For example, if the constraint length K=7, the number of states increases to 64. Therefore, the size of the path metric memory is 2×64=128 sets.

The drawback is that the circuit scale increases dramatically.

An object of the present invention is to reduce the circuit size when using an ACS circuit in a time-division manner by appropriately selecting the order of internal states and by configuring the path metric memory as a latch.

[Means for solving problems]

The above problem can be solved by using a latch type memory as a memory element in the path metric memory 5 which is provided in the Viterbi decoder and stores the path metric values output from the addition/comparison/selection circuit 1 used for time division. This problem can be solved by omitting part of the path metric memory by changing the order of internal states and the phase of the clock that accesses the read memory.

[Effect]

According to the present invention, when multiplexing an ACS circuit, part of the path metric memory can be reduced by appropriately selecting the order of internal states, and the path metric memory can be created using a latch circuit with a smaller circuit scale than a D-type flip-flop. , the circuit scale of the entire path metric memory can be reduced.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a Viterbi decoder according to the present invention.

FIG. 2 is a time chart of FIG. 1.

In the figure, 5 is a path metric memory according to the present invention.

Note that the write memories W0 to W6 and the read memories R0 to R7 constituting the path metric memory 5 according to the present invention are all latch type memories.

ACS circuit 1 in the conventional system shown in Figure 6
The internal state was in the order 0→1→2→3→4→5→6→7.

In the present invention, the internal states of the ACS circuit 1 are multiplexed in the order of 0→1→4→5→6→7→2→3 as shown in FIG.

If you change the order of the internal states like this, for example, 3
At the time of the th internal state 4, the read memory R4 has already been read when the internal state was 0 and 1, and therefore will not be read until the internal state becomes 0 again in the next symbol.

That is, the write memory W4 in internal state 4 is not necessary, and the path metric value can be written directly to the read memory R4.

Further, the contents of the write memories W0 to W7 may be transferred after the contents of the corresponding read memories R0 to R7 are read out, until they are written to the memory next.
There is no problem even if the symbol crosses over to the next symbol clock.

Therefore, as shown in FIG.
It becomes possible to omit W3, W4, and W6.

The state of the D-type flip-flop changes with a cross-queue. On the other hand, in a latch type memory, when the enable signal is "1ow", a change in the input appears on its side output, but when the enable signal is "high", it retains the state just before the enable signal went "high". different.

In both of the embodiments described above, the constraint length K=4, but if the constraint length K≧4, it is possible to handle the internal state in the same way by converting it into a binary number and dividing it into 8 groups according to the upper 3 digits. .

Furthermore, by increasing the degree of multiplicity, it is possible to further reduce the number of memories.

Furthermore, when converting into an LSI, a latch type memory is smaller than a D type flip-flop, so it is possible to reduce the number of memories and further downsize.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the circuit scale of the path metric memory can be reduced, which has a great effect on converting the device into an LSI.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a Viterbi decoder according to the present invention. FIG. 2 is a time chart of FIG. 1. FIG. 3 is a diagram showing an example of a conventional Viterbi decoder. FIG. 4 is a time chart of FIG. 3. In the figure, 1 is an ACS circuit, 2 is a path metric memory, W0 to W6 are write memories, and R0 to W6 are write memories.
R7 is a read memory, 3, 4, 6, and 7, respectively.
are selectors, and 5 is a path metric memory according to the present invention.

Claims (1)

[Claims] 1. A path metric memory 5 provided in the Viterbi decoder and storing path metric values output from the addition/comparison/selection circuit 1 used for time division.
Viterbi decoding characterized in that a latch type memory is used as a memory element, and a part of the path metric memory is omitted by changing the order of internal states and the phase of a clock that accesses the read memory. vessel.