JPH0294529A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0294529A JPH0294529A JP24415788A JP24415788A JPH0294529A JP H0294529 A JPH0294529 A JP H0294529A JP 24415788 A JP24415788 A JP 24415788A JP 24415788 A JP24415788 A JP 24415788A JP H0294529 A JPH0294529 A JP H0294529A
- Authority
- JP
- Japan
- Prior art keywords
- buffer layer
- yas
- less
- layer
- yal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 4
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 239000000203 mixture Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 3
- 230000005516 deep trap Effects 0.000 abstract description 2
- 230000005264 electron capture Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 34
- 241001547860 Gaya Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 101100148117 Bacillus subtilis (strain 168) rsoA gene Proteins 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 241000220317 Rosa Species 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＩｎＰ基板上にエピタキシャル成長して作成し
たＩｎＡ Ｑ Ａｓ／ ＩｎＧａＡｓ系ヘテロ構造電界
効果トランジスタの高抵抗バッファ層の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a high-resistance buffer layer of an InA Q As/InGaAs heterostructure field effect transistor formed by epitaxial growth on an InP substrate.
従来、ＩｎＰ基板上に形成されるＩｎｘＧａｔ−ｘＡｓ
／ＩｎｙＡ Ｑ １−ｙＡｓヘテロ構造ＦＥＴのＩｎｙ
Ａ Ｑ ｔ−ｙＡｓＡｓバラフッＩｎ組成比ｙはＩｎＰ
基板に格子整合するように、０．５２ の値が用いられ
ていた。この最近の良い報告例として１９８８年春季応
用物理学関係連合講演会予稿集３０ｐ−ＺＢ−１１／ｍ
ｐ、１００３ において論じられている。Conventionally, InxGat-xAs formed on an InP substrate
/InyA Q 1-yAs heterostructure FET Iny
A Q t-yAsAs rose fill In composition ratio y is InP
A value of 0.52 was used to lattice match the substrate. An example of a recent good report is the Proceedings of the Spring 1988 Applied Physics Conference 30p-ZB-11/m
Discussed in p. 1003.
ＩｎＰ基板は１０１１！Ｉｃ＋＋＋−”程度のｎ形不純
物が含まれ半絶縁化するためにＦｅがドーピングされて
いる。上記従来技術ではこの基板上に
Ｉｎｏ、Ｉ！ｌｚＡ Ｑ ０．４８Ａ８バツフア一層を
エピタキシャル成長すると、このｎ形不純物がエピタキ
シャル層中に拡散し、ＩｎｙＡ Ｑ ｘ−ｙＡｓは１０
１１ｓＣｍ−”前後の電子濃度を持つｎ形になり、高抵
抗になりにくい。InP substrate is 1011! It contains an n-type impurity of the order of Ic+++-" and is doped with Fe to make it semi-insulating. In the conventional technique described above, when a single layer of Ino, I!lzA Q 0.48A8 buffer is epitaxially grown on this substrate, this n-type The impurity diffuses into the epitaxial layer and InyA Q x-yAs is 10
It becomes an n-type with an electron concentration of around 11sCm-'' and is unlikely to have high resistance.
従って、バッファー層リーク電流などの発生により、ｎ
チャンネルＩｎｘＧａｘ−ｘＡｓ／ ＩｎｙＡ Ｑ ｔ
−ｙＡｓ系ＦＥＴにおいて、ピンチオフ不良、高周波特
性不良を生じるという問題があった。Therefore, due to the occurrence of buffer layer leakage current, n
Channel InxGax-xAs/ InyA Q t
-YAs-based FETs have had problems in that pinch-off failures and high-frequency characteristic failures occur.
本発明の目的は、高抵抗のＩｎｙＡ Ｑ ｚ−ｙＡｓバ
ッファー層を提供することにある。It is an object of the present invention to provide a high resistance InyA Q z-yAs buffer layer.
上記目的を達成するために、ＩｎｙＡ Ｑ ５−ｙＡｓ
バッファー層のＩｎ組成ｙを０．５１以下ないし０．５
５以上の値とした。In order to achieve the above purpose, InyA Q 5-yAs
The In composition y of the buffer layer is 0.51 or less to 0.5
The value was set as 5 or more.
また、Ｉｎｘ（ＧａｙＡ ｎ １−７）１−ＸＡＳ系材
料をバッファー層として用いる場合には、５．８６４Å
以下ないし５．８８０Å以上の格子定数を採用する。In addition, when using Inx(GayA n 1-7)1-XAS material as a buffer layer, the thickness of 5.864 Å
A lattice constant of 5.880 Å or less is adopted.
ここで、バッファー層の不純物含有量は零（真性）又は
１０１６ｃｍ−”以下のｐ形不純物である。Here, the impurity content of the buffer layer is zero (intrinsic) or p-type impurity of 10<16>cm<-> or less.
ＩｎｙＡ Ｑ ｚ−ｙＡｓのＩｎ組成比ｙを０．５１
以下ないし、０．５５以上にすることによってＩｎｙＡ
Ｑ １−ｙＡｓ中にディープ・トラップ・レベル（深
い電子捕獲準位）が発生し、ＩｎｙＡ Ｑ ｚ−ｙＡｓ
中のｎ形不純物により発生した電子を捕獲し高抵抗にな
る。In composition ratio y of InyA Q z-yAs is 0.51
InyA by setting it less than or equal to 0.55
A deep trap level (deep electron trap level) occurs in Q 1-yAs, and InyA Q z-yAs
The electrons generated by the n-type impurities inside are captured, resulting in high resistance.
第２図はアンドープＩｎｙＧａｔ−ｙＡｓバッファー層
中の電子濃度とｙの関係を示したものである。電子濃度
はｙが０．５１ 以下で急激に、０．５３ から０．５
５ にかけてゆるやかに減少している。FIG. 2 shows the relationship between the electron concentration in the undoped InyGat-yAs buffer layer and y. The electron concentration suddenly increases from 0.53 to 0.5 when y is less than 0.51.
It is gradually decreasing until 5th.
Ｉｎｘ（ＧａｙＡ Ｑ ５−ｙ）１−ｘＡｓ系材料によ
るバッファー層を用いた場合では、格子定数で５．８６
４Å以下及び５．８８０Å以上の範囲で電子濃度の低下
がみられた。When using a buffer layer made of Inx(GayA Q 5-y)1-xAs-based material, the lattice constant is 5.86.
A decrease in electron concentration was observed in the range of 4 Å or less and 5.880 Å or more.
なお、当然ながら、これらのバッファー層にＢｅやＺｎ
などのＰ形不純物を１０１５ｃｍ−８以下ドーピングし
てもピンチオフ特性改善になどにおいて効果があるのは
接合論上明らかである。Of course, these buffer layers contain Be and Zn.
It is clear from junction theory that doping with P-type impurities such as 10@15 cm@-8 or less is effective in improving pinch-off characteristics.
実施例１
本発明の実施例１の選択ドープヘテロ構造ＦＥＴを第１
図により説明する。Ｆｅドープ半絶縁性ＩｎＰ基板１上
に分子線エピタキシー法によりアンドープＩｎｏ 、
ｓｏＡ Ｑ ｏ 、 ！ｌ０Ａｓバッファー層２を１１
００ｎ、アンドープＩｎｏ、 ５ａＧａｏ、４ｏＡｓ層
３を５０ ｎ ｍ 。Example 1 The selectively doped heterostructure FET of Example 1 of the present invention was
This will be explained using figures. Undoped Ino,
soAQo,! l0As buffer layer 2 to 11
00n, undoped Ino, 5aGao, 4oAs layer 3 of 50 nm.
アンドープＩｎｏ 、 ！ＩＯＡ Ｑ ｏ 、 ５ｏＡ
ｓ層４を２ｎｍ、Ｓｉドープ（２Ｘ １０ ”ｃｍ−８
） Ｉｎｏ、ｎｏＡ Ｑ ｏ、ｎＡｓ層５を１５ ｎ
ｍ 、アンドープＩｎｏ、ａｏＡ Ｑ ｏｍｓｏＡｓ層
６を４０ｎｍ順次成長した。このウェハ上にＡｕＧｅＮ
ｉオーミック電極によりソース７とドレイン８を形成し
、更に、０．６μｍ長のＡｆｌゲート９を形成した。Undoped Ino! IOA Qo, 5oA
The s-layer 4 is 2 nm thick and Si-doped (2X 10"cm-8
) Ino, noA Q o, n As layer 5 is 15 n
m, undoped Ino, and aoA Q omsoAs layers 6 were sequentially grown to a thickness of 40 nm. AuGeN on this wafer
A source 7 and a drain 8 were formed using i-ohmic electrodes, and an Afl gate 9 having a length of 0.6 μm was further formed.
本実施例によれば、Ｉｎｏ、２ＩｏＡ Ｑ ｏ＊５ｏＡ
ｓバッファー層２が高抵抗になり、第３図に示すような
ピンチオフ特性の良好なＦＥＴが得られる。一方、バッ
ファー層に従来のようなＩｎＰに格子整合するようなＩ
ｎｏ、３ｚＡ Ｑ ０．４１１Ａ８を用いた場合Ｉｎｏ
、ｓｚＡ Ｑ Ｏ，４！ＩＡｓは２．５ Ｘ １０１１
１ｃｍ−ｓのｎ形を示し、第４図に示すようなピンチオ
フ特性不良を生じた。According to this embodiment, Ino, 2IoA Q o*5oA
The s-buffer layer 2 has a high resistance, and an FET with good pinch-off characteristics as shown in FIG. 3 can be obtained. On the other hand, in the buffer layer, I
no, when using 3zA Q 0.411A8 Ino
, szA Q O, 4! IAs is 2.5 x 1011
It exhibited an n-type of 1 cm-s, and a pinch-off characteristic failure as shown in FIG. 4 occurred.
第３図の特性を示したトランジスタはＪＴ＝１２０ＧＨ
ｚを示したが、第４図の特性を示したトランジスタはｆ
ｒ＝２０ＧＨｚに留まった。The transistor exhibiting the characteristics shown in Figure 3 is JT=120GH.
z, but the transistor exhibiting the characteristics shown in Figure 4 is f.
r remained at 20 GHz.
実施例２
第５図は、ｐ −ｉ −ｎ接合形ＦＥＴの構造で、Ｆｅ
ドープＩｎＰ基板１０上にアンドープＩｎｏ、ｇｏ（Ｇ
ａｏ、２ｏＡ Ｑ ａ、ｎｏ）ｏ、５ｏＡＳバツフア一
層１１を１１００ｎ、ＳｉドープＩｎｏ、ｎＧａｏ、ｔ
ＢＡｓ層（ｎ＝ ２．Ｘ １０１７ｃｍ−８） １２を
１１００ｎ、アンドープＩｎｏ、ｓｏＡ Ｑ ０．５Ｏ
ＡＳ層１３を４０ｎｍ、ＢｅドープＩｎｏ 、 ｌ５ｏ
Ａ Ｑ ｏ 、 ５ｏＡｓ層（ｐ ＝ ５ Ｘ １０
”ｃｍ−３）１４を１０ｎｍ、アンドープＩｎｏ、ｓｏ
Ａ Ｑ ｏ、５ｏＡｓ層１５を２ｎｍ順次エピタキシャ
ル成長し、ＡｕＧｃＮｊ合金でソース電極１６．ドレイ
ン電極１７を形成後ＡＱゲート電極（ゲート長０．６μ
ｍ）を形成しＦＥＴ構造とした。バッファー層１１の格
子定数は５．８５９人でキャリア濃度１０ ”ｃｍ−’
以下を示し、第３図と同等の良好なピンチオフ特性が得
られた。このトランジスタはｆ丁＝６０ＧＨｚの高性能
を示している。Example 2 FIG. 5 shows the structure of a p-i-n junction type FET.
Undoped Ino, go (G
ao, 2oA Q a, no) o, 5o AS buffer single layer 11 1100n, Si-doped Ino, nGao, t
BAs layer (n = 2.X 1017cm-8) 12 to 1100n, undoped Ino, soA Q 0.5O
The AS layer 13 is 40 nm thick, Be-doped Ino, l5o.
A Q o , 5oAs layer (p = 5 x 10
"cm-3) 14 to 10 nm, undoped Ino, so
A Q o, 5oAs layer 15 is epitaxially grown to 2 nm in thickness, and a source electrode 16 is made of an AuGcNj alloy. After forming the drain electrode 17, the AQ gate electrode (gate length 0.6μ
m) to form an FET structure. The lattice constant of the buffer layer 11 is 5.859, and the carrier concentration is 10"cm-'
As shown below, good pinch-off characteristics equivalent to those shown in FIG. 3 were obtained. This transistor exhibits high performance of f = 60 GHz.
本発明によれば高抵抗バッファー層が再現性良く得られ
るので、ピンチオフ特性・高周波特性に優れたトランジ
スタが作製できる。According to the present invention, a high resistance buffer layer can be obtained with good reproducibility, so a transistor with excellent pinch-off characteristics and high frequency characteristics can be manufactured.
第１図は本発明の実施例１の選択ドープＩｎｘＧａｚ−
ｘＡｓ／ ＩｎｙＡ Ｑ ｚ−ｙＡｓ Ｆ Ｅ Ｔの縦
断面図、第２図はアンドープＩｎｙＡΩｚ−ｙＡｓ層の
電子濃度とＩｎｎ組成比上の関係を示す図、第３図は実
施例１・・・ＦｅドープＩｎＰ基板、２・・・Ｉｎｏ
、 ａｏＡ Ｑ ｏ 、 ｌ５ｏＡｓバッファ層、３・
・・Ｉｎｏ、Ｉ！ｇＧａｏ、ａｓＡｓ層、４ ＝４ｎｏ
、８ｏＡ Ｑ ｏ、ＩＩｏＡｓ層、５− Ｓ ｉドープ
Ｉｎｏ、ａｏＡ Ｑ Ｏ，５ＯＡＳ層、６・・・Ｉｎｏ
、ｓｏＡ Ｑ ｏ、ＩＩｏＡｓ層、７・・・ソース電極
、８・・・ドレイン電極、９・・・ゲート電極、１ｏ・
・・ＦｅドープＩｎＰ基板、 １１ …Ｉｎｏ、３ｏ（
Ｇａｏ、ｚｏＡ （ｌ ｏ、ｇｏ）ｏ、ａｏＡｓバッフ
ァー層、１２−８ｉドープＩｎｏ、ｎ４Ｇａｏ、４ｏＡ
ｓ層、１３ ＝４ｎｏ、ｓｏＡ Ｑ ｏ、５ｏＡｓ層
、１４−ＢｅドープＩｎｏ、３ｏＡ Ｑ ０．６ＯＡＳ
層、１５ ＝Ｉｎｏ、ａｏＡ Ｑ ｏ、ｒｓｏＡｓ層、
１６・・・ソース電極、１７・・・ドレイン電極、１８
・・・ゲート電極−FIG. 1 shows selectively doped InxGaz-
xAs/InyA Qz-yAs FET. Fig. 2 is a diagram showing the relationship between the electron concentration and Inn composition ratio of the undoped InyAΩz-yAs layer. Fig. 3 is Example 1... Fe-doped. InP substrate, 2... Ino
, aoA Q o , l5oAs buffer layer, 3.
...Ino, I! gGao, asAs layer, 4 = 4no
, 8oA Qo, IIoAs layer, 5-Si doped Ino, aoA QO, 5OAS layer, 6...Ino
, soA Q o, IIoAs layer, 7... Source electrode, 8... Drain electrode, 9... Gate electrode, 1o.
...Fe-doped InP substrate, 11...Ino, 3o (
Gao, zoA (lo, go)o, aoAs buffer layer, 12-8i doped Ino, n4Gao, 4oA
s layer, 13 = 4no, soA Q o, 5oAs layer
, 14-Be doped Ino, 3oA Q 0.6OAS
layer, 15 = Ino, aoA Q o, rsoAs layer,
16... Source electrode, 17... Drain electrode, 18
...Gate electrode-
Claims (1)
＾−＾３以下のｐ形不純物を含むＩｎ＿ｙＡｌ＿１＿−
＿ｙＡｓ（０＜ｙ＜１）バッファー層を介してエピタキ
シャル成長素子部が形成されたＩｎ＿ｘＧａ＿１＿−＿
ｘＡｓ／Ｉｎ＿ｙＡｌ＿１＿−＿ｙＡｓ（０≦ｘ≦１、
０≦ｙ≦１）系ヘテロ構造電界効果トランジスタにおい
て、上記Ｉｎ＿ｙＡｌ＿１＿−＿ｙＡｓバッファー層の
Ｉｎ組成比ｙは、０．５１以下ないし０．５５以上であ
ることを特徴とする半導体装置。 ２、上記Ｉｎ＿ｙＡｌ＿１＿−＿ｙＡｓバッファー層の
厚さは、各ｙにおける転位発生臨界膜厚以下である特許
請求の範囲第１項記載の半導体装置。 ３、半絶縁性ＩｎＰ基板上に真性又は１０＾１＾５ｃｍ
＾−＾３以下のｐ形不純物を含むＩｎ＿ｘ（ＧａＡｌ＿
１＿−＿ｙ）＿１＿−＿ｘＡｓ（０≦ｘ≦１、０≦ｙ≦
１）バッファー層を介してエピタキシャル成長素子部が
形成された Ｉｎ＿ｘ（Ｇａ＿ｙＡｌ＿１＿−＿ｙ）＿１＿−＿ｘＡ
ｓ（０＜ｘ＜１、０＜ｙ＜１）系ヘテロ構造電界効果ト
ランジスタにおいて、上記バッファー層の格子定数は５
．８６４Å以下ないし５．８８０Å以上であることを特
徴とする半導体装置。 ４、上記バッファー層の厚さはその格子定数における転
位発生臨界膜厚以下である特許請求の範囲第３項記載の
半導体装置。[Claims] 1. Intrinsic or 10^1^5 cm on semi-insulating InP substrate
In_yAl_1_- containing p-type impurities of ^-^3 or less
_yAs (0<y<1) In_xGa_1_-_ with epitaxially grown element part formed via buffer layer
xAs/In_yAl_1_-_yAs(0≦x≦1,
0≦y≦1) type heterostructure field effect transistor, wherein the In composition ratio y of the In_yAl_1_-_yAs buffer layer is from 0.51 or less to 0.55 or more. 2. The semiconductor device according to claim 1, wherein the thickness of the In_yAl_1_-_yAs buffer layer is equal to or less than the critical film thickness for dislocation generation at each y. 3. Intrinsic or 10^1^5cm on semi-insulating InP substrate
In_x (GaAl_
1_-_y)_1_-_xAs(0≦x≦1, 0≦y≦
1) In_x(Ga_yAl_1_-_y)_1_-_xA with an epitaxially grown element part formed through a buffer layer
In the s (0<x<1, 0<y<1) type heterostructure field effect transistor, the lattice constant of the buffer layer is 5.
．． A semiconductor device characterized in that the thickness is from 864 Å or less to 5.880 Å or more. 4. The semiconductor device according to claim 3, wherein the thickness of the buffer layer is less than or equal to the critical film thickness for dislocation generation based on the lattice constant of the buffer layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63244157A JP2786208B2 (en) | 1988-09-30 | 1988-09-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63244157A JP2786208B2 (en) | 1988-09-30 | 1988-09-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0294529A true JPH0294529A (en) | 1990-04-05 |
| JP2786208B2 JP2786208B2 (en) | 1998-08-13 |
Family
ID=17114612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63244157A Expired - Fee Related JP2786208B2 (en) | 1988-09-30 | 1988-09-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2786208B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142808A (en) * | 1986-12-05 | 1988-06-15 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
| JPS6466972A (en) * | 1987-09-07 | 1989-03-13 | Fujitsu Ltd | Heterojunction fet |
-
1988
- 1988-09-30 JP JP63244157A patent/JP2786208B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142808A (en) * | 1986-12-05 | 1988-06-15 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
| JPS6466972A (en) * | 1987-09-07 | 1989-03-13 | Fujitsu Ltd | Heterojunction fet |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2786208B2 (en) | 1998-08-13 |
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