JPH0293929A - Four value deciding circuit - Google Patents

Four value deciding circuit

Info

Publication number
JPH0293929A
JPH0293929A JP24794688A JP24794688A JPH0293929A JP H0293929 A JPH0293929 A JP H0293929A JP 24794688 A JP24794688 A JP 24794688A JP 24794688 A JP24794688 A JP 24794688A JP H0293929 A JPH0293929 A JP H0293929A
Authority
JP
Japan
Prior art keywords
input signal
output
signal
value
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24794688A
Other languages
Japanese (ja)
Inventor
Hirohiko Shibata
柴田 大彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24794688A priority Critical patent/JPH0293929A/en
Publication of JPH0293929A publication Critical patent/JPH0293929A/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To simplify a constitution by deciding a four values of a digital input signal based on a 1st output based upon a sine bit expressing the positive/ negative polarity of the digital input signal and a 2nd output based upon a sine bit expressing the positive/negative polarity of an added output between the absolute value of the digital input signal and a threshold signal. CONSTITUTION:A selector 6 outputs the inverse signal of an input signal based upon an inverter 8 when a selection signal utilizing the output of a selector 7 is '1', and when the selection signal is '0', selects an input signal and supplies the selected signal to an adder 9. When the selector 7 selects the sine bit of an input signal supplied to a 1st input terminal 1, the selectors 6, 7, the inverter 8 and the adder 9 form an absolute value circuit, and when input signals supplied to the 1st and 2nd input terminals 1, 2 are respectively defined as X and Y, ¦X¦ + Y is outputted to an output terminal 3. When X, Y < 0, outputs shown by the table are outputted from output terminals 4, 5 and X can be decided by the threshold of '0' and + or -Y. Thus, the constitution of the circuit can be simplified.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は4値判定回路に関し、特にデジタル信号処理に
おいて、0および絶対値が等しく極性の異なる2つの閾
値と入力信号との関係を判定する4値判定回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a four-value determination circuit, particularly in digital signal processing, which determines the relationship between an input signal and two threshold values having equal 0 and absolute values and different polarities. This invention relates to a four-value determination circuit.

〔従来の技術〕[Conventional technology]

デジタル信号処理系において、4値符号の入力信号をO
を含み絶対値が等しく極性の異る2つの閾値と比較する
4値判定回路はよく知られている。
In a digital signal processing system, input signals of four-level code are
A four-value judgment circuit that compares two threshold values having the same absolute value and different polarity is well known.

この場合入力信号を閾値と比較して判定する方法として
は2つの代表的方法があり、その1は入力信号と判定閾
値との減算結果の符号を利用する方法であり、その2は
ハードウェア比較器で両者を比較する方法である。
In this case, there are two typical methods for making a decision by comparing the input signal with a threshold.The first is a method that uses the sign of the result of subtracting the input signal and the decision threshold, and the second is a hardware comparison. This is a method of comparing the two using a device.

高速デジタル伝送装置における多値符号の判定には、処
理能力の点から後者のハードウェア比較器による方法が
多用されている。
The latter method using a hardware comparator is often used to determine multilevel codes in high-speed digital transmission equipment from the viewpoint of processing performance.

第2図は4値符号の判定に用いる従来の4値判定回路の
一例を示す構成図である。
FIG. 2 is a block diagram showing an example of a conventional four-value determination circuit used for determining four-value codes.

第2図の4値判定回路はハードウェアの比較器16.1
7とセレクタ18を備えて構成され、他にパラレルデー
タとしての入力信号を受ける信号入力端子11.正側閾
値入力端子12.負側閾値入力端子131判定出力のサ
インビット(極性ビット)を出力する出力端子15、出
力の振幅情報を出力する出力端子14を備えて構成され
る。
The four-value judgment circuit in Figure 2 is a hardware comparator 16.1.
7 and a selector 18, and also has a signal input terminal 11.7 that receives an input signal as parallel data. Positive side threshold input terminal 12. The output terminal 15 outputs the sign bit (polarity bit) of the judgment output from the negative threshold input terminal 131, and the output terminal 14 outputs the amplitude information of the output.

この場合の出力の表現は、入力信号の極性が正であるが
負であるかの“1”、“0”のサインビットと、その振
幅が正負の閾値の絶対値を越えたか否かを示す″IIZ
IIQ”の表現の組合わせで行なわれる。
In this case, the output expression is a sign bit of “1” or “0” indicating whether the polarity of the input signal is positive or negative, and whether the amplitude exceeds the absolute value of the positive or negative threshold. ″IIZ
This is done by combining the expressions "IIQ".

セレクタ18は選択信号が1のときは比較器17の出力
、選択信号がOのときは比較器16の出力を選択出力し
、これが振幅出力として出力端子14に供給される。
The selector 18 selectively outputs the output of the comparator 17 when the selection signal is 1, and the output of the comparator 16 when the selection signal is O, and this is supplied to the output terminal 14 as an amplitude output.

選択信号は出力端子15から出力される入力信号のサイ
ンビットと同じく、これは多ビツト構成のパラレルデー
タの入力信号の正負を示すMSBビットの1,0が利用
される。
Similar to the sign bit of the input signal outputted from the output terminal 15, the selection signal uses the MSB bits 1 and 0 indicating the positive/negative of the input signal of multi-bit parallel data.

比較器16.17はそれぞれ、入力信号を正の2進数と
して正側閾値および負側閾値と比較し、入力端子Aに供
給される閾値が入力端子Bに供給される入力信号値より
も小さいときは、この状態をA<Bが1であるとして出
力し、逆に入力端子Aに供給される閾値が入力端子Bに
供給される入力信号よりも大なるかもしくは等しいとき
には、この状態をA<Bが0であるとして表現し、この
1.0をそれぞれセレクタ18に供給する。
Comparators 16 and 17 each compare the input signal as a positive binary number with a positive threshold value and a negative threshold value, and when the threshold value supplied to input terminal A is smaller than the input signal value supplied to input terminal B. outputs this state as A<B is 1, and conversely, when the threshold supplied to input terminal A is greater than or equal to the input signal supplied to input terminal B, outputs this state as A<B. B is expressed as 0, and this 1.0 is supplied to the selector 18, respectively.

従って一般に、負数を2の補数表現の形式で表現した入
力信号、および閾値を信号入力端子11および正側閾値
入力端子12、負側閾値入力端子13に与える出力側子
15.14に出力される判定結果のサインビットおよび
振幅情報は第4図の判定状態図の如く示される。
Therefore, in general, an input signal representing a negative number in the form of two's complement representation and a threshold value are outputted to the output terminal 15.14 which provides the signal input terminal 11, the positive threshold input terminal 12, and the negative threshold input terminal 13. The sign bit and amplitude information of the determination result are shown as in the determination state diagram in FIG.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の4値判定回路は、2個の比較器を必要と
し、回路規模が複雑化するという欠点がある。
The conventional four-value determination circuit described above requires two comparators, which has the disadvantage of complicating the circuit scale.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の回路は、正負の等ビット数構成による閾値信号
と比較してデイタル入力信号の1値判定を行なう4値判
定回路において、デジタル入力信号の正負の極性を表現
するサインビットによる第1の出力と、デジタル入力信
号の絶対値と前記閾値信号との加算出力の正負の極性を
表現するサインビットによる第2の出力とにもとづいて
前記デジタル入力信号の4値判定を行なう手段を備えて
構成される。
The circuit of the present invention is a four-value determination circuit that performs a one-value determination of a digital input signal by comparing it with a threshold signal having an equal number of positive and negative bits. The apparatus further comprises means for performing a four-value determination of the digital input signal based on the output and a second output using a sign bit representing the positive or negative polarity of the addition output of the absolute value of the digital input signal and the threshold signal. be done.

〔実施例〕〔Example〕

次に、図面を参照して本発明の詳細な説明する。 Next, the present invention will be described in detail with reference to the drawings.

第1図は本発明の4値判定回路の一実施例の構成図で、
入力信号を受ける第1の入力端子1、閾値信号を入力す
る第2の入力端子2.4値判定結果の出力端子3.4値
判定結果のMSBビットを利用するサインビットを出力
する出力端子4、入力信号のMSBビットを出力する出
力端子5、セレクタ6.7、インバータ8、加算回路9
を備えて構成される。
FIG. 1 is a configuration diagram of an embodiment of the four-value determination circuit of the present invention.
A first input terminal 1 for receiving an input signal, a second input terminal for inputting a threshold signal, 2. An output terminal for outputting a 4-value determination result, 3. An output terminal 4 for outputting a sign bit using the MSB bit of the 4-value determination result. , an output terminal 5 that outputs the MSB bit of the input signal, a selector 6.7, an inverter 8, an adder circuit 9
It is composed of:

セレクタ6はセレクタ7の出力を利用する選択信号が1
”のときインバータ8による入力信号の反転信号を出力
し、選択信号が“0”のときは入力信号を選択して加算
器9に供給する。
The selector 6 has a selection signal that uses the output of the selector 7.
”, the inverter 8 outputs an inverted signal of the input signal, and when the selection signal is “0”, the input signal is selected and supplied to the adder 9.

セレクタ6.7、インバータ8、加算回路っけセレクタ
7が第1の入力端子1に供給された入力信号のサインビ
ットを選択しているとき絶対値回路を形成し、第1の入
力端子1に供給された入力信号をX、第2の入力端子2
に供給された入力信号をYとすると出力端子3にl X
 l +Yを出力する。
The selector 6.7, the inverter 8 and the adder circuit form an absolute value circuit when the selector 7 selects the sign bit of the input signal supplied to the first input terminal 1; The supplied input signal is connected to X, the second input terminal 2
Let the input signal supplied to output terminal 3 be Y, then l X
Output l +Y.

ここで、出力端子4,5はX、Y(<O)とすると第3
図に示す出力が得られ、Xが0、±Yの閾値で判定でき
る。なお、この実施例では入力信号がパラレルデータの
場合を例として説明したが、シリアルデータの場合もこ
れを一旦パラレルデータと変換することで容易に実施で
きることは明らかであり、さらに、入力信号の絶対値化
をとる処理を他に含むデジタル信号処理回路にあっては
、それを利用することによってその分の回路構成が省略
されて、必要とする回路構成がさらに簡素化す、ること
も明らかである。
Here, if the output terminals 4 and 5 are X, Y (<O), the third
The output shown in the figure is obtained, and determination can be made using a threshold value of 0 and ±Y for X. Although this embodiment has been explained using the case where the input signal is parallel data, it is clear that it can be easily implemented even in the case of serial data by first converting it into parallel data. It is also clear that for digital signal processing circuits that also include processing for converting values into values, by using this, the corresponding circuit configuration can be omitted and the required circuit configuration can be further simplified. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、入力信号を0及び
絶対値が等しく極性の異なる2つの閾値に対し1マシン
サイクルで判定することができ、信号の絶対値をとる処
理を他に含むデジタル信号処理装置においては回路規模
の増加をほとんど伴なわずに処理能力を上げる効果があ
る。
As explained above, according to the present invention, an input signal can be determined in one machine cycle for 0 and two thresholds having the same absolute value and different polarities, and a digital This has the effect of increasing processing capacity in a signal processing device with almost no increase in circuit scale.

り。the law of nature.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の4値判定回路の一実施例の構成図、第
2図は従来の4値符号の判定に用いられている4値判定
回路の一例を示す構成図、第3図は第1図の一実施例を
4値判定回路の4値判定内容を表現して示す判定状態図
、第4図は第3図の従来の4値判定回路の4値判定内容
を表記して示す判定状態図である。
FIG. 1 is a block diagram of an embodiment of a four-value determination circuit of the present invention, FIG. 2 is a block diagram showing an example of a four-value determination circuit used for conventional four-value code determination, and FIG. Fig. 1 is a judgment state diagram showing an embodiment of the 4-value judgment circuit expressing the 4-value judgment contents, and Fig. 4 shows the 4-value judgment contents of the conventional 4-value judgment circuit shown in Fig. 3. It is a determination state diagram.

Claims (1)

【特許請求の範囲】 正負の等ビット数構成による閾値信号と比較してデジタ
ル入力信号の4値判定を行なう4値判定回路において、 デジタル入力信号の正負の極性を表現するサインビット
による第1の出力と、デジタル入力信号の絶対値と前記
閾値信号との加算出力の正負の極性を表現するサインビ
ットによる第2の出力とにもとづいて前記デジタル入力
信号の4値判定を行なう手段を備えて成ることを特徴と
する4値判定回路。
[Claims] In a four-value judgment circuit that performs four-value judgment of a digital input signal by comparing it with a threshold signal having an equal number of positive and negative bits, It comprises means for performing a four-value determination of the digital input signal based on the output and a second output using a sign bit representing the positive or negative polarity of the addition output of the absolute value of the digital input signal and the threshold signal. A four-value determination circuit characterized by the following.
JP24794688A 1988-09-30 1988-09-30 Four value deciding circuit Pending JPH0293929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24794688A JPH0293929A (en) 1988-09-30 1988-09-30 Four value deciding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24794688A JPH0293929A (en) 1988-09-30 1988-09-30 Four value deciding circuit

Publications (1)

Publication Number Publication Date
JPH0293929A true JPH0293929A (en) 1990-04-04

Family

ID=17170900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24794688A Pending JPH0293929A (en) 1988-09-30 1988-09-30 Four value deciding circuit

Country Status (1)

Country Link
JP (1) JPH0293929A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62187929A (en) * 1986-02-13 1987-08-17 Mitsubishi Electric Corp Calculation logical arithmetic unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62187929A (en) * 1986-02-13 1987-08-17 Mitsubishi Electric Corp Calculation logical arithmetic unit

Similar Documents

Publication Publication Date Title
US5166956A (en) Data transmission system and apparatus providing multi-level differential signal transmission
CA1134026A (en) Digital video effect equipment
JPH0375900B2 (en)
JPH08339291A (en) Selection circuit of maximum value
JP3482212B2 (en) Encoding device and method for encoding (n-1) -bit information words into n-bit channel words, and decoding device and method for decoding channel words into information words
JP5506232B2 (en) Multilevel encoding method, decoding method thereof, and multilevel signal transmission apparatus
JPH0293929A (en) Four value deciding circuit
US4860235A (en) Arithmetic unit with alternate mark inversion (AMI) coding
KR100246620B1 (en) Symbol decision apparatus and method
US5293165A (en) 5B6B coding rule inverse conversion circuit for digital transmission
JP2001077870A (en) Multi-value signal transmission system
US4810995A (en) Arithmetic and logic operating unit
US5148480A (en) Decoder
JPS6232724A (en) Analog/digital converter
JPH07120958B2 (en) Tree search vector quantizer
KR100239631B1 (en) Digital multiplier
JP2638842B2 (en) Decoder circuit
JP2666349B2 (en) Peak level detection circuit
JPS62245823A (en) Linear/nonlinear code converting method
JP2538769B2 (en) Linear-nonlinear code conversion method and conversion circuit
JPS61274425A (en) Digital compressing curcuit
KR100270814B1 (en) Filtering method using shift-adder
JPH08288858A (en) Variable length code decoding device
JP3567510B2 (en) Interrupt priority judgment circuit
JPS63189023A (en) Direct current suppression multivalue code