KR100246620B1 - Symbol decision apparatus and method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Symbol Determination Apparatus and Method for Digital Quadrature Amplitude Modulation Transceiver System

2. The technical problem to be solved by the invention

It is an object of the present invention to provide a symbol determination apparatus and method for use in a digital quadrature amplitude modulation transmission / reception system or the like that can obtain a symbol value simply by using a minimum logic gate.

3. Summary of the Solution of the Invention

According to an aspect of the present invention, there is provided a display apparatus comprising: selection signal generating means for determining selection states of integer bits of waveform shaping data and outputting selection signals for selecting symbols; And symbol selecting means for selecting and outputting a predetermined symbol among the symbols according to the selection signals.

4. Important uses of the invention

The quadrature amplitude modulation symbol can be determined using the sign bit and the predetermined number of upper bits of the integer part of the waveform-formed two's complement data.

Description

Symbol Determination Apparatus and Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a symbol determination apparatus used in a transmission / reception system such as digital quadrature amplitude modulation (QAM). Particularly, the present invention relates to a symbol determination apparatus using a sign bit and a predetermined number of upper bits of an integer part. It relates to a symbol determination apparatus and method for determining the.

Conventionally, in order to determine a symbol value received in a QAM (Quadrature Amplitude Modulation) transmission system implemented in a digital manner, the waveform shaping data is corresponding to one of -3, -1, +1, and +3 four symbols. Since the input waveform shaping data has to be compared with three boundary values of -2, 0, and +2, which are boundary points among the four symbols.

For example, if the input waveform data is larger compared to the input waveform shaping data and -2, it should be compared again to zero, and if the input waveform shaping data is larger, it should be compared again to +2.

Of course, if the input waveform shaping data is less than -2 during the first comparison, no further comparison is necessary and a symbol value of -3 could be output.

However, in the case of symbol determination in a conventional digital quadrature amplitude modulation transmission / reception system, it is very rare to determine the symbol through only one comparison when comparing the waveform shaping data and the result values. As a result, many time-consuming problems still exist.

Accordingly, the present invention for solving the above problems eliminates the magnitude comparison process required to determine the symbol value of the digital quadrature amplitude modulation signal from the waveform-formed two's complement data, and signifies the waveform-formed two's complement data. And symbols are determined by using a predetermined number of upper bits of the integer part. In this case, since the upper bits of the integer part have the same number as each other, there is provided a symbol determination apparatus and method for simply obtaining a symbol value using a minimum logic gate. There is a purpose.

1 is a circuit diagram of an embodiment of a symbol determination apparatus used in a digital quadrature amplitude modulation transmission and reception system according to the present invention.

Figure 2 is a flow diagram illustrating an embodiment process of the symbol determination method used in the digital quadrature amplitude modulation transmission and reception system according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: storage unit 20: selection signal generator

30, 40: first and second symbol selector

The symbol determination apparatus of the present invention for achieving the above object comprises: a storage means for storing data in which the most significant bit, the predetermined integer bit and the plurality of decimal bits, which are code bits, are waveform-formed sequentially; Selection signal generating means for determining the arrangement state of the integer bits stored in the storage means and outputting selection signals for selecting preset symbols; First symbol selecting means for selecting and outputting a predetermined symbol among the symbols according to the selection signals output from the selection signal generating means; And second symbol selecting means for selecting and outputting one symbol among the predetermined symbols output from the first symbol selecting means using the code bit stored in the storing means as a selection signal.

In addition, in order to achieve the above object, a method for determining a predetermined symbol in the quadrature amplitude modulation transmission and reception system using waveform shaping data, the method comprising: a first step of storing waveform shaping data; A second step of determining whether the sign bit of the waveform shaping data stored in the first step is positive or negative; A third step of determining an arrangement state of integer bits of the waveform shaping data according to the second step determination result; And a fourth step of selecting and outputting one symbol among the symbols according to the determination result of the third step.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 and 2.

Referring to FIG. 1, the symbol determination apparatus used in the digital quadrature amplitude modulation transmission / reception system of the present invention stores data in which waveforms of a most significant bit (MSB), predetermined integer bits, and a plurality of decimal bits, which are code bits, are sequentially shaped. A selection signal generator 20 for outputting selection signals for selecting preset symbols by determining the storage state of the storage unit 10 and the integer bits stored in the storage unit 10; A first symbol selector 30 for selecting and outputting a predetermined symbol among the symbols according to the selection signals output from the selection signal generator 20, and the code bit stored in the storage unit 10; As a selection signal, a second symbol selector 40 for selecting and outputting one symbol among the predetermined symbols output from the first symbol selector 30 is provided.

The storage unit 10 stores waveform shaping data in the form of <24, 4, t>, where 24 indicates that the total number of bits is 24 bits, the most significant bit of the 24 bits is a sign bit, and 4 is an integer bit. 19 except the most significant bit and the integer bit which are sign bits are used as decimal bits, and t is two's complement.

The selection signal generator 20 inputs a predetermined integer bit of the storage unit 10 to output a first selection signal for selecting a symbol having a positive value among the symbols. A second selection signal generator for inputting a predetermined integer bit of the generator 21 and the storage unit 10 to output a second selection signal for selecting a symbol having a negative value among the symbols; 22).

The first selection signal generator 21 is composed of an oragate 21-1 for outputting a logic-valued logic value by logicing the integer bits of the storage unit 10 inputted through the first to third input terminals.

The second selection signal generator 22 is composed of an AND gate 22-1 for outputting a logic-ended logic value by logic-ending the integer bits of the storage unit 10 inputted through the first to third input terminals. .

The first symbol selector 30 is one of symbols (+ 1, + 3) having positive values input to the one input terminal and the type force terminal according to the first selection signal output from the first selection signal generator 21. A symbol having a negative value input to the one input terminal and the type force terminal according to the first symbol selector 31 for selecting a symbol of? And the second selection signal output from the second selection signal generator 22; A second symbol selector 32 for selecting one of the symbols.

The first symbol selector 31 has a select terminal connected to an output terminal of the oragate 21-1 of the first select signal generator 21, and positive symbols (+ 1, +) at the first and second input terminals, respectively. 3) are input, and the output terminal is composed of a first multiplexer 31-1 connected to the input terminal of the second symbol selector 40.

The second symbol selector 32 has a select terminal connected to an output terminal of the AND gate 22-1 of the second select signal generator 22, and a negative symbol (-1,-) at the first and second input terminals, respectively. 3) are inputted, and an output terminal includes a second multiplexer 32-1 connected to an input terminal of the second symbol selector 40.

In the second symbol selector 40, a sign bit, which is the most significant bit of the storage unit 10, is applied to the select terminal, and the first and second input terminals are respectively the first and second multiplexers 31-1 and 32-1. Is connected to an output terminal, and the output terminal comprises a third multiplexer 41 connected to the final output terminal.

Table 1 shows values according to a representation method of binary integers represented by 4 bits.

TABLE 1

Binary 2, repair method 1, repair method Code size method 01101110010111011110001001101010111100110111101111 01234567-8-7-6-5-4-3-2-1 01234567-7-6-5-4-3-2-1-0 01234567-0-1-2-3-4-5-6-7

In Table 1, all three methods, such as two's complement, one's complement, and code size, indicate a sign in the least significant bit (MSB). In the case of positive numbers, all three methods do not differ. In the case of a negative number, in the most easily recognized sign size method, the remaining bit values except the most significant bit represent the size of the number directly, and the negative size in the one's complement method is a value obtained by complementing the negative number. In the 2's complement method, the negative number's complement is taken and '1' is added.

The operation of the symbol determination apparatus of the present invention having the structure as described above is as follows.

When the sign bit, which is the most significant bit stored in the storage unit 10, is 0 (positive), when the integer bit of the storage unit 10 applied to the oragate 21-1 and the end gate 22-1 is 000, , OA gate 21-1 and AND gate 22-1 apply 0 to the selection terminals of the first and second multiplexers 31-1 and 32-1, respectively, with 0 as the selection signal. Subsequently, the first multiplexer 31-1 selects +1 from the positive symbols (+ 1, + 3) according to 0, which is a selection signal output from the oragate 21-1, and thus the third multiplexer 41. In addition, the second multiplexer 32-1 selects -3 among the negative symbols (-1, -3) according to 0, which is a selection signal output from the AND gate 22-1, and then the third multiplexer 32-1. To 41. Subsequently, the third multiplexer 41 of the second symbol selector 40 selects 0, which is a sign bit of the storage unit 10, as a selection signal, and then selects the first multiplexer 31-1 and 32-1 from the first and second multiplexers 31-1 and 32-1. Among the output symbols, +1, which is a symbol output from the first multiplexer 31-1, is selected and output.

When the sign bit that is the most significant bit stored in the storage unit 10 is 1 (negative), the integer bit of the storage unit 10 applied to the oragate 21-1 and the end gate 22-1 is If it is 111, the oragate 21-1 and the AND gate 22-1 apply 1 to the selection terminals of the first and second multiplexers 31-1 and 32-1, respectively. Subsequently, the first multiplexer 31-1 selects +3 from the positive symbols (+1, +3) according to 1, which is a selection signal output from the oragate 21-1, and thus the third multiplexer 41. In addition, the second multiplexer 32-1 selects -1 among the negative symbols (-1, -3) according to 1, which is a selection signal output from the AND gate 22-1, and then the third multiplexer 32-1. To 41. Subsequently, the third multiplexer 41 of the second symbol selector 40 selects 1, which is the sign bit of the storage unit 10, as a selection signal, and then selects the first multiplexer 31-1 and 32-1 from the first and second multiplexers 31-1 and 32-1. Among the output symbols, -1, which is a symbol output from the second multiplexer 32-1, is selected and output.

On the other hand, if the integer bits of the storage unit 10 applied to the oragate 21-1 and the AND gate 22-1 have a bit arrangement other than 000 and 111, the oragate 21-1 Outputs 1 as the selection signal of the first multiplexer 31-1, and the AND gate 22-1 outputs 0 as the selection signal of the second multiplexer 32-1.

The waveform shaping data stored in the storage unit 10 corresponds to four symbols of -3, -1, +1, and +3 according to three symbol boundary thresholds of -2, 0, and +2. As shown in Fig. 1, when the sign bit is 0 (positive), the waveform shaping data has a value of less than 2 only when the 4 bits of the integer part are 0000,0001. It can be seen that it has a value of two or more. Therefore, except for the least significant 1 bit of the integer part, the remaining 3 bits are mapped to +1 symbol when the value is &quot; 0 &quot; and +3 symbol otherwise. On the contrary, when the sign bit is '1' (negative), it means -1 when the 4 bits of the integer part are "1111" and -2 when "1110". However, when the integer part is "1110" and at least one of the remaining fractional bits is 1, the integer part is greater than -2 according to the two's complement property (for example, -1.xxxx) and corresponds to the -1 symbol. Therefore, when the 4 bits of the integer part are "1111" or "1110", they always have a size greater than -2, so they must correspond to -1 symbols, otherwise they must correspond to -3 symbols. Therefore, even in the case of negative numbers, except for the least significant 1 bit of the integer part, if the remaining 3 bit values are " 111 "

Therefore, the symbol determination apparatus used in the digital quadrature amplitude modulation transmission / reception system of the present invention, when the 16-square amplitude modulation symbol value is determined by the above-described method, as shown in FIG. After determining only the bits, the upper three bits of the integer portion pass through only one of the oragate 21-1 or the AND gate 22-1, so that the symbol values can be easily corresponded.

FIG. 2 illustrates a method of determining ± 1, ± 3, which are four symbols used in a 16-square amplitude modulation system, from <24,4, t> waveform shaped data (2's complement form). .

Here, the waveform shaping data corresponds to four symbols of -3, -1, +1, and +3 according to three symbol boundary thresholds of -2, 0, and +2.

Referring to FIG. 2, the waveform shaping data is stored in the storage unit 10 of the system (201), and the second symbol selector 40 determines whether the sign bit of the stored waveform shaping data is positive (0) or negative (1). Determine 202.

If the sign bit of the waveform shaping data stored in the storage unit 10 is positive, the first selection signal generator 21 determines whether the integer bit stored in the storage unit 10 is 000 (203). Is determined as 000, the first selection signal generator 21 outputs 0 as the selection signal of the first symbol selector 31, and the first symbol selector 31 then stores the positive symbols (+1, +) in advance. The +1 symbol is selected and output from 3) (204). Further, if it is determined that the integer bit is not 000, the first selection signal generator 21 outputs 1 as the selection signal of the first symbol selector 31, and then the first symbol selector 31 outputs a positive symbol ( Among the +1 and +3, +3 symbols are selected and output (205).

When the sign bit of the waveform shaping data stored in the storage unit 10 is negative, the second selection signal generator 22 determines whether the integer bit stored in the storage unit 10 is 111 (206). When the integer bit is determined to be 111, the second selection signal generator 22 outputs 1 as the selection signal of the second symbol selector 32, and the second symbol selector 32 then stores the previously stored negative symbol (-1). , -3 selects and outputs a -1 symbol from (3). In addition, when it is determined that the integer bit is not 111, the second selection signal generator 22 outputs 0 as the selection signal of the second symbol selector 32, and then the second symbol selector 32 generates a negative symbol. The -3 symbols are selected and output from the (-1, -3) (208).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the symbol determination apparatus and method used in the digital quadrature amplitude modulation transmission / reception system of the present invention are four symbol values of ± 1 and ± 3 in each in-phase and quadrature in the case of a 16-square amplitude modulation symbol. Is present, in which case it has -2, 0, +2, etc. as three symbol boundary thresholds. In other words, if the size of the waveform-shaped data is less than or equal to -2, it is a symbol value of -3; if it is greater than -2 and less than 0, it is a symbol value of -1; if it is greater than 0 and less than +2, it is +1. , If it is greater than +2, it is matched with symbol value of +3, and if using two's complement data whose integer part is 4 bits, each symbol value is easily compared only by comparing the arrangement status of one sign bit and the upper three bits of integer part. It has an effect that can be found easily.

Claims (9)

Storage means for storing waveform-shaped data in which the most significant bit, the predetermined integer bit, and the plurality of decimal bits, which are sign bits, are sequentially shaped; Selection signal generating means for outputting selection signals for judging an arrangement state of the integer bits stored in the storage means to select preset symbols; First symbol selecting means for selecting and outputting a predetermined symbol among the symbols according to the selection signals output from the selection signal generating means; And Second symbol selecting means for selecting and outputting one symbol among the predetermined symbols output from the first symbol selecting means using the code bit stored in the storage means as a selection signal; Symbol determination device having a. The method of claim 1, The selection signal generating means, A first selection signal generator for inputting a predetermined integer bit of the storage means to output a first selection signal for selecting a symbol having a positive value among the symbols; And A second selection signal generator for outputting a second selection signal for inputting a predetermined integer bit of the storage means to select a symbol having a negative value among the symbols; Symbol determination device comprising a. The method of claim 2, The first selection signal generator, An oragate for outputting the logical bits of the storage means inputted through the first to third input terminals Symbol determination device comprising a. The method of claim 2, The second selection signal generator, AND gate for outputting the AND bit of the storage means inputted through the first to third input terminal Symbol determination device comprising a. The method of claim 2, The first symbol selecting means, A first symbol selector configured to select one symbol among symbols having positive values input to one input terminal and a type force terminal according to the first selection signal output from the first selection signal generator; And A second symbol selector for selecting one of negative symbols input to one input terminal and a type force terminal according to the second selection signal output from the second selection signal generator; Symbol determination device comprising a. The method of claim 5, The first symbol selector, A multiplexer having a selection terminal connected to an output terminal of the first selection signal generator, positive symbols being respectively input to first and second input terminals, and an output terminal connected to an input terminal of the second symbol selection unit Symbol determination device comprising a. The method of claim 5, The second symbol selector, A multiplexer having a selection terminal connected to an output terminal of the second selection signal generator, negative symbols being input to first and second input terminals, respectively, and an output terminal connected to an input terminal of the second symbol selection unit Symbol determination device comprising a. The method of claim 4, wherein The second symbol selecting means, A code bit of the storage means is applied to a selection terminal, a first and second input terminals are respectively connected to output terminals of the first and second symbol selection units, and an output terminal is connected to a final output terminal of the system. Symbol determination device comprising a. In the method for determining a predetermined symbol in the quadrature amplitude modulation transmission and reception system using waveform shaping data, A first step of storing waveform shaping data; A second step of determining whether the sign bit of the waveform shaping data stored in the first step is positive or negative; A third step of determining an arrangement state of integer bits of the waveform shaping data according to the second step determination result; And A fourth step of selecting and outputting one symbol among the symbols according to the determination result of the third step Symbol determination method comprising a.

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