JPH0293583A - Display device - Google Patents

Abstract

PURPOSE:To attain both picture quality improvement and smooth display performance like a moving display by making the order in which display panels and scanning electrodes are selected different between a 1st write scan and a 2nd write scan. CONSTITUTION:A graphic controller 102 transfers scanning line address information for specifying scanning electrodes and pieces of image information PD0 - PD3 on the scanning lines specified with the address information to display driving circuits 104 and 105 of a liquid crystal display device 101. A signal for identifying the transfer of image information having the scanning address information and display information through the same transmission line is AH/DL. A signal for synchronizing the devices 101 and 102 with each other during the image information transfer is SYNC and the AH/DL signal is switched at every one horizontal scanning period to control the transfer of the information. Consequently, a decrease in picture quality due to low-frame frequency dividing is improved and the smoothness of the moving display and scrolling display is improved as well.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an information processing device, and particularly to an image information processing device suitable for a display device using a ferroelectric liquid crystal having memory properties.

[Prior art]

Conventionally, refresh scan type CRTs have been mainly used as computer terminal display devices, and vector scan type CRTs with some memory properties have been used in Daqing large-definition displays for CAD. Once a vector scan type CRT has been displayed, the next screen will not be updated until the screen is erased. Edit display (insert/delete/move/
It is not suitable for display devices for real-time man-machine interfaces such as those used in photocopying, etc. On the other hand, in the case of a refresh scan type CRT, the frame frequency is 60
The non-interlace method is used to improve the visibility of the moving display of screen white information (moving display of icons), which requires a refresh cycle of Hz or higher (
The TV uses an interlaced system for video display and to simplify the drive control system, with a 60Hz field frequency and 3
0Hz frame frequency). For this reason, the higher the display resolution, the larger the display device, requiring higher power, and the larger the drive control, resulting in higher costs.

The reason behind the appearance of flat display panels in recent years is this C.
This is caused by the inconvenience of increasing the size and power of RTs.

There are currently several types of flat display panels. For example, the high time division driving method (STN) for twisted nematic liquid crystals, and its variant, the method aiming at black and white display (
NTN) or plasma display systems use the same image data transfer method as CRT, and their screen update method also uses a non-interlaced method with a frame frequency of 60 Hz or higher, so they form one screen. A large flat display panel with a total number of scanning lines of 400 to 480 or more than 1000 has not been obtained. The reason for this is that these display panels do not have memory properties due to their driving principle, so in order to prevent flicker, a frame frequency of 60
A refresh cycle of Hz or more is required, and therefore one horizontal scanning time is as short as 10 to 50 μsec or more, making it impossible to obtain good contrast.

Ferroelectric liquid crystal display devices are capable of displaying larger screens and higher definition than the display devices mentioned above, but because of their low frame frequency drive, they are not compatible with the man-machine interface display devices mentioned above. In order to cope with this, a partial rewriting scanning method (scanning only the scanning lines within the rewriting area) that takes advantage of memory properties is required. This partial rewriting scanning method is known, for example, in U.S. Pat.
Publication No. 561, Japanese Patent Application No. 61-207326 and Japanese Patent Application No. 1983
1-212184, etc.

As a display, ferroelectric liquid crystal display devices are required to have smooth changes (switching) of image information. Generally, non-interlaced scanning is preferable in terms of smooth transitions between display screens, and for regular CRTs, the frame frequency is set high (≧70Hz) to prevent flickering and scan the entire screen in non-interlaced mode. There are many things being scanned.

However, since the ferroelectric liquid crystal display device is driven at a low frame frequency as mentioned above, it is not desirable to constantly rewrite the entire screen using non-interlaced scanning from the viewpoint of maintaining image quality (flickering occurs). do not have.

In particular, the above-mentioned partial rewrite scanning method is suitable for ferroelectric liquid crystal display devices, such as moving display of a mouse or cursor, scrolling display of multi-windows, and the like. These moving displays and scrolling displays needed to be displayed smoothly, but it was necessary to improve the image quality degradation caused by the low frame frequency drive inherent in the ferroelectric liquid crystal display device mentioned above, and at the same time improve the smoothness of the moving displays and scrolling displays. Nothing has been found that improves this.

[Summary of the invention]

An object of the present invention is to provide a display device that achieves both improved image quality and smooth display performance such as moving display and scrolling display.

The present invention provides a driving means having a scanning line driving means connected to a scanning electrode and an information line driving means connected to an information electrode, a display panel, and a driving means having an information line driving means connected to an information electrode. The display device is characterized by having means for controlling the driving means so as to vary depending on the time.

[Detailed Description of Aspects of the Invention] FIG. 1 is a block configuration diagram of a ferroelectric liquid crystal display device 101 and a graphics controller 102 provided in a main body device such as a personal computer that is a source of display information. Moreover, FIG. 2 is a communication timing chart of image information. The display panel 103 has scanning electrodes 1
120 information electrodes and 1280 information electrodes arranged in a matrix,
A ferroelectric liquid crystal is sealed in two glass plates subjected to alignment treatment, and the scanning line is connected to a scanning line drive circuit 104 and the information line is connected to an information line drive circuit 105.

The operation will be explained below with reference to the drawings. The graphics controller 102 sends scan line address information specifying scan electrodes and image information (PDO to PD3) on the scan line specified by the address information to the display drive circuit (scan line drive circuit 104 and information line) of the liquid crystal display device 101. (configured by the drive circuit 105) 104/105. In this embodiment, since image information including scanning line address information and display information is transferred through the same transmission path, it is necessary to distinguish between the two types of information. The signal for this identification is A)(/DL, and when this AH/DL signal is at Hi level, it indicates scanning line address information;
When it is O level, it indicates that it is display information.

The scanning line address information is extracted from the image information transferred as image information PDO-PD3 on the drive control circuit 111 side in the liquid crystal display device 101, and then scanned in accordance with the timing of driving the specified scanning line. Line drive circuit 1
04. This scanning line address information is input to the decoder 106 in the scanning line driving circuit 104, and the designated scanning electrode of the display panel 103 is driven by the scanning signal generating circuit 107 via the decoder 106. On the other hand, the display information is guided to the shift register 108 in the information line drive circuit 105, and shifted in units of four pixels using a transfer lock.

When the shift register 108 completes the shift for one scanning line in the horizontal direction, the display information for 1280 pixels is transferred to the attached line memory 109 and stored for a horizontal scanning period, and an information signal is generated. The signal is output from the circuit 110 to each information electrode as a display information signal.

Further, in this embodiment, the display panel 103 in the liquid crystal display device 101 is driven and the graphics controller 102 is driven.
Because the generation of scanning line address information and display information in
01/102) is necessary to synchronize. The signal that controls this synchronization is Sz-, which controls the drive control circuit 111 in the liquid crystal display device 101 every horizontal scanning period.
Occurs in The graphics controller NQ side always monitors the 5sync signal, and if the SF signal is at LO level, image information is transferred, and conversely, when it is at Hi level, the transfer of image information for one horizontal scanning line is completed. No further transfer is performed. That is, in Figure 2,
As soon as the graphics controller 102
/DL signal is set to Hi level and transfer of image information for one horizontal scanning line is started. The drive control circuit 111 in the liquid crystal display device 101 sets the SGO signal to Hi level during the image information transfer period. After the writing to the display panel 103 is completed after one predetermined horizontal scanning period, the drive control circuit (FLCD control NO roller) 111 returns the signal to the LO level again and receives the image information of the next scanning line. can be taken.

FIG. 3 shows the display screen 3 when there is a request to display a plurality of pieces of display information in the multi-window and multi-task system.

Display request 31; Mouse and font move smoothly diagonally Display request 32; A certain window is selected as the active screen and the part that overlaps with the previous window that is already being displayed is brought to the front Display request 33; Input from the keyboard Character insertion display request 34; Movement of the previous character that was already displayed (character movement in the direction of the arrow) Display request 35; Overlap area display change display request 36; Non-active window display display request 37 Scroll display of non-active window Display request 38; Full scan display Table 1 below shows the display priorities of graphic events corresponding to the display requests 31 to 38 described above.

"Partial rewriting" in the table is a driving method that scans only the scan lines in the partial rewriting area, and "multi-field refresh" is a driving method that scans only the scanning lines in the partial rewriting area.
=2. 4. 8...2N) scanning (the driving method described in Japanese Patent Application No. 62-287172). "Display priority" is a prespecified order, and in this embodiment, the emphasis is on the operability of the man-machine interface, and graphic event 31 (mouse movement display) is given the highest priority display, followed by Graphic event 33. The priority display order was set as 34, 37 and 38. Further, "drawing operation" represents an internal drawing operation of the graphics processor.

The reason why the mouse movement display has the highest display priority is because the purpose of the pointing device is to reflect the operator's intention most quickly (in real time) on the computer. The next important thing is character input from the keyboard, which is usually buffered, and although it has high real-time performance, it is lower than that of a mouse. The screen within the window as a result of this key input does not necessarily need to be updated at the same time as the key input, and the line where the key input is input has a higher priority. The relationship between scrolling in other windows and the display of the overlap area changes depending on the system settings, but this can naturally occur under multi-tasking, and here, line scrolling that goes under the active window is It is said that the

In the present invention, the screen display control program shown in FIG. 4 receives external screen display requests 31 to 38 through the communication procedure shown in the diagram, and sends them to the ferroelectric liquid crystal display (FLCD) 101 shown in FIG. It has a function to control the transfer of image information. This screen display control program requires only a small number of requests to rewrite already displayed content (if it occurs only once, the rewriting area and the VRAM (
The image information to be sent to the display device 101 can be selected and transferred while being synchronized with the display device 101 by determining the drawing process to the image information storage memory) based on the display priority order.

The communication procedure shown in FIG.
1 and an operating system (O3) 42 are used. Operating System (O3) 4
2 is rMS-nosj from Microsoft, USA.
(product name), the company's rXENIXj (product name), AT&T's rUNIXJ (product name), and Microsoft's ros/2J (product name). 'MS-Windows ver 1
゜03'' or ``ver2.OJ'' (all product names), Microsoft's ROS/2 Presenta
tion Manager J (product name), the public domain "X-WindowJ" and rDEC-WindowJ of Digital Equipment Corporation (USA).
(product name) is used. The illustrated event emulator 43 includes a set of rMS-DO3&MS-Wi
naOWS", rUNIX & X-WindowJ, etc. can be used.

The partial rewriting used in the present invention scans only the scanning lines in the partial rewriting area, and since the FLCD has memory properties, high-speed partial rewriting can be performed. Furthermore, the present invention assumes the condition that the computer system does not rewrite display information instantaneously at high speed within the entire screen. For example, information from a pointing device (such as a mouse) may be displayed at a speed of 30) 1z or less, and cannot be followed by the human eye at a speed higher than that. Similarly, the speed of smooth scrolling (scrolling for each line), which most requires high-speed display, is not noticeable if it is too fast. In fact, in practice, scrolling is not done line by line (in many cases, it is done character by character, or by a certain group of blocks).In computer systems, scrolling is often used when editing programs or documents, and its purpose is to create a smooth, sliding surface. Rather than scrolling, the display is moving from one line to another;
There is no practical problem if the rate is 10 lines/sec.

If the mouse font is composed of 32 x 32 dots and the partial rewriting scan for FLCD is driven in a non-interlaced manner, a simple calculation of this is as follows: [Equation 1: 32 lines x 100 psec/line = 3. A response speed of 2m5ec = 312Hz is possible.

On the other hand, performing line scrolling in 10 lines and 7'sec corresponds to a non-interlaced screen update rate of 10 Hz. Strictly speaking, there is no flicker at a frequency of 10Hz.
However, since the entire screen moves line by line, changes in information are more noticeable than flickers, so this is not actually a problem. Therefore, when scrolling row by row, the number of scanning lines that can be driven in non-interlaced mode is [Formula 2] (1710Hz)/100μ5ec=10
It becomes 00 (book).

The present invention is based on the scanning lines shown in FIGS. 1 and 2.
This realizes a liquid crystal display device based on a partial rewrite scanning algorithm on the graphics controller side.

Image information is generated by the graphics controller 102 on the main device side, and is transferred to the display panel 103 according to the signal transfer means shown in FIGS. 1 and 2. The graphics controller 102 includes a CPU (Central Processing Unit, hereinafter abbreviated as GCPU 112) and a VR
The AM (image information storage memory) 114 is responsible for managing and communicating image information between the host CPU 113 and the liquid crystal display device 101, and the control method of the present invention is mainly realized on this graphics controller 102. It is something that

Here, in order to take a data format of image information having scanning line address information, the scanning line address information is
It was mapped onto AM114 as shown in Figure 10. VR
The AM 114 is divided into two areas, one of which is assigned to a scanning line address information area and the other to a display information area. VR
154 pieces of image information are arranged horizontally so that the information on the AM114 corresponds to the pixels of the display panel 103 at a ratio of 1:1, and scanning line address information is placed in advance at the beginning (left end) of this one line of image data. Embedded. The GCPU 112 is
By reading information line by line from the left end of the RAM 114 and sending it to the liquid crystal display device 101, a data format in which scanning line address information is also image information is realized.

FIG. 9 is an algorithm for partial rewriting according to the present invention.

In this embodiment, when there is no partial rewriting request, the entire screen is scanned by multi-interlace scanning (full refresh drive). The image information (pointing device, pop-up menu, etc.) necessary for partial rewriting of the ferroelectric liquid crystal display device 101 is stored in advance by the GCPU.
112, and branches to a partial rewriting routine according to information from the host CPU 113. In partial rewriting, first of all, the scanning line address immediately before branching, the number of scanning lines, and the scanning method (non-interlaced scanning, multi-interlaced scanning, multi-interlaced scanning, In the case of scanning, the number of fields forming one screen, etc.) is saved in a register prepared in advance within the GCPU 112. Next, image information associated with partial rewriting is expanded to the VRAM 114, but the host CP
U113 connects to VRAM114 only via GCPU112
The GCPU 112 manages the storage start address and storage area of the image information on the VRAM 114 due to partial rewriting.

After the image information is stored in the VRAM 114, the image information starts to be transferred to the liquid crystal display device 101.
The GCPU 112 responds to image information associated with partial rewriting,
Switch the scanning method from multi-interlaced scanning to non-interlaced scanning. Switching the scanning method is the first
All you need to do is change the reading order of the image information with the scanning line address information on the VRAM 114 shown in Figure 0. VRAM11
The image information on 4 can be read out every 8 lines, and in non-interlaced scanning, it can be read out in sequence one line at a time. Transfer to the liquid crystal display device 101 is performed line by line while the GCPU 112 constantly monitors the scanning line address information mapped on the VRAM 114 in accordance with the signal transfer method shown in FIGS. 1 and 2. The scanning method is not changed during the image information transfer period associated with one partial rewrite.

In addition, in consideration of the case where another partial rewriting request occurs during one partial rewriting process, for each line transfer, a second partial rewriting request with a higher display priority than the partial rewriting image information currently being processed is
Checks whether there is a partial rewrite request. If a second partial rewrite request has occurred at that time, the first
The data transfer of the partial rewrite information is interrupted and the process branches to the second partial rewrite routine. In the second partial rewriting routine, first, information on the scanning method at the time of the first partial rewriting is stored, and the scanning method is changed according to the image information associated with the partial rewriting. Thereafter, the same processing as in the first partial rewriting routine is performed to restore the scanning method and the like at the time of the first partial rewriting, and the process returns to the first partial rewriting routine. In the first partial rewriting routine, the transfer of the remaining image information is continued while checking whether a higher-level partial rewriting request has occurred for each line, and after all image data has been transferred, the scanning line that has been saved in advance is Based on address, number of scan lines, and scan method, return to normal full screen refresh routine.

Table 2 below shows the scanning electrode numbers (scanning electrodes from the top of the screen to the bottom) with codes (1', 2°, 3°, etc.) sequentially from the top.
(N') represents the relationship between the scanning method and the order in which scanning electrodes are selected.

FIG. 11 shows a multi-window display screen 11 according to the present invention.
This is an example of 0. Window 1 is a screen that expresses certain aggregated results as a pie chart. Window 2 is a screen that displays the tabulated results of Window 1. window 3 is window l
A screen that shows the aggregated results in a bar graph. Window 4 is the screen where a document is being created. and 5 is a pointing device mouse. Assume now that the windows 1 to 3 are in a stationary state, and the mouse 5 is moved while scrolling in the window 4 in conjunction with document editing work. A change in image information within a certain window or movement of the mouse is image information that requires partial rewriting scanning for the ferroelectric liquid crystal display device 101. By the way, -horizontal scanning time = 8
When scanning 1120 lines on the entire screen in 0μsec, the frame frequency is about 1OHz, which is equivalent to one normal mouse movement (≧
30Hz) cannot be followed at all.

Here, by applying the partial rewriting algorithm according to the present invention, the scrolling operation of the window 4 and the movement of the mouse 5 will be made to correspond to the first and second partial rewriting routines, respectively. In the first partial rewriting routine, first, the scanning method for the display panel is changed from multi-interlaced scanning in the full screen refresh routine to non-interlaced scanning, and window 4 is partially rewritten. This is because the display operation of scrolling within a window is one of the fastest display switching operations for the ferroelectric liquid crystal display device 101, and at the same time, it is necessary that the display contents (characters) can be identified even during scrolling. However, if the content being rewritten in Window 4 does not require particular recognition of the rewriting process, such as when turning a page, there is no need to change the scanning method; in fact, multi-interlace scanning provides better image quality. becomes stable. Branching to the second partial rewriting routine occurs when the mouse 5 is moved, and the time required for this branching is within one horizontal scanning time at the longest. As with the scrolling of the window 4, it is particularly important to be able to trace the movement process of the mouse 5, so the scanning method for partial rewriting here is also non-interlaced scanning. Assuming that the mouse font size is 32 x 32 dots and the horizontal scanning time is 80 μs, the time required to write with the mouse on the display panel is 32 x 82 μs = 2.56 m5, and during this time the scrolling operation of window 4 due to the first partial rewriting is performed. Although it is stopped, it is a sufficiently short period of time and has little effect on scrolling speed. After writing with the mouse 5, the process returns to the partial rewriting scan of the window 4, but if the mouse moves again, it immediately branches to the mouse partial rewriting routine and performs a mouse writing operation using non-interlaced scanning. Thus, the first and second partial rewriting processes are completed, and the process returns to the full screen refresh routine.

Normally, windows and mice are also refreshed using multi-interlace scanning unless their display contents change or move. However, by performing partial rewriting and switching the scanning method for predetermined display operations in this way, even in the low frame frequency drive unique to ferroelectric liquid crystal display devices,
Not only can the movement speed of the mouse, etc. be ensured, but also the display quality can be maintained during movement.

In a preferred embodiment of the present invention, in the case of image information that changes slowly due to partial rewriting, multi-interlace scanning, movement of a pointing device, or scrolling within a window is used to maintain image quality. In the case of image information that changes quickly and places emphasis on its movement process, there should be a means for switching the scanning method according to image information associated with partial rewriting, such as non-interlaced scanning that places emphasis on display response. Through this, we have realized an algorithm optimized for various display applications that require partial rewrite scanning for ferroelectric liquid crystal display devices, and can run advanced display application software such as multi-window and multi-tasking without failure. , which enables smooth display.

FIG. 5 is a block diagram of the graphics controller 102, FIG. 6 is a block diagram of the digital interface, and FIGS. 7 and 8 are timing charts of information transfer.

The major difference between the graphics controller 102 used in the present invention and the conventional one is that the graphics processor 501 has its own system memory 502 and is capable of not only managing RAM 503 and ROM 504, but also managing RAM 503 and ROM 504.
In addition to executing and managing drawing commands to the RAM 503, it is possible to independently program information transfer from the digital interface 505 to the FLCD controller, management of the FLCD driving method, etc.

First, the digital interface 505 in FIG.
77 which is an external synchronization signal from the CD controller 111
While synchronizing with the drive circuits 104 and 105 of the display panel 103 by m, the information in the VRAM is sent at 4 bits/clock (clock = data transfer lock) at the final stage.

FIG. 7 shows the timing when the FLCD rewrites the entire screen, and the parameters in the diagram are the same as the timing chart at the time of information transfer in FIG. First, the transfer of image information for one line starts after W and F in FIG. 8 become active (low level in this case). m de lo
It is the FLCD controller 111 that sets panel 1 to w.
Represents an information request from the 03 side. This information request from the panel 103 side is received by the graphics processor 501 shown in FIG. 5, and is internally processed at the timing shown in FIG. In the timing chart of FIG. 8, H3YNC of the information request from the panel 103 side is equivalent to one period of the external video clock (CLKOUT) from the outside (from another perspective,
VCLK (7) low period). In this case, this V
CLK is actually input and this processor 50 is designed to sample during the 1-month OW period), and after 2.5 clocks of VCLK, the horizontal counter HCOUNT inside the processor 501 is cleared, and the parameters shown in FIG. 7) IESYNC, HEBLNK Figure 7 immediately before HCOUNT=1 by programming.

8 becomes disabled (high), and in the circuit of FIG. 6, DATEN becomes active (high) after half a clock of VCLK as shown in FIG. After 4.5 clocks from the sampling point, the next line of data is VRA.
Every 4 bits are transferred from M to the FLCD controller 111.

Now, in the line information to be transferred in this case, as shown in the lower right corner of FIG. One line of display information is sent. In this case, the FLCD controller 111 uses the AH/DL signal to identify the scanning line address information and display information.
When the /DL signal is high, it indicates scanning line address information, and when it is low, it recognizes display information. Therefore, FLC
In D, scanning lines are selected according to this scanning line address information and display information is written, so when the scanning line address information from the graphic controller in FIG. When increasing the number every m, the FLCD is driven to interlace, and when increasing every m, the FLCD is driven to multi-interlace. Therefore, it is possible to control the display driving method.

The driving time for one scanning line of FLCD is usually 100 μsec.
Around c is required. Assuming that the driving time for one scanning line is 100 μsec and the lowest frequency at which flicker does not occur is 30 Hz, in the non-interlaced drive method of this FLCD, [Formula 3] (1/30 Hz)/100 μsec”q
333 (book) In the interlaced drive system, [Formula 4 (1/30Hz) x 2/100 use
c! =t666 (numbers) m multi-interlace [Formula 5] (1/30Hz)Xm/100μsec''
Even when scanning (scanning/driving) the scanning lines of the i333Xm (book), no flicker occurs as a still image. According to experiments conducted by the present inventor, it was confirmed that no flicker occurs even when m=32. That is, [Formula 6] (1/30Hz) x 32/100μs
The display panel 103, which has 333 x 32 = 10,656 (lines) scanning lines, can be displayed without flickering, and it is numerically possible to achieve high definition, which is unprecedented for a flat display panel. That's why.

In addition, r74As161AJ, r74AS74 in Fig. 6
J, r74ALS257J, r74ALs878J, and r74As257J each represent an IC number, and the numbers in the figure each represent a pin number.

Figure 12 shows the multi-interlace drive method (a method in which scanning electrodes are selected at intervals of every second or more) used in the present invention.
This is an example of a drive waveform.

Figure 12 shows (4M-3) field F 4M-3, (
4M=2) field F4M-2, (4M-1) field F 4M-1 and 4M field F4M (where l
A field is one vertical scanning period. M=1.
Scan selection signal 54n-3 (n=1.2.3-) applied to the 4n-3rd scan electrode at 2°3...)
), 4n-scan selection signal 5 applied to the second scan electrode
A scan selection signal 54n-1 applied to the 4n-2 and 4n-1th scan electrodes and a scan selection signal S4n applied to the 4nth scan electrode are shown. According to FIG. 12, the scan selection signal 54n-3 corresponds to (4M-3) field F 4
M-3 and (4M-1) field F4M-1 (M=1.
2.3...) in the same phase (voltage polarity based on the voltage of the scan non-selection signal) are opposite to each other, and (4M2) field F 4M-2 and 4M field F4M It is configured not to scan, and the same applies to the scan selection signal 84n-1. Furthermore, the scan selection signal S 4n-3 applied within the l field period
and 84n-1 have different voltage waveforms, and the voltage polarities of the same phase are opposite to each other.

Similarly, the scan selection signal 54n-2 has voltage polarities (voltage polarities based on the voltage of the scan non-selection signal) in the same phase of the (4M-2) field F4M-2 and the 4M field F4M that are opposite to each other. Ori, cutlet (4M-3)
Field F 4M-3 and (4M-1) Field F4
In M-1, scanning is not performed, and the same applies to the scanning selection signal S4n. Furthermore, the scan selection signals 54n-2 and 84n applied within one field period have different voltage waveforms, and the voltage polarities of the same phase are opposite to each other.

In addition, in the scan drive waveform example shown in FIG. 12, the third phase is provided for stopping the screen all at once (for example, applying a voltage of 0 to all pixels constituting the screen at once), and the scan selection signal is The third phase is set to voltage 0 (same level as the voltage of the scan non-selection signal).

Also, according to FIG. 12, the information signal applied to the signal electrode in the (4M-3)th field F 4M-3 is as follows:
A white signal (by combination with the scan selection signal 34M-3, a voltage 3v0 exceeding the threshold voltage of the ferroelectric liquid crystal in the second phase is applied to the scan selection signal 54n-3 to form a white pixel. ) and a hold signal (by combining with the scan selection signal 54n-3, a voltage ±v0 smaller than the threshold voltage of the ferroelectric liquid crystal is applied to the pixel) are selectively applied, and the scan selection signal 54n-+ is a black signal (by combination with the scanning selection signal 54n-1, a voltage -3Vo exceeding the threshold voltage of the ferroelectric liquid crystal is applied in the second phase to form a black pixel) and a holding signal. (By combining with the scan selection signal 54n-+, a voltage ±v smaller than that of the ferroelectric liquid crystal is applied to the pixel.
o is applied) are selectively applied. and,(
Since the scan non-selection signal is applied to the 4n-2)th and (4n)th scan electrodes, the information signal is applied as is.

Following the writing of the above-mentioned (4M-3) field F 4M-3, the information signal applied to the signal electrode in (4M-2) field F 4M-2 is the scanning selection signal 54n-2.
For the scanning selection signal S4n, the same black signal and holding signal as described above are selectively applied, and for the scanning selection signal S4n, the same white signal and holding signal as described above are selectively applied. Since the scan non-selection signal is applied to the (4n-3)th and (4n-1)th scan electrodes, the information signal is applied as is.

Also, (4M-2) Field F Following 4M-2 ((4M
-1) In field F 4M-1, as information signals applied to the signal electrodes, a black signal and a holding signal similar to those described above are selectively applied to scanning selection signal S 4n-3, and scanning The same white signal and hold signal as described above are selectively applied to the selection signal 54n-+. And (4
Since the scan non-selection signal is applied to the n-2)th and 4nth scan electrodes, the information signal is applied as is.

(4M-1) Continuing from field F4M-1 (as the information signal applied to the signal electrode in 4M field F4M, the black signal and hold signal similar to those described above are selectively applied to the scanning selection signal 54n-2). The same white signal and holding signal as described above are selectively applied to the scan selection signal S4n.Then, the (4n-3)th and (4n-1)th
Since the scan non-selection signal is applied to the th scan electrode,
The information signal is applied as is.

13(A), (B), and (C) show timing charts when the display state shown in FIG. 13(D) is written using the drive waveform shown in FIG. 12. Figure 13 (D
), ○ represents a white pixel and . represents a black pixel. Further, I1-31 in FIG. 13(B) is a time-series waveform of the voltage applied to the intersection of the scanning electrode S1 and the signal electrode I. I2-31 is a time-series waveform of the voltage applied to the intersection of scanning electrode S1 and signal electrode 2. Similarly 11-3
2 is a time series waveform of the voltage applied to the intersection of the scanning electrode S2 and the signal electrode 11. 2-82 is a time series waveform of the voltage applied to the intersection of the scanning electrode S2 and the signal electrode I2.

Furthermore, the present invention is not limited to the above-mentioned drive waveform examples (for example, every four scanning lines, every fifth scanning line, every sixth scanning line,
It is possible to scan every 7 lines, preferably every 8 lines or more. Further, the scanning selection signal may have a waveform whose polarity is inverted for each field as shown in FIG. 12, or may have the same waveform for each field.

FIG. 14 schematically depicts an example of a ferroelectric liquid crystal cell. 141a and 141b are In2O3°SnO
It is a substrate (glass plate) coated with transparent electrodes such as □ or ITO (indium tin oxide), and a SmC main phase liquid crystal with liquid crystal molecular layers 142 oriented perpendicular to the glass surface is sealed between them. ing. A thick line 143 represents a liquid crystal molecule, and this liquid crystal molecule 143
has a dipole moment (P) 144 in the direction perpendicular to its molecule. When a voltage higher than a certain threshold is applied between the electrodes on the substrates 141a and 141b, the liquid crystal molecules 1
The helical structure of 43 unravels and the dipole moment (P soil)
The alignment direction of the liquid crystal molecules 143 can be changed so that all of the liquid crystal molecules 144 are oriented in the direction of the electric field. The liquid crystal molecules 143 have an elongated shape and exhibit refractive index anisotropy in the major and minor axis directions. Therefore, for example, if polarizers are placed above and below the glass surface in a crossed nicol positional relationship, It is easily understood that the liquid crystal optical modulation element is a liquid crystal optical modulation element whose optical characteristics change depending on the polarity of applied voltage. Furthermore, when the thickness of the liquid crystal cell is made sufficiently thin (for example, 1μ), the helical structure of the liquid crystal molecules is unraveled even when no electric field is applied, as shown in Figure 15, and its dipole moment Pa or pb
is either upward (154a) or downward (154b). When an electric field Ea or Eb of different polarity above a certain threshold value is applied to such a cell for a predetermined time as shown in FIG.
upward 154a or downward 1 with respect to the electric field vector of b
54b, and accordingly, the liquid crystal molecules are aligned in either the first stable state 153a or the second stable state 153b.

There are two advantages to using such a ferroelectric liquid crystal as an optical modulation element. Firstly, the response speed is extremely fast, and secondly, the alignment of liquid crystal molecules has a bistable state. To explain the second point with reference to FIG. 15, for example, when the electric field Ea is applied, the liquid crystal molecules enter the first stable state 153a.
This state is stable even when the electric field is turned off.

Furthermore, when an electric field Eb in the opposite direction is applied, the liquid crystal molecules are oriented to a second stable state 153b and change their orientation, but they remain in this state even after the electric field is turned off. Further, as long as the applied electric field Ea does not exceed a certain threshold value, each orientation state is maintained. In order to effectively realize such fast response speed and bistability, it is preferable for the cell to be as thin as possible, and generally from 0.5μ to
20μ, especially 1μ to 5μ is suitable.

〔Effect of the invention〕

As explained above, in the scanning method of a ferroelectric liquid crystal display device that involves partial rewriting scanning, for example, multi-interlace scanning is used during full-screen scanning, and non-interlace scanning is used during partial rewriting scanning depending on the image information. By providing a means to switch the scanning method between scanning and partial rewriting scanning, the rewriting speed is comparable to that of conventional display devices (CRTs) even in low frame frequency driving inherent to ferroelectric liquid crystal display devices. This enables smooth display switching, making it possible to display advanced display applications and software, such as multi-window and multi-tasking, smoothly on a ferroelectric liquid crystal display panel without disruption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a liquid crystal display device and a graphics controller, and FIG. 2 is a timing chart for communicating image information between the liquid crystal display device and the graphics controller. FIG. 3 is a display screen diagram schematically showing a plurality of graphic events. Figure 4 shows
FIG. 2 is a block diagram of a display control program used in the present invention. FIG. 5 is a block diagram of the graphics controller used in the present invention, and FIG. 6 is a block diagram of the digital interface. FIG. 7 is an interface timing chart for the display driving device used in the present invention, and FIG. 8 is an interface timing chart for the FLCD controller. FIG. 9 is a sequence diagram showing an algorithm for partial rewriting used in the present invention. FIG. 10 shows the V used in the present invention.
FIG. 3 is an explanatory diagram showing data mapping of scanning line address information and display information on a RAM; FIG. 11 is a diagram of the multi-window display screen in this embodiment. Figure 12 (A)
and (B) are drive waveform diagrams used in the present invention, and Figures 13 (A) to (C) are timing chart diagrams thereof.
Figure (D) is a schematic diagram showing the display state of the pixels at that time. 14 and 15 are perspective views of the ferroelectric liquid crystal cell used in the present invention. Figure 12 CB) II ■? /43 /43

Claims (5)

[Claims] (1) The order of selection of the drive means, display panel, and scan electrode having a scan line drive means connected to the scan electrode and an information line drive means connected to the information electrode is during the first write scan and during the second write scan. means for controlling the driving means to be different from each other. (2) The display device according to claim 1, wherein the first write scan is a full screen scan, and the second write scan is a partial rewrite scan that scans only scan electrodes in a partial rewrite area. (3) The order in which scan electrodes are selected during the first write scan is determined by interlaced selection of every two or more scan electrodes, and the order in which scan electrodes are selected during the second write scan is determined by interlaced selection of every two or more scan electrodes. 2. The display device according to claim 1, wherein the order is determined by sequentially selecting the scanning electrodes one by one. (4) The display device according to claim 1, wherein the display panel is a display panel having memory properties. (5) The display device according to claim 4, wherein the display panel having memory properties is a ferroelectric liquid crystal panel.