JPH0291962A - Design changing method for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To change the result of layout automatically with respect to design change by determining the arranging positions of additional cells at the minimum rectangle region which is constituted with the group of terminals in connecting relation with said cells. CONSTITUTION:The positions of terminals 21, 22 and 23 which are connected to signals in connecting relation with cells are obtained for every additional cell. Then the coordinates of the terminal points of a rectangle which is formed with the connecting terminals are obtained for every obtained signal, and corresponding sections 41-43 are obtained. When said operations are all finished for all the signals, sectors which include the terminal points of all the obtained signal at the at least one side are obtained on the X axis or the Y axis. The sector on the X axis obtained in this process is expanded on the Y axis, and a two-dimensional region is set. The length in the direction of the Y axis is made to be the longest section 51 which is held between the minimum value and the maximum value among the lower end point and the upper end point of the circumscribing rectangle of the connecting terminals for every signal. Whether the additional cell can be arranged or not within said region without moving the already arranged cell or not is judged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to changes in layout design accompanying system changes that occur after completion of layout design of a semiconductor integrated circuit.

(Conventional Technique WI) Automatic placement and wiring systems are often used for layout design of semiconductor integrated circuits. Circuits used for layout design have undergone logical operation verification and timing verification using expected wiring lengths, and layout design is required to not deviate significantly from the values obtained here.

On the other hand, for the circuit whose layout design has been completed, verification is performed to check whether there are any violations of design standards or whether the above-mentioned electrical characteristics satisfy predicted values. These design verification tasks generally require a large amount of computer resources.

If a problem is discovered during the design verification work described above, it may be necessary to partially change the layout result or re-layout. Further, there are cases where instructions are given to change the layout result by adding or deleting circuit elements by changing the circuit itself to be laid out. In actual product design, layout design is often not started after system design but is proceeded in parallel, and such design changes after layout design may occur frequently. In such a situation, it is important to minimize the influence on the verification results of the layout results and to efficiently reflect the design changes on the system side in the layout changes.

Conventionally, when making the above-mentioned design changes, either the interactive corrections or changes were made using graphics and editors, or the layout was redone.

In the case of the former method, a large amount of time is required due to manual correction, and there is a risk that errors may be introduced. On the other hand, in the latter case, there is a problem in that the verification results obtained by spending a lot of computer resources are wasted. When changing the layout results in response to such system changes, it is necessary to minimize the impact on the verification results before making the changes, prevent errors from being introduced, and save man-hours. Therefore, it is necessary for K to automate these tasks. (Problem to be solved by the invention) As mentioned above, conventionally, when making design changes, it is necessary to make interactive corrections and changes using graphics and editors, or to re-layout. However, in the former case, manual corrections required a large amount of time and there was a risk of errors being introduced.

On the other hand, in the latter case, there is a problem that the verification results obtained by spending a lot of computer resources will be wasted. The purpose is to provide a means to automatically change the layout results.

The present invention relates to layout changes for desired circuit changes to circuits for which layout design has been completed, in particular cell addition, and a method for calculating and adding an optimal cell insertion position and processing partial re-layout for cell addition. give.

That is, in the present invention, a minimum rectangular area consisting of a group of terminals having a connection relationship with the cell is set as an area for adding a cell. If a cell can be added without moving the already placed cells, the cell is added within the area. Although cells cannot be added without moving the already placed cells in the area, if the area is large enough to accommodate the cells, a partial re-layout of the area is performed.

In this case, first, a virtual terminal is set at the boundary condition of the area, that is, at the boundary of the rectangular area, and then all cells in the area are made unplaced, and partial relayout is executed including additional cells. If the cell cannot be accommodated in the area, the size of the rectangular area is enlarged and the same process as above is repeated.

(Operation) According to the present invention, since the placement position of a cell to be added is set to the minimum rectangular area consisting of a group of terminals connected to the cell, the layout change area can be kept to a minimum, and the layout change area can be kept to a minimum. The length of the wiring related to the cell can also be made sufficiently short. Also, if the cell cannot be placed within the area set by this means, the area will be enlarged.
In either case, the area is within a rectangular area made up of a group of terminals connected to the relevant cell, or at worst around the rectangular area.

All of the above layout change processing is executed automatically, so Vcv! Since there is no contamination by A, and changes in the layout results are kept to a minimum, the influence on the verification results obtained by spending a lot of calculation time can be minimized.

(Example) Hereinafter, specific examples of the present invention will be described with reference to FIGS. 1, 2, and 3.

FIG. 1 is a flowchart showing the design change processing procedure.

First, for each cell to be added, the position of the terminal connected to the signal connected to the cell is determined. In Figure 2, 21,
22 and 23 are the corresponding terminals.

Next, for each signal obtained, the coordinates of the end points of the rectangle made up of the terminals to be connected are determined, and the corresponding section as shown at 41.42° 43 in FIG. 2 is determined. When the above operations are completed for all the signals, find a section on the X-axis or Y-axis that includes at least one end point of all the signals found above. In the following, we will consider the X coordinate of the end point.

First, starting from the one with the smallest endpoint of the Xl51 mark, a section including at least one endpoint of all the signals is found as described above. In Figure 2, 31 is X1
This section includes the smallest endpoints of the 11 markers and includes at least one endpoint of all signals. The section on the X-axis obtained by the above processing is expanded onto the Y-axis to set a two-dimensional area. The length in the Y-axis direction is the longest section sandwiched between the minimum value ° and the maximum value among the lower end point and the upper end point of the circumscribed rectangle of the terminal connected for each signal obtained in the above processing. In FIG. 2, 51 is the longest section on the Y axis determined for each signal.

Next, it is determined whether additional cells can be placed within this area without moving the already placed cells.

If an additional cell can be placed without moving the already placed cell, the cell is placed there, then wiring processing is performed, and the process is completed. It is not possible to place additional cells without moving the already placed cells, but if there is enough space to insert the additional cells, set the boundary conditions for the area and move all the already placed cells. Re-layout is performed within the area in an unplaced state. At this time, the boundary conditions of the region are determined by setting virtual terminals corresponding to all signals that cross the region boundary. Under the boundary conditions obtained in this manner, re-layout is executed within the area including the additional cells. Figure 3 shows this situation. Third
In the figure, 71 is a virtual terminal on the rectangular area boundary, 72 is a terminal connected to an additional cell, and 81 is a re-layout target area including boundary conditions.

If it is not possible to arrange additional cells due to space constraints, the relayout target area is enlarged and the same process as above is repeatedly executed. To enlarge the re-layout target area, if the section on the X-axis constituting the current rectangle is section 31 in FIG. 2, the next section is section 32 including the right end point of section 43 in FIG. The next section is section 33 that includes the right end point of section 42), and so on.

In the above example, the unit section for setting the rectangular area is the section sandwiched between the end points of the terminals connected for each signal, and the positions of the terminals included in these sections are not considered, but the detailed processing In this case, the position information of each terminal may be used instead of the section for each signal.

〔Effect of the invention〕

As described above, according to the present invention, in response to a design change that occurs after the completion of layout design, it is possible to suffice by simply adding cells due to the design change without changing the already designed part, or by changing the already designed part. It is possible to change the layout design with minimal impact. This means that the designed layout result information can be utilized to the fullest, and the effort required to re-verify the layout results can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing a design change processing procedure according to an embodiment of the invention, FIG. 2 is a diagram for explaining a method of setting a rectangular area and a method of enlarging the area according to an embodiment of the invention, and FIG. The figure shows a method for setting a re-layout target area. 11... Semiconductor substrate, 21.22.23... Terminals of already placed cells that have a connection relationship with additional cells, 31.32, 33.34... Section on the X-axis forming a rectangular area, 41142 .43...A section bounded by the end points on the X-axis for each signal, 1...Maximum section 1 of the end points on the Y-axis determined for each signal 1...Rectangular area, l... Terminals connected to additional cells, 2... Virtual terminals for signals crossing on rectangular area boundary sides, 1... Re-layout target area IX.

Claims (2)

[Claims] (1) When manufacturing a semiconductor integrated circuit device that realizes a desired circuit by arranging multiple logic cells on a semiconductor substrate and wiring between each logic cell, design changes may be made to the already designed layout result. When adding a corresponding cell, find a set of laid out cell terminals that have a connection relationship with the added cell, and from this set, excluding terminals for special signals, include at least one terminal for each signal. 1. A method for changing the design of a semiconductor integrated circuit device, the method comprising: configuring a minimum rectangular area, and arranging additional cells within the area. (2) Although it is not possible to place additional cells without moving the already placed cells, if you can secure space to accommodate the additional cells by moving the already placed cells, all the already placed cells can be moved. 2. The method for changing the design of a semiconductor integrated circuit device according to claim 1, wherein the layout is carried out including unplaced cells and additional cells.