JPH0291366U - - Google Patents
Info
- Publication number
- JPH0291366U JPH0291366U JP19489U JP19489U JPH0291366U JP H0291366 U JPH0291366 U JP H0291366U JP 19489 U JP19489 U JP 19489U JP 19489 U JP19489 U JP 19489U JP H0291366 U JPH0291366 U JP H0291366U
- Authority
- JP
- Japan
- Prior art keywords
- component
- conductive foil
- conductive
- land
- probe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011888 foil Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000523 sample Substances 0.000 claims 3
- 239000011810 insulating material Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000007664 blowing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19489U JPH0291366U (US06878557-20050412-C00065.png) | 1989-01-05 | 1989-01-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19489U JPH0291366U (US06878557-20050412-C00065.png) | 1989-01-05 | 1989-01-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0291366U true JPH0291366U (US06878557-20050412-C00065.png) | 1990-07-19 |
Family
ID=31199004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19489U Pending JPH0291366U (US06878557-20050412-C00065.png) | 1989-01-05 | 1989-01-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0291366U (US06878557-20050412-C00065.png) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012038925A (ja) * | 2010-08-06 | 2012-02-23 | Jtekt Corp | 素子実装基板の組み立て方法 |
-
1989
- 1989-01-05 JP JP19489U patent/JPH0291366U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012038925A (ja) * | 2010-08-06 | 2012-02-23 | Jtekt Corp | 素子実装基板の組み立て方法 |
