JPH029129A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH029129A
JPH029129A JP16010188A JP16010188A JPH029129A JP H029129 A JPH029129 A JP H029129A JP 16010188 A JP16010188 A JP 16010188A JP 16010188 A JP16010188 A JP 16010188A JP H029129 A JPH029129 A JP H029129A
Authority
JP
Japan
Prior art keywords
film
sinx
tft
electron spin
spin density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16010188A
Other languages
Japanese (ja)
Other versions
JPH0727900B2 (en
Inventor
Hiroyoshi Takezawa
浩義 竹澤
Toru Koshimizu
輿水 透
Sadakichi Hotta
定吉 堀田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63160101A priority Critical patent/JPH0727900B2/en
Publication of JPH029129A publication Critical patent/JPH029129A/en
Publication of JPH0727900B2 publication Critical patent/JPH0727900B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To obtain an a-Si TFT stable for a long period of time of 600 times as long as a conventional one by employing an SiNX film having specific value of electron spin density of the SiNX film. CONSTITUTION:A conductor is selectively formed as a gate electrode 2 on a glass board 1. An SiNX is deposited as a gate insulating film 3, and a-Si films are continuously deposited as a semiconductor film 4 by the same plasma chemical vapor depositing method as that of the SiNX film. The a-Si film is selectively removed, and an insular a-Si film pattern 4 is formed. The pattern 4 and an N<+> type a-Si film 5 containing phosphorus as an impurity selectively remain between a source electrode 6 and a drain electrode 7 selectively covered and made of conductors to form an a-Si TFT. The electron spin density of the SiNX is small value of 2.4X10<17>cm<-3> or less. Thus, a stable a-Si TFT endurable for a long period of time of 600 times a conventional one is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、パッシベーション膜や層間絶縁膜等に用いら
れるシリコン窒化膜を有する半導体装置に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a silicon nitride film used as a passivation film, an interlayer insulating film, or the like.

従来の技術 プラズマ化学気相堆積法(以後、プラズマCVD法と呼
ぶ)でシリコン窒化膜(以後、StN工膜と呼ぶ)と非
晶質シリコン膜(以後、a−8t膜と呼ぶ)が各々、ゲ
ート絶縁膜及び半導体膜として連続的に形成された薄膜
電界効果トランジスタ(以後、a−5iTFTと呼ぶ)
は優れたオン抵抗、オフ抵抗を有することから、液晶画
像表示装置のスイッチング素子として実用化されている
Conventional technology: A silicon nitride film (hereinafter referred to as StN film) and an amorphous silicon film (hereinafter referred to as A-8T film) are formed using plasma chemical vapor deposition method (hereinafter referred to as plasma CVD method), respectively. Thin film field effect transistor (hereinafter referred to as a-5iTFT) formed continuously as a gate insulating film and a semiconductor film
Because it has excellent on-resistance and off-resistance, it has been put into practical use as a switching element for liquid crystal image display devices.

発明が解決しようとする課題 しかし、それらの作製方法や作製条件により、特性劣化
に大きな差があり、劣悪なものでは、100分程程度寿
命しかないものがあった(参考文献日経エレクトロニク
ス 1982.12.20P146〜14了「特集アモ
ーファスシリコン」)。
Problems to be Solved by the Invention However, there are large differences in characteristic deterioration depending on the manufacturing method and manufacturing conditions, and some inferior products have a lifespan of only about 100 minutes (Reference Nikkei Electronics 1982.12) .20P146-14 ``Special feature on amorphous silicon'').

そこで本発明は、SiNx膜の膜質を改善し、優れた信
頼性を有するa−8iTFTを提供することを目的とす
るものである。
Therefore, an object of the present invention is to improve the film quality of the SiNx film and provide an a-8i TFT with excellent reliability.

課題を解決するだめの手段 上記目的を達成する為、本発明は、プラズマCVD法で
作製されるSiNx膜の電子スピン密度が2,4X10
  (m  以下の小さな値を有するSiN工膜を用い
るものである。
Means for Solving the Problems In order to achieve the above objects, the present invention provides an SiNx film manufactured by plasma CVD with an electron spin density of 2.4×10
(It uses a SiN film having a small value of m or less.

作  用 本発明は、SiNx膜の膜質の改善により、従来の60
0倍以上の長時間にわたシ安定なa−8iTPTを提供
するものである。更に、本発明によるSiNx膜は、特
に界面付近の膜質がすぐれており、トラップ準位が少な
いことに起因して、優れた特性のa−3iTFTが提供
出来る。従って、本発明の5iNX膜を用いた他の応用
の半導体装置も優れた特性のものが得られる。
Function The present invention improves the film quality of the SiNx film, thereby improving the film quality of the SiNx film.
This provides a-8iTPT that is stable for a longer period of time than 0 times. Furthermore, the SiNx film according to the present invention has excellent film quality especially near the interface and has few trap levels, so it can provide an a-3i TFT with excellent characteristics. Therefore, other applied semiconductor devices using the 5iNX film of the present invention can also have excellent characteristics.

実施例 第2図に、a−3iTFTの一実施例の要部構造断面図
を示す。ガラス基板1上K Cr 、 Mo S 12
等の導電体をゲート電極2として選択的に形成する。1
3.56 MHzのグロー放電を用いた平行平板型のプ
ラズマCVD法でゲート絶縁膜3として5eooA程度
の膜厚のSiNx膜と、半導体膜4としてSiN工膜と
同じプラズマ化学気相堆積法で300人程鹿のa−3L
膜を連続的に堆積し、エツチング等でa−5i膜を選択
的に除去し島状のa−3i膜のパターン4を形成する。
Embodiment FIG. 2 shows a cross-sectional view of the main structure of an embodiment of an a-3i TFT. KCr, MoS 12 on glass substrate 1
A conductor such as the like is selectively formed as the gate electrode 2. 1
A SiNx film with a thickness of about 5eooA was formed as the gate insulating film 3 using a parallel plate plasma CVD method using a glow discharge of 3.56 MHz, and a SiNx film with a thickness of about 5eooA was formed as the semiconductor film 4 using the same plasma chemical vapor deposition method as the SiN film. Hitoshika's a-3L
A film is continuously deposited, and the a-5i film is selectively removed by etching or the like to form an island-like pattern 4 of the a-3i film.

a−3i膜パターン4とAl、 MOS 12等の導電
体からなる選択的に被着形成されたソース電極6とドレ
イン電極7との間に、リンを不純物として含むn+型の
a−9i膜5を膜厚500人程連速択的に残してa−3
iTFTが製作される。a−3iTFTの特性において
、我々の研究によると、特にオン特性と信頼性は、ゲー
ト絶縁膜として用いるSiNx膜の膜質によって大いに
左右される。
An n+ type a-9i film 5 containing phosphorus as an impurity is interposed between the a-3i film pattern 4 and a selectively deposited source electrode 6 and drain electrode 7 made of a conductor such as Al or MOS 12. A-3 with a film thickness of about 500 continuous speed selectively left
iTFT is manufactured. According to our research, the characteristics of a-3i TFTs, especially the on-characteristics and reliability, are greatly influenced by the quality of the SiNx film used as the gate insulating film.

更に、これらのSiNx膜の膜質の内で電子スピン密度
が最適なSiN工膜を示す大きなパラメータであること
が解った。
Furthermore, it has been found that among the film qualities of these SiNx films, the electron spin density is a major parameter that indicates an optimal SiN film.

本実施例におけるSiNx膜の電子スピン密度は、a 
−St T F Tを作製するのと同じ条件で比抵抗が
200〜240Ω・(7)の両面研摩された単結晶シリ
コン基板上にSiNx膜を堆積させ、基板温度が26、
Q±3.0℃の状態で電子スピン共鳴装置を用いてq 
fMが2.006〜2.006のシリコンの電子スピン
数を測定し、シリコン基板だけの場合の電子スピン数を
減じて、SiN工膜の電子スピン数とし、劣化は、特に
ゲートのしきい値電圧V、に表われ、印加したゲート電
圧の符号の正、負により同符号のV、のシフトが生じる
The electron spin density of the SiNx film in this example is a
-St T F A SiNx film was deposited on a double-sided polished single crystal silicon substrate with a resistivity of 200 to 240 Ω (7) under the same conditions as for fabricating the T F T, and the substrate temperature was 26°C.
q using an electron spin resonance device at Q±3.0℃
The electron spin number of silicon with fM of 2.006 to 2.006 is measured, and the electron spin number of the SiN film is obtained by subtracting the electron spin number of the silicon substrate alone. It appears as a voltage V, and depending on whether the sign of the applied gate voltage is positive or negative, a shift of V with the same sign occurs.

本実施例におけるゲートのしきい値電圧■、は、第2図
に示すa−3iTFTにおいて、チャンネル幅W、チャ
ンネル長りのW/L比が66.7のものを用い、基板温
度25.0±3℃で暗所の環境の中でソース接地、ドレ
イン電圧15Vを一定に印加した時にドレイン電流がl
X10  Aになる時のゲート電工とした。またV、シ
フト量はa−StTFTを長時間動作させ終了した時の
しきい値電圧■tからa−3iTFT作製直後のゲート
しきい値電圧V、を減じたものである。
The gate threshold voltage (■) in this example is determined by using an a-3i TFT shown in FIG. 2 with a channel width W and a channel length W/L ratio of 66.7, and a substrate temperature of 25.0. When the source is connected and a constant drain voltage of 15V is applied in a dark environment at ±3℃, the drain current is l.
I worked as a gate electrician when it became X10A. The shift amount V is obtained by subtracting the gate threshold voltage V immediately after fabricating the a-3i TFT from the threshold voltage t when the a-StTFT has been operated for a long time.

第3図にSiNx膜の電子7ピン密度が1.7X101
8/7ff’のa−3iTFTのV、シフトの模様を示
す。
Figure 3 shows that the electron 7 pin density of the SiNx film is 1.7X101.
The V of the 8/7ff' a-3i TFT shows the shift pattern.

a−3iTFT作製直後の特性がへ曲線であり、■、−
vt1z5.9■テアツタ。a−8iT F T 全暗
所の乾燥窒素ガス雰囲気中25.o±3.0℃の環境で
ソース接地、ドレイン電圧12V、ゲート電圧30V一
定(直流動作条件)で30分動作させた後(7) 特性
力B 曲線テアリ、Vt=Vt2=9.TVト、■、が
正のシフトを示し、ゲート電圧が15Vの場合のドレイ
ン電流は初期ID1=17μAであったものが動作後で
はID2=8μAと半減してしまっている。
The characteristics of a-3i TFT immediately after fabrication are curves, and ■, -
vt1z5.9■ Tea Tsuta. a-8iT F T In a dry nitrogen gas atmosphere in complete darkness 25. After operating for 30 minutes in an environment of o±3.0°C with a common source, a constant drain voltage of 12 V, and a constant gate voltage of 30 V (DC operating conditions) (7) Characteristic force B Curve tear, Vt = Vt2 = 9. The drain current when the gate voltage is 15 V is initially ID1=17 μA, but after operation, it has been halved to ID2=8 μA.

第1図はS I H4ガスとNH3ガスの流量比、放電
パワー、真空度等のプラズマCVDの条件を種々変えて
作製したSiNx膜について、暗所の乾燥窒素ガス雰囲
気中26.0±3.0℃の環境で、ソース接地、ドレイ
ン電圧12■、ゲート電圧3oV一定(直流動作条件)
で30分動作させた時のvtシフト量を縦軸に、SiN
x膜の電子スピン密度を横軸にプロットした図である。
Figure 1 shows SiNx films produced under various plasma CVD conditions such as the flow rate ratio of S I H4 gas and NH3 gas, discharge power, degree of vacuum, etc. in a dry nitrogen gas atmosphere in the dark at 26.0±3. In an environment of 0℃, source common, drain voltage 12■, gate voltage constant 3oV (DC operating conditions)
SiN
It is a diagram in which the electron spin density of the x film is plotted on the horizontal axis.

第1図に於いて、プラズマCVDの条件の種々異なる膜
であっても、電子スピン密度をパラメーターにすること
により、a−8iTFTのvtシフト量が2つの直線上
に並ぶ。そして、電子スピン密度が約2.4XIQ  
c7Rより大きくなると、v七シフト量が電子スピン密
度の増加とともに増大することが明らかになった。
In FIG. 1, even when films are subjected to various plasma CVD conditions, by using the electron spin density as a parameter, the vt shift amount of the a-8i TFT is aligned on two straight lines. And the electron spin density is about 2.4XIQ
It has become clear that when the value becomes larger than c7R, the amount of v7 shift increases as the electron spin density increases.

第4図は、a−8iTFTを第2図のガラス基板に対し
、a−SiTPTが形成されていない側の表面で照度が
8000/レツクスになるように蛍光灯で照明され、乾
燥窒素ガス雰囲気中80.0±3′Cの環境でソース接
地、ゲート電極にパルス幅60μ式で60田のピークと
ピーク間が21Vのパルス電圧を印加し、ドレインに3
01−itでピークとピーク間が4vの交流矩形e(交
流動作条件)を印加し1000時間動作させた時のV、
シフト量を縦軸にSiN工膜の電子スピン密度を横軸に
プロットした図である。先きの第1図と同様にSiNx
膜の電子スピン密度が2.4 X 10  口 より大
きくなると、a−3iTFTのv1ンフト量がS I 
Nx膜の増加とともに増大することが解る。またSiN
Figure 4 shows an a-8i TFT placed on the glass substrate of Figure 2, illuminated with a fluorescent lamp so that the illumination intensity is 8000/rex on the surface on which the a-SiTPT is not formed, and placed in a dry nitrogen gas atmosphere. In an environment of 80.0±3'C, a pulse voltage of 21V between peaks of 60°C with a pulse width of 60μ is applied to the gate electrode with the source grounded, and the drain voltage is 3V.
V when applying AC rectangular e (AC operating condition) with 4V peak-to-peak at 01-it and operating for 1000 hours,
It is a diagram in which the shift amount is plotted on the vertical axis and the electron spin density of the SiN film is plotted on the horizontal axis. Similar to the previous figure 1, SiNx
When the electron spin density of the film becomes larger than 2.4 × 10 , the v1 amplitude of the a-3i TFT becomes S I
It can be seen that it increases as the Nx film increases. Also, SiN
.

膜の電子スピン密度が2.4X10ff  以下に小さ
くなるとη シフトが測定限界以下になる事が明らかに
なった。
It has become clear that when the electron spin density of the film becomes less than 2.4×10ff, the η shift becomes below the measurement limit.

以上のことから、信頼性にすぐれたa−3iTFTを得
るには、S iNx膜の電子スピン密度が2.4 X 
10 3  以下に小さいことが必要であることが解る
From the above, in order to obtain a highly reliable a-3i TFT, the electron spin density of the SiNx film must be 2.4
It can be seen that it is necessary to be as small as 10 3 or less.

発明の効果 本発明による電子スピン密度が2.4X10ff以下に
小さいプラズマCVD法で作製された5iN3c膜は、
前述した様に界面付近の準位密度が小さく、半導体装置
の層間絶縁膜やパッシベーション膜としてすぐれている
と考えられる。更に、a−Si膜と組合せて、ゲート絶
縁膜として本発明の5INx膜を用いたa−3iTFT
は、従来報告されているものに比ベロ00倍以上の寿命
を有する。
Effects of the Invention The 5iN3c film produced by the plasma CVD method with a small electron spin density of 2.4×10ff or less according to the present invention has the following properties:
As mentioned above, the level density near the interface is low, and it is considered to be excellent as an interlayer insulating film or a passivation film for semiconductor devices. Furthermore, an a-3iTFT using the 5INx film of the present invention as a gate insulating film in combination with an a-Si film
has a lifespan that is 00 times longer than that previously reported.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるa−SiTFTの要
部構造断面図、第2図はSiNx膜の電子スピン密度と
直流動作を30分行った場合のa−3iTFTのゲート
しきい値電圧の■、シフト量との関係を示す特性図、第
3図は縦軸にドレイン電流、横軸にゲート電圧をプロッ
トし、■、シフトの様子を示した特性図、第4図は5i
NX膜のスピン密度と交流動作を1000時間行った時
のa−5iTPTのゲートしきい値電圧vtンシフ量と
の関係を示す特性図である。 1・・・・・・ガラス基板、2・・・・・ゲート電極、
3・・・・・・SiNx膜、4−・・−a −Si膜、
5−・・・n+型a−3i膜、6・・・・・・ソース電
極、了・・・・・・トシイン電極。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 ガ  ラ  ス 基 1罠 づ−一ト電歇 SiNx野財 Q−9i膜 n?梨α−5iW胃 ソース電極 トレインを槌 Vtシフトt <V) 仝 第 図 ゲート電圧 (v)
Figure 1 is a cross-sectional view of the main part structure of an a-SiTFT in one embodiment of the present invention, and Figure 2 is the electron spin density of the SiNx film and the gate threshold voltage of the a-3iTFT when DC operation is performed for 30 minutes. ■, Characteristic diagram showing the relationship with the shift amount, Figure 3 plots the drain current on the vertical axis and gate voltage on the horizontal axis, ■, Characteristic diagram showing the state of shift, Figure 4 shows the 5i
FIG. 3 is a characteristic diagram showing the relationship between the spin density of the NX film and the gate threshold voltage vt shift amount of a-5iTPT when AC operation is performed for 1000 hours. 1...Glass substrate, 2...Gate electrode,
3...SiNx film, 4-...-a-Si film,
5-...n+ type a-3i film, 6...source electrode, end...tosine electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure glass base 1 trap - 1 electric switch SiNx field Q-9i film n? Pear α-5iW gastric source electrode train Vt shift t<V) Fig. Gate voltage (v)

Claims (5)

【特許請求の範囲】[Claims] (1)基板上の一主面上に互いに接する半導体層と絶縁
膜とを一部の構成体として有し、前記絶縁膜が2.4×
10^1^7cm^−^3以下の電子スピン密度を有す
るシリコン窒化膜であることを特徴とする半導体装置。
(1) A semiconductor layer and an insulating film that are in contact with each other on one main surface of a substrate are included as part of the structure, and the insulating film is 2.4×
A semiconductor device characterized in that it is a silicon nitride film having an electron spin density of 10^1^7 cm^-^3 or less.
(2)絶縁膜が、プラズマ化学気相堆積法によって作製
されたシリコン窒化膜であることを特徴とする請求項1
記載の半導体装置。
(2) Claim 1, wherein the insulating film is a silicon nitride film produced by plasma chemical vapor deposition.
The semiconductor device described.
(3)絶縁膜が、電界効果トランジスタのゲート絶縁膜
であることを特徴とする請求項1記載の半導体装置。
(3) The semiconductor device according to claim 1, wherein the insulating film is a gate insulating film of a field effect transistor.
(4)半導体層が、非晶質シリコン膜であることを特徴
とする請求項1記載の半導体装置。
(4) The semiconductor device according to claim 1, wherein the semiconductor layer is an amorphous silicon film.
(5)半導体層が、プラズマ化学気相堆積法によって作
製された非晶質シリコン膜であることを特徴とする請求
項1または4記載の半導体装置。
(5) The semiconductor device according to claim 1 or 4, wherein the semiconductor layer is an amorphous silicon film produced by plasma chemical vapor deposition.
JP63160101A 1988-06-28 1988-06-28 Method for manufacturing semiconductor device Expired - Lifetime JPH0727900B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63160101A JPH0727900B2 (en) 1988-06-28 1988-06-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63160101A JPH0727900B2 (en) 1988-06-28 1988-06-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH029129A true JPH029129A (en) 1990-01-12
JPH0727900B2 JPH0727900B2 (en) 1995-03-29

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Country Status (1)

Country Link
JP (1) JPH0727900B2 (en)

Cited By (8)

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US5175763A (en) * 1990-03-27 1992-12-29 Siemens Aktiengesellschaft Two-wire/four-wire converter
WO2010041446A1 (en) * 2008-10-08 2010-04-15 株式会社アルバック Vacuum processing apparatus
JP2013254950A (en) * 2012-05-10 2013-12-19 Semiconductor Energy Lab Co Ltd Semiconductor device
JP2015062223A (en) * 2013-08-23 2015-04-02 株式会社半導体エネルギー研究所 Semiconductor device
US20150102341A1 (en) * 2013-10-10 2015-04-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2019125809A (en) * 2012-05-10 2019-07-25 株式会社半導体エネルギー研究所 Semiconductor device
JP2020030419A (en) * 2012-08-23 2020-02-27 株式会社半導体エネルギー研究所 Display device

Citations (5)

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