JPH0290714A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for the phase lock between an input signal and a processing clock by generating a digital signal phase-locked with a sampling clock by an arithmetic circuit receiving an output of a coefficient generator controlled with a phase difference of a signal subject to digital conversion and an input digital signal. CONSTITUTION:An A/D conversion circuit 2 converts an analog signal inputted from an analog input terminal 1 by using a sampling clock generated from a sampling clock generating circuit 3. A burst gate 22 extracts a color burst signal from the digital signal, a reference signal generating circuit 24 generates a reference color burst signal phase-locked with the sampling clock and a phase difference detection circuit 23 detected a phase difference between the two color burst signals. Thus, the phase lock between the input signal and the processing clock by the analog circuit is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing circuit for video signals, and more particularly to a digital signal processing circuit suitable for performing processing in which an input signal and a sampling clock are phase-locked. .

[Conventional technology]

Conventionally, in digital signal processing circuits that perform processing in which an input signal and a sampling clock are phase-locked, an analog circuit has been used to generate a clock signal that is phase-locked to the input signal. - As an example, FIG. 3 shows a digital signal processing circuit that receives a chroma signal as input and performs signal processing using a clock phase-locked to the color burst signal of the chroma signal.

In FIG. 3, the burst gate 30 has the analog input terminal 1 as its input, the sampling clock generation circuit 31 has the output of the burst gate 31 as its input, and the A/D conversion circuit 2 has the output of the burst clock generation circuit 31 as its input. The output is used as a black input, the analog input terminal is used as a data input, and the data is output to the digital output terminal 17. The burst gate 30 extracts a color burst signal from the input analog signal through analog processing, and the sampling clock generation circuit 31 is phase-locked to the color burst signal using, for example, a phase-locked loop circuit (hereinafter abbreviated as PLL circuit). A clock is generated, and the A/D conversion circuit 2 converts an analog input signal into a digital signal in accordance with this clock.

[Problem to be solved by the invention]

As mentioned above, in conventional digital signal processing circuits, in order to perform digital signal processing in which the input signal and the sampling clock are phase-locked, an analog circuit is used to generate the sampling clock that is phase-locked to the input signal. When integrated into an LSI, a relatively large number of external parts such as resistors and capacitors are required, making it difficult to miniaturize the device.

Furthermore, when a signal with time axis fluctuation (hereinafter referred to as jitter) is input, such as the output of a magnetic recording reproduction device (hereinafter referred to as VTR), the sampling clock also has jitter, so other digital The disadvantage is that it is difficult to interface with a signal processing circuit.

output terminals, and the output of an arithmetic circuit that uses the digital signal input terminal group as one input, or a phase detection circuit that uses the digital input terminal group as input, and a coefficient generation circuit that uses the output of the phase detection circuit as input. The output of the coefficient generation circuit is used as the other input of the calculation.

The coefficient generation circuit includes an address generation circuit that receives the output of the phase detection circuit as an input, and a plurality of ROMs that receive the output of the address generation circuit as input, and the output of the ROM is used as the input of the coefficient generation circuit. .

The arithmetic circuit is a digital filter having a plurality of data latches, a multiplier, and an adder.

The coefficient generation circuit includes a read address generation circuit and a plurality of read-only memories each having an output from the read address generation circuit as an input; The output may be used as the output of the coefficient generation circuit.

The arithmetic circuit may be a digital filter.

The signal input from the digital input terminal group is a chroma signal, and the phase detection circuit includes a burst gate that receives the digital signal input, a reference signal generation circuit that receives the sampling clock input, and the burst gate output. and a phase difference detection circuit which inputs the output of the reference signal generation circuit, and the output of the phase difference detection [i:+1 path] may be used as the output of the phase detection circuit.

The signal input from the digital signal input of the phase detection circuit is a luminance signal, and the phase detection circuit includes a synchronization separation circuit that receives the digital signal input, and a reference signal generation circuit that receives the sampling clock input. The phase difference detection circuit may be comprised of a phase difference detection circuit which receives the output of the synchronization separation circuit and the output of the reference signal generation circuit, and the output of the phase difference detection circuit may be used as the output of the phase detection circuit.

If the signal inputted from the digital input terminal group is a frequency modulation signal (hereinafter abbreviated as FM signal), the arithmetic circuit may include at least FM demodulation means.

〔Example〕

FIG. 1 shows, as an embodiment of the present invention, a circuit diagram of a digital signal processing circuit that performs processing in which a color burst signal of a chroma signal and a sampling clock are phase-locked. In the first factor, the (A/l) conversion circuit 2U uses the analog input terminal l as a data input, and the output of the sampling clock generation circuit 3 as a clock input, and the burst gate 22 uses the output of the A/D conversion circuit 2. The phase difference detection circuit 23 uses the output of the burst gate 22 as one input, the output of the reference signal generation circuit 24 as the other input, and the output of the sampling clock generation circuit 3 as the reference signal generation circuit 24. The read address generation circuit 25 receives the output of the phase difference detection circuit 23, the read-only memories (hereinafter referred to as ROM) 18 to 21 receive the output of the read address generation circuit 25, and the digital filter circuit 5 receives the output of the phase difference detection circuit 23. The output of the /D conversion circuit 2 is used as one input, the output of the ROMs 18 to 21 is used as the other input, and the output of the digital filter circuit 5 is used as the digital output terminal 17.
It is said that The digital filter circuit 5 is composed of data latches 6 to 9, multipliers 10 to 13, and adders 14 to 16. The input of the digital filter circuit 5 is used as the input of the data latch 6, and the output of the data latches 6 to 8 is Data latches 6 to 9 are input to data latches and chia to 9, respectively.
The output of is set as one input of each multiplier 10 to 13,
The outputs of ROMs 18 to 21 are transmitted to multipliers 10 to 13, respectively.
The outputs of multipliers 10-13 are used as one input of adders 14-16, respectively, and the outputs of multiplier 9 and the outputs of adders 14.15 are used as one input of adders 14-16, respectively.
16, and the output of the adder 16 is used as the output of the digital filter circuit 5.

The A/D conversion circuit 2 converts an analog signal input from the analog input terminal 1 into a digital signal using a sampling clock generated by the sampling clock generation circuit 3. The burst gate 22 extracts the color burst signal from this digital signal, the reference signal generation circuit 24 generates a reference color burst signal whose phase is locked to the sampling clock, and the phase difference detection circuit 23 extracts the color burst signal.
The phase difference between these two color burst signals is detected.

The read address generation circuit 25 generates coefficients for correcting the phase difference according to this phase difference.
Generate a read address of 1.

The characteristics are changed according to the coefficients read from digital filter circuit 5 #iROM18 to 21, and the A/D conversion circuit 2
By giving an appropriate delay to the output of , a digital signal whose phase is locked to the sampling clock is generated, and the digital signal is output from the digital filter circuit 5 . Here, the phase difference detection circuit 23 uses, for example, an FM demodulation means to convert the color burst signal output from the burst gate 22.
The phase signal is detected and subtracted from the phase signal of the reference burst signal generated by the reference signal generation circuit 24 to determine whether the phase of the color burst signal of the input chroma signal is ahead or behind the sampling clock. The read address generation circuit that detects the phase signal is, for example, U
It consists of a P/DOWN counter, and the counter value is increased or decreased based on a relative phase signal. here,
There are 4 ROMs, ROM address input is 4 pins,
4x oversampling filter H(z)"[(z1+z-')+2(z"+z-")+
3 (z"+z-")+4:1・z-474 coefficient (1/4, 2/4, 3/4, 1, 3/4
, 2/4, 1/4) as ROM data as shown in Table 1, the larger the ROM address input, the more the phase of the output signal of the digital filter 5 can be delayed.

The following margins are shown in Table 1 and Figure 2 as a second embodiment of the present invention.
This is a digital signal processing circuit that performs post-M post-processing digital signal processing, and performs processing in which the synchronization signal of the luminance signal after FM demodulation and the processed black and white signals are phase-locked. In FIG. 2, the analog input terminal 1 of the A/D conversion path circuit 2 is used as a data input, the output of the sampling clock generation circuit 3 is used as a clock input, and the digital filter circuit 5 is connected to the output of the A/D conversion circuit 2. is used as one input and the output of the digital filter circuit 5 is input to the FMM modulator 5o, the output of the pM tuner 50 is output to the digital output terminal 17, and the synchronization separation circuit 26 receives the output of the FM tuner 5o. The phase difference detection circuit 27 uses the output of the synchronous separation circuit 26 as one input, the output of the reference signal generation circuit 28 as the other input, and the output of the sampling clock generation circuit 3 as the reference signal generation circuit 28. The read address generation circuit 25 receives the output of the phase difference detection circuit 27 as an input, and the ROMs 18 to 21 receive the output of the offset address generation circuit 2.
The output of ROM 9 is used as an input, and the output of ROM 18 to 21 is used as the other input of digital filter circuit 5.

The A/D conversion circuit 2 converts the analog signal input from the analog input terminal 1 into a digital signal using the sampling clock generated by the sampling clock generation circuit 3, and outputs the digital signal to the digital filter circuit 5. The synchronization separation circuit 26 extracts a synchronization signal from the luminance signal generated by the FMM modulator 50, and the reference signal generation circuit 28 generates a reference synchronization signal whose phase is different from the sampling clock. Now, detect the phase difference between these two synchronization signals. Thereafter, the same processing as in the first embodiment is performed to generate a digital signal whose phase is shifted from the sampling clock.

The burst gate 22, the phase difference detection circuit 23, and the reference signal generation circuit 24 are means for detecting phase information of an input digital signal, and for example, the following can be used as a reference.

“Digital carrier color signal processing circuit” [Published] 1986-0152190 (JVC)'
"Digital color signal demodulation circuit" [Publication] 1982-82795 (NEC) The following can be used as a reference for the FM demodulation circuit 50.

"Frequency demodulation device" [Application] 1986-290008 (NEC) The phase difference detection circuit 27 and the reference signal generation circuit 28 are means for detecting the phase difference between two pulses. For example, the following can be referred to. .

-Design and Practical Circuit of PLL by Howard M, BERLIN Miya 1) Hide Translated by Mytic P27 Figure 3-11 [Effect of the Invention] As explained above, the present invention detects the phase of a digitally converted signal using a phase detection circuit. It is possible to generate a digital signal that is phase-locked to the sampling clock using the output of a coefficient generator controlled by the phase difference and the input digital signal as input. There is no need to phase lock the input signal and processing clock using a circuit, and the digitization of the circuit makes it suitable for LSI integration, making it possible to miniaturize equipment.In addition, the sampling clock is always stable regardless of the jitter of the input signal. This has the effect of making it easier to interface with other digital signal processing circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the invention, FIG. 2 is a circuit diagram showing a second embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional example. 2...A/D conversion circuit, 5...Digital filter circuit, 50...FM demodulation circuit, 6
~9...Data latch, 10-13...
- Multiplier, 14-16... Adder, 17...
... Digital output terminal, 18-21 ... Read-only memory, 22 ... Burst gate,
23...Phase difference detection circuit, 24...Reference signal generation circuit, 25...T extraction address generation circuit, 26...Synchronization separation circuit, 27...
... Phase difference detection circuit, 28 ... Reference signal generation circuit, 29 ... Read address generation circuit, 3
0...Past Gate. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] a group of digital signal input terminals, an arithmetic circuit whose one input is a signal input from the group of digital signal input terminals, and an output of the arithmetic circuit or a signal input from the group of digital input terminals which is used as a digital signal input. The output of the coefficient generator is used as the other input of the arithmetic circuit, and the signal input from the digital input terminal group is sampled. A digital signal processing circuit characterized in that a clock is used as a sampling clock input of the phase detection circuit.