JPH0290639A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0290639A
JPH0290639A JP24364888A JP24364888A JPH0290639A JP H0290639 A JPH0290639 A JP H0290639A JP 24364888 A JP24364888 A JP 24364888A JP 24364888 A JP24364888 A JP 24364888A JP H0290639 A JPH0290639 A JP H0290639A
Authority
JP
Japan
Prior art keywords
bonding
stage
profile
deformation resistance
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24364888A
Other languages
Japanese (ja)
Inventor
Kouji Ooshige
大重 稿二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24364888A priority Critical patent/JPH0290639A/en
Publication of JPH0290639A publication Critical patent/JPH0290639A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To minimize the mechanical damage to a semiconductor element by a method wherein the bonding pressure conforming to the history of the deformation resistance of a material used for lead and bump electrode is specified to perform the bonding process in compliance therewith. CONSTITUTION:Assuming the bonding times O-to, to-tp and tp-termination T to be termed stage 1, stage 2 and stage 3, the profile of bonding pressure P in the stage 1 conforms to the profile of deformation resistance in the elasticity region of material (epsilon<=epsilono). At this time, the elastic deformation 0-epsilono corresponds to the bonding time O-to-(epsilon=epsilon.t). Within the stage 2, the profile of bonding pressure after exceeding the yield stress Y of the material conforms to the profile of deformation resistance in the plasticity region of material (epsilon>epsilono). During the unloading process, the profile of the bonding pressure in the stage 3 conforms to the profile of deformation resistance in the elasticity region of material similar to the case in the stage 1 in consideration of the spring back after the plasticity deformation of the material.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に突起型電極
付半導体装置のインナーリードボンディングの方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of inner lead bonding of a semiconductor device with protruding electrodes.

〔従来の技術〕[Conventional technology]

従来の技術として、フィルムキャリア型半導体装置のボ
ンディング、ずなわちTAB(Tape^utoiat
ed Bonding )方式によるI L B (I
nnerLead Bonding)は次のように行わ
れている。
As a conventional technique, bonding of film carrier type semiconductor devices, that is, TAB (Tape
ILB (I
nnerLead Bonding) is performed as follows.

すなわち、スプロケットホールを持ったポリイミドテー
プに銅箔をラミネートし、これにボンディングワイヤー
に相当するリードパターンをフォトエツチングにて形成
した後、金または錫あるいは半田をメツキしたTABテ
ープと、外部引き出し用電極上に突起型電極〈以下、バ
ンプと称する)を形成した半導体素子(ベレット)を準
備する。
That is, copper foil is laminated onto a polyimide tape with sprocket holes, a lead pattern corresponding to a bonding wire is formed on this by photo-etching, and then a TAB tape plated with gold, tin, or solder and an electrode for external extraction are formed. A semiconductor element (bellet) having a protruding electrode (hereinafter referred to as a bump) formed thereon is prepared.

そして、このバングにポリイミドテープと金または錫あ
るいは半田メツキされた銅箔で形成されるテープキャリ
アのリードを重ね合わせ、上からボンディングツールに
て加圧加熱してボンディングを行っている。
Then, polyimide tape and leads of a tape carrier made of gold, tin, or solder-plated copper foil are superimposed on this bang, and bonding is performed from above by applying heat and pressure with a bonding tool.

あるいは、TABテープにリードパターンを形成すると
ともに、リード先端部をフォトエツチングにてハーフエ
ツチングを施し、このリード先端部にバンプを形成した
後、少なくとも一層の金属層(例えば金)にてメツキを
施し、通常の半導体素子の外部引き出し用電極上にこの
リードを重ね合わせ、上からボンディングツールにて加
圧加熱してボンディングを行っている。
Alternatively, a lead pattern is formed on the TAB tape, half-etching is performed on the lead tip by photo-etching, a bump is formed on the lead tip, and then plating is performed with at least one metal layer (for example, gold). This lead is superimposed on the external lead electrode of a normal semiconductor element, and bonding is performed by applying pressure and heating from above using a bonding tool.

ところで、このボンディング時の加圧方法は、第2図(
電子材料、 1985年5月、PI3より引用)および
第3図(Ha口onal Technical Rep
ort 187゜Vol、33. No、I P23よ
り引用)ニ見られるように、ボンディング圧力(荷重)
はボンディング時間に対し、不連続なステップ荷重を採
用していた。
By the way, the method of applying pressure during bonding is shown in Figure 2 (
Electronic Materials, May 1985, quoted from PI3) and Figure 3 (Ha oral Technical Rep.
ort 187°Vol, 33. No. Quoted from I P23) As can be seen, the bonding pressure (load)
adopted a discontinuous step load for the bonding time.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のボンディング加圧方法は、ボンディング
時間に対して急激な圧力(荷重)変化を伴うステップ荷
重方法、すなわち動的荷重を負荷していることになるの
で、TABテープのリード。
The conventional bonding pressurization method described above is a step loading method that involves rapid changes in pressure (load) with respect to the bonding time, that is, a dynamic load is applied.

バンプおよび半導体素子基板のそれぞれに対し、ひずみ
速度i (j=dε/dtで、εは材料内部に生ずるひ
ずみ、tは時間)の速い変形挙動を強いられていること
になる。一般に材料は塑性変形に伴い、材料の加工硬化
が進行し、外部荷重(この場合ボンディング圧力)に対
する変形抵抗が非線形に増加する。また、ひずみ速度と
温度の変化に対し、材料の応力−ひずみ曲線は第4図(
塑性学と塑性加工、第2版、昭和57.オーム社。
The bump and the semiconductor element substrate are each forced to undergo rapid deformation behavior at a strain rate i (j=dε/dt, where ε is the strain generated inside the material and t is time). Generally, as a material undergoes plastic deformation, work hardening of the material progresses, and the deformation resistance against external load (bonding pressure in this case) increases nonlinearly. In addition, the stress-strain curve of the material with respect to changes in strain rate and temperature is shown in Figure 4 (
Plasticity and plastic working, 2nd edition, 1977. Ohmsha.

P9より引用)を見て明らかなように、その履歴が変化
する。つまり、材料の機械的特性が変化する。
As is clear from the above (quoted from page 9), the history changes. That is, the mechanical properties of the material change.

これらの理由からひずみ速度の速い従来のボンディング
加圧方法は、特にバング以下の半導体素子基板に動的過
渡応力を生ぜしめ余剰な機械的ダメージ、例えば、バン
プ以下の半導体素子基板にぜい性破壊あるいはへき開破
壊による微小なき裂の発生、進展が現われ、さらにこの
き裂が成長して半導体素子基板の巨視的な破壊、すなわ
ちバンプのはがれ等の不良が発生ずるという欠点があっ
た。
For these reasons, the conventional bonding pressurization method, which has a high strain rate, produces dynamic transient stress particularly on the semiconductor element substrate below the bump, resulting in excessive mechanical damage, such as brittle fracture on the semiconductor element substrate below the bump. Alternatively, there is a drawback that minute cracks are generated and propagated due to cleavage fracture, and these cracks further grow to cause macroscopic destruction of the semiconductor element substrate, that is, defects such as bump peeling occur.

本発明の目的は前記課題を解決した半導体装置の製造方
法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above problems.

〔発明の従来技術に対する相違点〕[Differences between the invention and the prior art]

上述した従来の半導体装置の製造方法(ボンディング加
圧方法)に対し、本発明はTABテープのリード、およ
びバンプに用いられた材料の、ボンディング圧力(外部
荷重)に対する加工硬化および変形抵抗の増加の履歴に
則したボンディング加圧方法を用い、半導体素子への機
械的ダメージをより小さくすることを可能とするという
相違点を有する。
In contrast to the conventional semiconductor device manufacturing method (bonding pressure method) described above, the present invention improves the work hardening and deformation resistance of the materials used for the TAB tape leads and bumps against bonding pressure (external load). The difference is that it uses a bonding pressure method that is consistent with the history, making it possible to further reduce mechanical damage to semiconductor elements.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため、本発明はフィルムキャリアテ
ープのリード先端部もしくは半導体素子上に設けられた
外部引き出し用電極パッド上のいずれか一方に突起型電
極を有する半導体装置に熱圧着プロセスにてボンディン
グを行う製造方法において、前記リードおよび前記突起
型電極に用いられた材料の変形抵抗の履歴に則したボン
ディング圧力を設定し、これに従ってボンディングを行
うものである。
In order to achieve the above object, the present invention provides bonding using a thermocompression bonding process to a semiconductor device having a protruding electrode on either the lead end of a film carrier tape or an external lead-out electrode pad provided on a semiconductor element. In the manufacturing method, a bonding pressure is set in accordance with the history of deformation resistance of the material used for the lead and the protruding electrode, and bonding is performed in accordance with this.

〔実施例〕〔Example〕

次に、本発明について図を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

(実施例1) 第1図は本発明の実施例1を示すボンディング圧力(荷
重)とボンディング時間との関係を示す図である。この
曲線の履歴は次式で表わされるP=F、・εt    
          (IP=Y+F・ (#−t−j
−t、)”   f2j=dε/dt=Δε/Δt  
     (3このときのPをボンディング圧力(kg
f/l112Fを材料の加工硬化係数(例えば銅で約2
5〜27kgf#g+g”) 、 Yを材料の静的降伏
応力(例えば銅で約25〜27kof/nm2> 、t
をボンディング時間、t、を材料が(2)式で表わされ
るひずみ速度1−定下で弾性限ひずみε、に到達するま
での時間(つまりt4=ε、/メで得られる)−nを材
料の加工硬化指数(例えば銅で約0.3前後)、Eを材
料の縦弾性係数(例えば銅で約0.7 x10’〜1、
Ox10’ kgf/nu’) ト定W>ル。
(Example 1) FIG. 1 is a diagram showing the relationship between bonding pressure (load) and bonding time showing Example 1 of the present invention. The history of this curve is expressed by the following formula: P=F,・εt
(IP=Y+F・(#-t-j
−t, )” f2j=dε/dt=Δε/Δt
(3 At this time, P is the bonding pressure (kg
f/l112F is the work hardening coefficient of the material (for example, about 2 for copper)
5 to 27 kgf#g+g''), Y is the static yield stress of the material (for example, about 25 to 27 kof/nm2 for copper), t
where t is the bonding time, t is the time required for the material to reach the elastic limit strain ε under a constant strain rate of 1 expressed by equation (2) (that is, t4 = ε, /me) - n is the material E is the work hardening index of the material (for example, around 0.3 for copper), and E is the longitudinal elastic modulus of the material (for example, about 0.7 x 10' to 1 for copper).
Ox10'kgf/nu')

ボンディング時間0〜t、までをステージ1、t、〜t
、までをステージ2、t、〜終了までをステージ3と呼
ぶことにすると、ステージ1では、ボンディング圧力の
プロファイルが(1)式および(3)式で表わされてお
り、これは材料の弾性域内(ε≦ε、)における変形抵
抗のプロファイルに則している。このとき、弾性ひずみ
0〜ε、がボンディング時間0〜1.(ε=j−t)に
対応している。ステージ2では材料の降伏応力Yを越え
てからのボンディング圧力のプロファイルが(2)式お
よび(3)式で表わされており、これは材料の塑性域(
ε〉ε、)における変形抵抗のプロファイルに則してい
る。このときも、ステージ1と同様に塑性ひずみε、〜
ε、がボンディング時間t、〜1.<ε=i・t)に対
応している。ステージ1および2が負荷の過程であり、
材料の加工硬化の度合いに合わせて圧力負荷が実現され
る。
The bonding time from 0 to t is stage 1, t, to t.
The period from t to the end is called stage 2, and the period from t to the end is called stage 3. In stage 1, the bonding pressure profile is expressed by equations (1) and (3), and this is determined by the elasticity of the material. It conforms to the profile of deformation resistance within the range (ε≦ε,). At this time, the elastic strain is 0 to ε, and the bonding time is 0 to 1. (ε=j−t). In stage 2, the bonding pressure profile after exceeding the yield stress Y of the material is expressed by equations (2) and (3), which are expressed in the plastic region of the material (
It conforms to the profile of deformation resistance at ε〉ε, ). At this time, as in stage 1, the plastic strain ε, ~
ε, is the bonding time t, ~1. <ε=i·t). Stages 1 and 2 are the loading process,
The pressure load is achieved according to the degree of work hardening of the material.

ステージ3は除荷の過程で、材料の塑性変形後のスプリ
ングバックを考慮して、ステージ1のときと同様に材料
の弾性域内における変形抵抗のプロファイルに則しであ
る。
Stage 3 is a process of unloading, and takes into account springback after plastic deformation of the material, and conforms to the profile of deformation resistance within the elastic range of the material, as in stage 1.

また(3)式はひずみ速度を決定するもので、Δεをひ
ずみ増分、Δtをボンディング時間の増分とし、dε/
dtは微分学の定義に則して記述したものである。この
ひずみ速度は高速度の圧縮試験にて、最適な大きさを決
定することで簡単に知ることができる。すなわち、所定
のボンディング温度付近にて、種々のひずみ速度tの下
で材料の高速度圧縮試験を行って、材料の変形抵抗の履
歴である応力σとひずみεとの各ひずみ速度に対応する
関係を定量的に求め、これらの中から準静的な圧縮試験
を行った時の応力σ−ひずみεの履歴と比較して、大き
く差異のない場合のひずみ速度tと応力σとひずみとの
関係を採用し、(3)式を変形した以下の(4)式 %式%(4) から、応力σ−ひずみεの関係をボンディング圧力−ポ
ンディング時間曲線に置き換える。
Equation (3) determines the strain rate, where Δε is the strain increment, Δt is the bonding time increment, and dε/
dt is described in accordance with the definition of differential theory. This strain rate can be easily determined by determining the optimal size in a high-speed compression test. That is, high-speed compression tests are performed on the material under various strain rates t near a predetermined bonding temperature, and the relationship between stress σ and strain ε, which is the history of the material's deformation resistance, corresponding to each strain rate is determined. Quantitatively determine the relationship between strain rate t, stress σ, and strain when there is no large difference by comparing the history of stress σ - strain ε when performing a quasi-static compression test from among these. The relationship between stress σ and strain ε is replaced by the bonding pressure-bonding time curve from the following formula (4), which is a modified version of formula (3).

(実施例2) 第5図は本発明の実施例2におけるボンディング圧力と
ボンディング時間との関係を示す図であり、これは、実
施例1で述べた曲線の履歴を表わす(2)式を以下に示
す区分多項式にて線形近似化したものである。
(Example 2) FIG. 5 is a diagram showing the relationship between bonding pressure and bonding time in Example 2 of the present invention. This is a linear approximation using the piecewise polynomial shown below.

ボンディング時間にて、0〜t、をステージ1、t、〜
1+をステージ2、t、〜t2をステージ3、t2〜t
、をステージ4、t3〜t、をステージ5、t、〜終了
をステージ6と呼ぶことにすると、ステージ1では、予
荷重P、を加えた後、実施例1と同様に弾性域内におけ
る変形抵抗プロファイルに則したボンディング圧力負荷
を行っている。ステージ2からステージ5では、ボンデ
ィング時間t、〜t、の間を数置間に区分し、その各区
間を対応する線形多項式にて、線形近似化してあり、そ
れぞれ次の様な形で定められているステージ2   P
+=α+jt      (4ステージ3  P2=α
2jt      (5ステージ4  P3=αsit
      (6ステージ5  P4=α<jt   
   (7これらは一般的に表わすと、任意の区間1に
てP、=α1めt (1=1.2. ・・−m、iは区分化された数)(8
)として得られ、実施例1の(3)式と連立して用いら
れる。
At bonding time, 0~t, stage 1, t,~
1+ to stage 2, t, ~t2 to stage 3, t2 to t
, is called stage 4, t3 to t is called stage 5, and t to the end is called stage 6. In stage 1, after applying the preload P, the deformation resistance in the elastic region is increased as in Example 1. Bonding pressure load is applied according to the profile. In stages 2 to 5, the bonding time t, ~t, is divided into several intervals, and each interval is linearly approximated by the corresponding linear polynomial, and each is determined in the following form. Stage 2 P
+=α+jt (4 stage 3 P2=α
2jt (5 stage 4 P3=αsit
(6 stage 5 P4=α<jt
(7 These are generally expressed as P in any interval 1, = α1th t (1 = 1.2. -m, i is the number of segments) (8
), and is used in conjunction with equation (3) of Example 1.

また、ステージ6は実施例1の場合と同様に、除荷の過
程であり、材料の塑性変形後のスプリングバックを考慮
してボンディング圧力の時間に対する傾きを材料の縦弾
性係数に等しく取っである。
Stage 6 is the unloading process as in Example 1, and the slope of the bonding pressure with respect to time is set equal to the longitudinal elastic modulus of the material in consideration of springback after plastic deformation of the material. .

以上のことより、この実施例では、ボンディング圧力の
負荷制御を線形制御できるので、制御が容易になるとい
う利点を持つ。
From the above, this embodiment has the advantage that the load control of the bonding pressure can be linearly controlled, making the control easier.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体装置に用いられた
材料(特にバンプ)の高速度圧縮試験をボンディング温
度付近の温度で行って、ひずみ速度−の影響が材料の変
形抵抗に対し大きく左右しない時のひずみ速度を知り、
この時の応力σ−ひずみεの変形抵抗履歴に則したボン
ディング圧力(荷重)と時間tの加圧曲線を設定し、こ
れに従ってボンディングを行うことにより、熱圧着プロ
セスにてボンディングを行う半導体装置へのatiIl
i的ダメージを小さくできる効果がある。
As explained above, the present invention performs a high-speed compression test on materials used in semiconductor devices (particularly bumps) at a temperature near the bonding temperature, so that the effect of strain rate does not significantly affect the deformation resistance of the material. Know the strain rate of time,
By setting a pressure curve of bonding pressure (load) and time t in accordance with the deformation resistance history of stress σ - strain ε at this time, and performing bonding according to this, the semiconductor device to be bonded by thermocompression bonding process. atiIl
This has the effect of reducing physical damage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第5図は本発明におけるボンディング加圧
曲線を示す図、第2図、第3図は従来のボンディング加
圧曲線を示す図、第4図は材料(銅)の温度とひずみ速
度が及ぼす材料の変形抵抗の履歴(σ−ε)の変化を示
す図である。 Y・・・材料の降伏応力 E・・・材料の縦弾性係数 F・・・材料の加工硬化係数 t・・・ひずみ速度(=dε/dt) P、Po 、P+ 、Pt 、Ps 、P4・・・ボン
ディング圧力 α l ― α 2 、 α 1 、 α 4・・・各
区分多項式における比例定数 t、・・・弾性限界ひずみε、に到達するまでのボンデ
ィング時間 t+、t2.ti・・・各区分多項式における任意のボ
ンディング区分時間 t、・・・ボンディング加圧の負荷過程が終了する時間 n・・・材料の加工硬化指数 σ・・・応力       ε・・・ひずみt・・・ボ
ンディング時間 第 図 第 図 碕r司t ・・・ボンディング温度 於ず〃ど 第4図
Figures 1 and 5 are diagrams showing bonding pressure curves in the present invention, Figures 2 and 3 are diagrams showing conventional bonding pressure curves, and Figure 4 is a diagram showing the temperature and strain rate of the material (copper). FIG. 4 is a diagram showing changes in the history (σ−ε) of the deformation resistance of the material. Y... Yield stress of material E... Longitudinal elastic modulus of material F... Work hardening coefficient of material t... Strain rate (=dε/dt) P, Po, P+, Pt, Ps, P4・... Bonding pressure α l - α 2 , α 1 , α 4 ... Proportionality constant t in each piecewise polynomial, ... Bonding time t+, t2 . . . until the elastic limit strain ε is reached. ti...Arbitrary bonding segment time t in each piecewise polynomial,...Time at which the bonding pressure loading process ends n...Work hardening index of the material σ...Stress ε...Strain t...・Bonding time diagram Figure 4. Bonding temperature diagram Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)フィルムキャリアテープのリード先端部もしくは
半導体素子上に設けられた外部引き出し用電極パッド上
のいずれか一方に突起型電極を有する半導体装置に熱圧
着プロセスにてボンディングを行う製造方法において、
前記リードおよび前記突起型電極に用いられた材料の変
形抵抗の履歴に則したボンディング圧力を設定し、これ
に従ってボンディングを行うことを特徴とする半導体装
置の製造方法。
(1) In a manufacturing method in which bonding is performed by a thermocompression bonding process to a semiconductor device having a protruding electrode on either the lead end of a film carrier tape or an external lead-out electrode pad provided on a semiconductor element,
A method for manufacturing a semiconductor device, characterized in that a bonding pressure is set in accordance with the history of deformation resistance of materials used for the leads and the protruding electrodes, and bonding is performed in accordance with this.
JP24364888A 1988-09-28 1988-09-28 Manufacture of semiconductor device Pending JPH0290639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24364888A JPH0290639A (en) 1988-09-28 1988-09-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24364888A JPH0290639A (en) 1988-09-28 1988-09-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0290639A true JPH0290639A (en) 1990-03-30

Family

ID=17106943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24364888A Pending JPH0290639A (en) 1988-09-28 1988-09-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0290639A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2020246094A1 (en) * 2019-06-04 2020-12-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2020246094A1 (en) * 2019-06-04 2020-12-10
WO2020246094A1 (en) * 2019-06-04 2020-12-10 田中電子工業株式会社 Palladium-coated copper bonding wire, method for producing palladium-coated copper bonding wire, semiconductor device using same, and method for producing same

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