JPH029020A - Focus control circuit - Google Patents

Abstract

PURPOSE:To always shift to a focusing pull-in state at an optimum time by bringing an input focusing shift signal to A/D conversion in a state before focusing pull-in in a focusing control circuit, deriving an average value in a prescribed period, and generating a focusing signal when the shift is equal to the average value. CONSTITUTION:A focusing shift signal SFE which has passed through an amplifying circuit 3 is brought to A/D conversion by a signal CKGEN of a circuit 23 based on a clock CLK from a control circuit 22 and goes to a signal DTFE. Based on the signal CKGEN, a phase compensating circuit 24 inputs a focusing servo-signal DTSB to a terminal (a) of a switching circuit 7. An FZC detecting circuit 25 generates a detecting signal DTFZC, based on a control signal CNTFZC. A servo-control circuit 26 generates a signal CNTPSI, based on a control signal CNTSB and the DTFZC, controls a focusing scanning circuit 27, and selects an input end of the switching circuit 7 by DTFS and CNTSWI. Subsequently, the output of the switching circuit 7 goes to a focusing coil driving signal SDV through a decoder 28, and an objective lens is driven in accordance with the DTSB or the DTFS through a driving circuit 9. According to such a constitution, it is always possible to enter into a focusing state at an optimum time irrespective of a value of a focusing bias signal.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A: Industrial field of application B: Outline of the invention C: Prior art (Figs. 3 and 4) D: Problems to be solved by the invention (Figs. 3 and 4) E: Means for solving the problems (FIGS. 1 and 2) F Effect (FIGS. 1 and 2) G Embodiment (FIGS. 1 and 2) H Effects of the Invention A Field of Industrial Application The present invention relates to a focus control circuit, For example, it is suitable for application to a focus control circuit of an optical disc device such as a compact disc (CD) player.

B Invention 1 Existing Invention The present invention provides a focus control circuit which adds a focus bias signal to a focus error signal so as to optimize a reproduced RF signal. In addition to converting the focus error data into digital values, the average value data for a predetermined period of time is calculated, and then a focus zero detection signal is sent at the timing when the focus error data becomes equal to the average value data. Therefore, regardless of the value of the focus bias signal added to the focus error signal, it is possible to always shift to the focus pull-in state at the optimal timing.

C. Prior Art Conventional CD players use, for example, a focus control circuit based on the astigmatism method to drive a two-axis device that holds the objective lens of the optical head, thereby keeping the laser beam always in just focus on the compact disc. There are some that control the irradiation so that it can be irradiated under certain conditions.

In addition, in this focus control circuit, prior to the above-mentioned focus servo operation, a two-axis device holding the objective lens is driven with a focus search signal consisting of an arbitrary ramp function to execute a focus search operation, thereby obtaining a desired result. The objective lens of the optical head shifts from focus search operation to focus servo operation at the timing when the zero-crossing point of the focus error signal (hereinafter referred to as focus zero-crossing point (FZC)), which is an S-shaped curve, is detected. The focus servo operation can be executed from a state as close to a just focus state as possible.

That is, as shown in FIG. 3, in this focus control circuit 1, a laser beam emitted from a semiconductor laser (not shown) is irradiated onto a compact disk (not shown), and the returned light is reflected. The light enters the light receiving section 2 which is made up of split light receiving elements.

As a result, the four light receiving elements 2A, 2B, 2 of the light receiving section 2
The first, second, third and fourth received light outputs 5FDA, 5FDI, 5FDC and S48.C obtained from C22D. are the first and third light receiving outputs S POA and 5F, respectively.
DC% 2nd and 4th light receiving output S PDll and S P
DD is added and input to the focus error amplification circuit 3 as first and second added signals S INI and SIN□.

In the focus error amplification circuit 3, the first and second addition signals SINI and SIN2 are converted from current values to voltage values via first and second buffer circuits 3A and 3B, and The input resistances R1 and R2 of
i! Then, it is manually inputted to the inverting input terminal and the non-inverting input terminal of the subtraction circuit 3C which is an operational amplifier.

In this subtraction circuit 3C, the inverting input terminal is connected to a predetermined negative feedback resistor R3, and the non-inverting input terminal is connected to a predetermined resistor R3.
The bias voltage (2) is obtained from the bias circuit 3D which is grounded through the terminal 4 and has a variable resistor VRI connected between the positive and negative power supplies (13) and 13 so as to obtain any voltage from any contact point. is supplied.

Note that this bias voltage ■□ is applied to each light receiving element 2 of the light receiving section 2.
This is to correct variations in the characteristics of A to 2D and adjustment errors in the optical system. For example, in the manufacturing process, the sum signal of the first to fourth received light outputs SPOA "' S poo, that is, the eye pattern of the reproduced RF signal, is corrected. The eye pattern is monitored and adjusted to a voltage value that can optimize the eye pattern.

In this way, the focus error amplification circuit 3 outputs the focus error signal sFt based on the astigmatism method using the four-divided light receiving elements 2A to 2D as the output signal of the subtraction circuit 3C.
The signal is sent to an FZC detection circuit 5 consisting of a phase compensation circuit 4 and a comparator circuit 5A having an operational amplifier configuration.

The FZC detection circuit 5 compares the input focus error signal SFE with a predetermined reference voltage VIIEF, and detects an FZC having the logic rHJ level during a period in which the voltage level of the focus error signal SFt is higher than the reference voltage V□. The signal S_FZC is sent to a servo control circuit 6 having a microcomputer configuration.

Further, the phase compensation circuit 4 compensates the phase of the input focus error signal SVt according to the servo characteristics, and sends it to the first input terminal a of the focus switching circuit 7 as a focus servo signal Ssm.

Note that a focus search circuit 8 is connected to the second input terminal of the focus switching circuit 7 based on the control of the servo control circuit 6.
A focus search signal SFS given from is input.

In addition, the focus switching circuit 7 receives a switching control signal CNT sw from the servo control circuit 6, and thus the output signal sent from the output terminal C of the focus switching circuit 7 is transmitted to the focus coil drive circuit. , 9 to the focus coil IOA of the two-axis device 10, and drives and controls the two-axis device 10, that is, the objective lens, in accordance with the focus servo signal S or the focus search signal SFS.

In this focus control circuit 1, for example, when a compact disc is loaded into a CD player, the servo control circuit 6 first detects this based on a CDfi control signal CN T co obtained from a system control circuit (not shown). , sends a switching control signal CNT'ssi for selecting the second input terminal to the focus switching circuit 7, and a focus search control signal CNTF for instructing the focus search circuit 8 to start a focus search operation.
Sends S.

Thereby, the focus search circuit 8 supplies the focus search signal srs having a predetermined ramp function waveform to the focus coil IOA of the two-axis device 10 via the focus switching circuit 7 and the focus coil drive circuit 9,
Gradually move the objective lens closer to the disk surface of the compact disk from its reference position when the compact disk is not mounted.

At this time, the system control circuit emits a laser beam from the semiconductor laser and receives the reflected light at the light receiving section 2, whereby a focus error signal srt obtained from the focus error amplification circuit 3 is inputted to the FZC detection circuit 5.

In practice, the focus error signal SFE obtained at this time
As shown in Fig. 4 (A), corresponds to the search time depending on the distance between the objective lens and the disk surface, the value sequentially rises from the θ level to the maximum value, then crosses the 0 level and rises to the minimum value. The FZC detection circuit 5 shows that the focus error signal syt is at the reference voltage V*! y (in this case, the reference voltage V REF has a voltage value of 0 (V)) from the time t0 when it crosses the reference voltage V□.

During this period, the FZC detection signal 5vzc (FIG. 4(B)) having the logic rHJ level is sent to the servo control circuit 6.

As a result, the servo control circuit 6 receives the FZC detection signal SF
The falling timing of ZC is detected, and at this timing, a switching control signal CN T sw for selecting the first input terminal a is sent to the focus switching circuit 7, and at the same time, the switching control signal CN T sw for selecting the first input terminal a is sent to the focus switching circuit 8. Focus search control signal CNTF for instructing termination
Sends S.

Thus, when a compact disc is loaded in the CD player, the focus control circuit 1 drives the focus coil IOA of the two-axis device 10 holding the objective lens with the focus search signal S□ to perform a focus search operation. The focus search operation is ended at the timing when the focus zero cross point of the focus error signal SFE formed by the S-shaped curve obtained by is detected.
a focus servo signal S obtained from the phase compensation circuit 4;
By driving the focus coil IOA of the two-axis device 10 using the following, focus servo operation is performed.

D Problems to be Solved by the Invention By the way, in the focus control circuit 1 having such a configuration, a bias voltage Vll is applied to the subtraction circuit 3C of the focus error amplification circuit 3, and the first to fourth light reception outputs S PDA
- Optimize the eye pattern of the sum signal of S PDll, that is, the reproduced RF signal, and
It is designed to correct variations in A to 2D and adjustment errors in the optical system.

However, in this focus control circuit 1, open loop control is actually performed during the focus search operation, and the focus search signal srs generated in the focus search circuit 8 is sent to the two axes via the focus switching circuit 7 and the focus coil drive circuit 9. It is supplied to the focus coil IOA of the device 10.

Therefore, during the focus search operation, the bias voltage 8. Offset voltage V according to. F occurs.

In this way the offset voltage ■. , F are caused by the focus error signal S, for example, a positive offset voltage V.

In the case of the focus error signal srt+ in which F is generated, a positive offset voltage V is generated as shown in FIG. 4(C).
. From the voltage level of FFI, FIG. 4(A), that is, the standard focus error signal sr! ■ Offset voltage to the maximum value of. After rising to the voltage level with FFI added,
It crosses the voltage level of the offset voltage VOFF+ and falls to the voltage level obtained by subtracting the offset voltage VOFF+ from the minimum value of the standard focus error signal SFE, and then the offset voltage ■. It forms an S-shaped curve that rises to the FFI voltage level.

Therefore, the FZC detection signal 5FICI obtained from the FZC detection circuit 5 is maintained for a predetermined time τ from the time t1 when the standard focus error signal SFE crosses the reference voltage VREF.

It falls to the logic rLJ level at a delayed time t (FIG. 4(D)).

Conversely, negative offset voltage ■. In the case of the focus error signal SFE□ in which FFt occurs, a negative offset voltage ■ is generated as shown in FIG. 4(E). □ Offset voltage ■ from the voltage level of 2 to the maximum value of the standard focus error signal SFE. After rising to the voltage level where FFt is added, it crosses the voltage level of the offset voltage V OFF□, and the offset voltage V OFF! is increased from the minimum value of the standard focus error signal SFE. falls to the voltage level obtained by subtracting V, and then the offset voltage V.

It forms an S-shaped curve that rises to the voltage level of FF2.

Therefore, the FZC detection signal S FZC2 obtained from the FZC detection circuit 5 starts from a time tz+, which is delayed by a predetermined time r from the time t0 when the standard focus error signal srt rises from the 0 level and crosses the reference voltage v*ty.
The standard focus error signal SFE has a logic rHJ level during a period of time txt which is two predetermined times earlier than the time t1 when the standard focus error signal SFE crosses the reference voltage V□1 (FIG. 4(F)).
.

In this way, the offset voltage V is applied to the focus error signal syt. , F, an error occurs at the time when the FZC detection signal 5F4e obtained from the FZC detection circuit 5 falls, and as a result, the objective lens of the optical head shifts to focus servo operation in a state where it is not in just focus state. As a result, there is a problem that the focus servo operation cannot be started in one go, or that the two-axis device 10 fluctuates when the focus search operation is executed many times.

In order to solve this problem, in the above-mentioned focus control circuit 1, the voltage value of the reference voltage VIIEF applied to the comparison circuit 5A of the FZC detection circuit 5 is set to the offset voltage 2 generated in the focus error signal SFt. , has been proposed to be made equal to .

However, if this is done, as shown in FIG. 4(G), if a lot of noise components occur in the focus error signal S03 obtained during the focus search operation, the FZC negative output signal will change depending on the noise components. The logic level of S F2Cff changes frequently, so in the servo control circuit, for example, when the FZC detection signal S F2C5 has the logic rHJ level for a predetermined period of time or more, this is detected as the correct FZ.
A complicated determination circuit for use as the C detection signal 5FZC is required, resulting in a problem that the overall circuit configuration becomes complicated and large, and this is still an insufficient solution.

The present invention has been made in consideration of the above points, and attempts to propose a focus control circuit that can always shift from focus search operation to focus servo operation at the optimal timing, regardless of the offset voltage that occurs in the focus error signal. It is something to do.

E Means for Solving the Problem In order to solve this problem, in the present invention, the focus control circuit 10 adds a focus bias signal V0 to the focus error signal SFE so as to optimize the reproduced RF signal. Focus error signal S□
Focus error data DTFE is a digital value.
An analog-to-digital conversion means 21 for converting focus error data DT into a predetermined period of time, and an average value calculation means 25 for calculating average values of focus error data DT and E over a predetermined period to obtain average value data DT*tvt are provided.

2 action Focus error data DTF in the state before focus pull-in! The average value data DTIE□ for a predetermined period of time is calculated, and then the focus error data DTF! By transmitting the focus zero detection signal DTrzc at the timing when DT*trz becomes equal to the average value data DT*trz, the offset voltage ■ is caused by the focus bias signal v0 added to the focus error signal SFE.

2. Embodiment G that can always shift to the focus pull-in state at an optimal timing even when a problem occurs.An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, in which parts corresponding to those in FIG. is input to the circuit 21, thereby the system control circuit 22
The timing clock CL generated by the timing control circuit 23 based on the clock signal CLK obtained from
, the focus error data DTF consisting of digital data at the timing of tN! is converted to

This focus error data DTFE is input to a phase compensation circuit 24 and an FZC detection circuit 25, each of which is a digital signal processing processor configured with a microcomputer, and which executes digital processing at the timing of a timing clock CLKatN obtained from a timing control circuit 23. .

The phase compensation circuit 24 digitally compensates the phase of the input focus error data DTrt according to the focus servo characteristics, and converts this into the focus servo data DTrt.
□ is input to the first input terminal a of the focus switching circuit 7.

Further, the FZC detection circuit 25 executes the FZC detection processing program SPI shown in FIG. FZC detection data I) T'rzc is sent to the servo control circuit 26.
Send to.

The servo control circuit 26 receives a servo control signal CNT input from the system control circuit 22 and the FZC detection circuit 2.
Based on the FZC detection data DT Fzc obtained from 5, a focus search control signal CN TF s + is created to control the focus search circuit 27,
A switching control signal CN T sw+ is generated to selectively control the input terminal of the focus switching circuit 7.

The focus search circuit 27 generates focus search data D whose value increases step by step according to a predetermined ramp function based on the focus search control signal CNTrsr.
r s and sends it to the second focus switching circuit 7.
The signal is sent to the input terminal.

The output data sent from the output terminal C of the focus switching circuit 7 is PWM (pulse width modu
lation) is input to the decoding circuit 28, for example, P
It is decoded using the WM modulation method, and the decoded signal obtained thereby is sent to the subsequent focus coil drive circuit 9 as a focus coil drive signal Sow.

In this way, the focus coil drive signal SDV is supplied to the focus coil IOA of the two-axis device 10 via the focus coil drive circuit 9, and the two-axis device IO1, that is, the objective lens, is supplied with the focus servo data D T s.
a or focus search data DTrs.

In the above configuration, for example, when a compact disc is loaded into a CD player, the system control circuit 22 sends out a servo control signal CNTS to the servo control circuit 26, and the servo control circuit 26 receives the servo control signal CNTS from the FZC detection circuit 25. Control is made to wait for input of FZC detection data DTPZC.

The system control circuit 22 also sends an FZC control signal CNTF□ to the FZC detection circuit 25 to perform an FZC detection operation. The FZC detection circuit 25 sends out the FZC detection processing program SPI (Fig. 2).
Start execution.

That is, the FZC detection circuit 25 enters the FZC detection processing program SPI, sets the value rQJ to the internal counter X in the next step SP2, and sets the value rOJ to the internal maximum value data DTMAX and minimum value data DTMIN in the subsequent step SP3. After setting and initializing, the value "64" is set in the internal counter N in the subsequent step SP4, and the process moves to the next step SP5.

In step SP5, the FZC detection circuit 25 inputs the focus error data DT and E obtained from the analog-to-digital conversion circuit 21, and compares the focus error data DTvt and maximum value data DTMAX input in the next Stella 7'SP6, The maximum value data DTMAX is updated using data with a large value, and the input focus error data DTFE and minimum value data DTs + s are compared in the next step SP7, and the minimum value is updated using data with a small value. Data DT)11.
Update 4.

Subsequently, the FZC detection circuit 25 decrements the internal counter N in step SP8, and then proceeds to the next step S.
In P9, it is determined whether the internal counter N is less than or equal to the value "0", and if a negative result is obtained here, the process returns to step SP5.
Execute steps 5P5-3P6-3P7-3P8 described above to input new focus error data DTvt, and for the focus error data DT, , maximum value data DTMAX and minimum value data DT1.11. Update processing of l is performed.

Eventually (in the case of this embodiment, the above-mentioned step SP5-
3 P 6-5 P 7-5 Processing loop of P 8 is 6
When a positive result is obtained in step SP9 (executed four times), the FZC detection circuit 25 repeats the processing loop of steps 5P5-SP6 to 5P7-3P8 described above 64 times in the next step 5PIO. Maximum value data DT□ of focus error data DTFE
After calculating the primary average value data DTRE□ expressed by the following formula, DTMAX+DT□8 DTREF+= ...... (1) using the minimum value data DTMIN and DTMIN, the next step 5 PII Move to.

In step 5PII, the FZC detection circuit 25 stores the primary average value data DTRE, obtained in step 5PIO described above, in the internal register MX, in which the value of the internal counter X is used as an argument.

Subsequently, in step 5PI2, the FZC detection circuit 25 increments the internal counter X, and then in the next step 5P13, determines whether the internal counter Returning to SP3, execute steps 5P3-SF3, the processing loop of steps 5P5-3P6-3P7-3P8 described above, and steps 5PIO-3PII-3P12, and obtain the maximum value data DTMAX among the new 64 focus error data DTFE. and the minimum value data DT□, the primary average value data DT++tr+ is stored in the internal register MX.

Further, when the FZC detection circuit 25 obtains a positive result in step 5P13, in the next step 5PI4, using the four primary average value data DTIIEF+ stored in the internal registers MO to M3 as described above, Quadratic average value data DTREF! expressed by the following formula, Σ MX ! seek.

Note that this secondary average value data DT□ is the average value of the focus error data DTRE when neither the focus search operation nor the focus servo operation is executed, and the influence of noise components is eliminated as much as possible. , ultimately represents the bias voltage V0 applied to the focus servo amplifier circuit 3.

Subsequently, in step 5P14, the FZC detection circuit 25 sends FZC detection data DTF2C indicating the start of the focus search operation to the servo control circuit 26.

As a result, the servo control circuit 26 sends out a focus search control signal CNTFSI that instructs the focus search circuit 27 to start a focus search operation, and also selects the second input terminal of the focus switching circuit 7. The switching control signal CNTS□ is sent out.

Then, the focus search circuit 27 generates focus search data DTFs, decodes it via the focus switching circuit 7 and the PWM decoding circuit 28, and sends it to the subsequent focus coil drive circuit 9. This controls the focus coil IOA of the two-axis device 10 to start a focus search operation.

Subsequently, in the next step 5P16, the FZC detection circuit 25 inputs the focus error data DTP obtained by the focus search operation, and then inputs the focus error data DTP obtained by the focus search operation.
Focus error data DT input in step 17,
However, it is determined whether or not it is equal to the secondary average value data DT*trt obtained in steps SP2 to step 5P14, that is, the bias voltage VSSO value, and if a negative result is obtained, the process returns to step 5P16 and a new The above process is repeated for the focus error data DT,i.

Eventually, the FZC detection circuit 25 obtains a positive result in step 5PI7 (that is, this indicates that the focus zero cross point of the focus error signal SFE, which is an S-curve including the bias voltage v, 3, has been detected). , in the next step 5P18, the FZC detection data DT'rz indicating the end of the focus search operation is
c to the servo control circuit 26, followed by step 5P1
At step 9, the BgFzcA* output processing program SPI is ended.

As a result, the servo control circuit 26 sends out a focus search control signal CNT F S + instructing the focus search circuit 27 to end the focus search operation, and also sends out the focus search control signal CNT F S + to the focus switching circuit 7 at its first input terminal. A switching control signal CNTsw+ is sent to select a.

In this way, the focus servo data DT obtained from the phase compensation circuit 24 is inputted to the PWM decoding circuit 28 via the focus switching circuit 7, and is decoded and sent to the following focus coil drive circuit 9, and then output to the two-axis device. The focus servo operation is started by controlling the ten focus coils IOA.

In this way, when the compact disc is loaded, the focus control circuit 20 first converts the focus error data DTrE obtained by digitizing the focus error signal SFE obtained from the focus amplification circuit 3 to mean bone value data for a predetermined period. The bias voltage ■□ given to the focus amplifier circuit 3 is determined from DT++Erz.

Next, the focus control circuit 20 executes a focus search operation by driving the focus coil 10A of the two-axis device 10 that holds the objective lens using the focus search data DT, 3, and performs a focus search operation using the S-shaped curve obtained thereby. The focus error data DTFt becomes bias voltage V
The timing at which the average value data DT and 1EFt equal to □ is detected as the focus zero cross point, and the focus search operation is ended at this timing,
Using the focus servo data DT□ obtained from the phase compensation circuit 24, the focus coil I of the two-axis device 10 is
By driving the OA, the focus servo operation is started.

According to the above configuration, the bias given to the focus amplifier circuit 3 is determined from the average value data DT□F2 for a predetermined period of the focus error data DTFE obtained by digitizing the focus error signal srt obtained from the focus amplifier circuit 3. The voltage VIIS is determined, and the timing when the focus error data D T F t formed by the S-shaped curve obtained by the focus search operation is equal to the average value data DT++tpz formed by the bias voltage □ is detected as the focus zero cross point, and at this timing After completing the focus search operation, the phase compensation circuit 2
By driving the focus coil IOA of the two-axis device 10 using the focus servo data DTsll obtained from 4 to start the focus servo operation, an offset voltage ■ occurs in the focus error signal SFE. , F, it is possible to realize a focus control circuit 20 that can always shift from a focus search operation to a focus servo operation at the correct timing.

Furthermore, according to the above configuration, when a large number of noise components occur in the focus error signal SF obtained during the focus search operation, the calculation formula described above for equation (2) is modified and the following equation is used. , secondary average value data DT,
By adding offset data I)T'orystt corresponding to the level of the noise component when obtaining ItF2, it is possible to realize a focus control circuit 20 that can effectively prevent erroneous detection of the focus zero cross point due to noise.

In the above embodiment, the average value data DTIIEF□ of the focus error data DTrt, that is, the bias voltage VIIS given to the focus servo amplifier circuit 3, was determined in the FZC detection processing program. For example, the average value of the focus error data DT□ over a predetermined period may be determined using a low-pass filter configured as a digital signal processor.

Furthermore, in the above embodiment, the focus search data D obtained from the output terminal C of the focus switching circuit 7 is
T r *or focus servo data DTsIl as P
Although WM modulation is performed and used as the focus coil drive signal Sov, instead of this, for example, the focus coil drive signal SDV may be obtained by converting it to an analog signal via a digital-to-analog conversion circuit. A similar effect can be obtained.

Furthermore, in the above-mentioned embodiments, a case has been described in which the present invention is applied to a focus control circuit that performs focus control using an astigmatism method, but the present invention is not limited to this, and can also be applied to a focus control circuit that performs other focus control. Can be widely applied.

Further, in the above-described embodiment, the present invention is applied to a focus control circuit of an optical disk device such as a CD player, but the present invention is not limited to this, and can be applied to a focus control circuit of an optical disk device such as a magneto-optical disk device, an optical tape device, etc. This is widely applicable and suitable for focus control circuits of optical recording/reproducing devices.

H Effects of the Invention As described above, according to the present invention, in the focus control circuit which adds a focus bias signal to the focus error signal so as to optimize the reproduced RF signal, the focus error signal is input before the focus is pulled into the focus control circuit. Converts the focus error signal to focus error data made up of digital values, calculates the average value data for a predetermined period, and then sends out a focus zero detection signal at the timing when the focus error data becomes equal to the average value data. By doing so, it is possible to realize a focus control circuit that can always shift to the focus pull-in state at an optimal timing regardless of the value of the focus bias signal added to the focus error signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flow chart explaining the operation of the FZC detection circuit, FIG. 3 is a block diagram showing a conventional focus control circuit, and FIG. 4 is a block diagram of the conventional focus control circuit. FIG. 3 is a signal waveform diagram for explaining the operation. ■, 20... Focus control circuit, 5.25.
...FZC detection circuit, 21...Analog-digital conversion circuit, SF! ...Focus error signal, DT, ...Focus error data, D'rBrz...Average value data, vms.
...Offset voltage.

Claims (1)

[Claims] In a focus control circuit that adds a focus bias signal to a focus error signal so as to optimize a reproduced RF signal, an analog-to-digital conversion converts the focus error signal into focus error data consisting of a digital value. and average value calculation means for calculating the average value of the focus error data over a predetermined period to obtain average value data, the average value of the focus error data over a predetermined period in a state before focus pull-in. A focus control circuit characterized in that it calculates value data and then sends out a focus zero detection signal at a timing when the focus error data becomes equal to the average value data.