JPH0289410A - Gain variable circuit - Google Patents

Abstract

PURPOSE:To suppress the fluctuation at an output DC operating point by keeping a DC bias circuit of a differential amplifier of a gain variable circuit utilizing the differential amplifier constant. CONSTITUTION:An input signal is supplied to input terminals 122, 123 of a differential amplifier comprising 1st, 2nd npn transistors(TRs) 101, 102 and 1st and 2nd resistors 7, 8, and a signal from the amplifier whose voltage amplification factor is adjusted to AV2=gmRL is outputted from an output terminal 124, where gm is the mutual conductance of the TRs 101, 102 and RL is a resistance of the resistors 7, 8. Moreover, a control voltage is inputted to input terminals 120, 121 of a differential pair comprising both and both TRs 105, 106 and resistors 109, 110 to control a collector current Ic flowing to the TRs 101, 102 thereby varying the gain of the entire amplifier. In this case, the base DC bias level of the TRs 101, 102 is made equal to each other and a collector current I13 of the TR 101 is made equal to a collector current I14 of the TR 102 thereby suppressing the fluctuation at an output DC operating point.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a variable gain circuit in an electronic circuit, and more particularly to improvement of a variable gain circuit using a differential amplifier.

(Prior Art) FIG. 2 is a block diagram showing an example of a variable gain circuit according to the prior art.

In FIG. 2, 201 to 206 are npn transistors, 207 to 210 are resistors, 211 is a constant voltage source, 212 is a constant current source, 220 to 223 are input terminals, and 224.225 are output terminals. be.

The resistance values of resistors 207 and 209 are respectively RL (Ω),
RB(Ω) and npnl-run9xp201.202
The collector currents are 2□ (A) and I22 (A), respectively.
Then, the voltage gain AV from the input terminals 222 and 223 to the output terminals 224 and 225, respectively, is! It can be expressed as

At this time, the erector currents I2□ and 2□ are input to the input terminal 22.
It changes according to the control voltage input to 0,221. That is, the voltage gain of the circuit is changed by changing the DC bias current flowing through the load using the control voltage.

(Problems to be Solved by the Invention) The conventional variable gain circuit described above has a drawback in that when changing the gain, the DC bias current flowing through the load changes, so the DC operating point changes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable gain circuit which eliminates the above disadvantages by adding a circuit to the above circuit to stabilize the DC bias voltage flowing to the load, and which is configured so that the DC operating point does not change. It is in.

(Means for Solving the Problems) A variable gain circuit according to the present invention includes first to sixth transistors, first to fourth resistors, a constant voltage source, and a constant current source, and has the following configuration. It has the following.

The first transistor has a collector connected to a constant voltage source via a first resistor, and a source connected to a first input terminal;
The emitter is connected to the emitter of the second transistor and the collector of the fifth transistor.

The second transistor has a collector connected to a constant voltage source via a second resistor, and a base connected to a second input terminal.

A connection point between the collector of the first transistor and the first resistor is connected to the output terminal and the collector of the third transistor.

A connection point between the collector of the second transistor and the second resistor is connected to the output terminal and the collector of the fourth transistor.

The third transistor has a base connected to the base of the fourth transistor and the fifth input terminal, and an emitter connected to the emitter of the fourth transistor and the collector of the sixth transistor.

The fifth transistor has a base connected to the third input terminal and an emitter connected to a constant current source via a third resistor.

The sixth transistor has a base connected to the fourth input terminal and an emitter connected to a constant current source via a fourth resistor.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a variable gain circuit according to the present invention.

In FIG. 1, 101 to 106 are the first to sixth numbers, respectively.
npf'l) transistors, 107 to 110 are the first to fourth resistors, 111 is a constant voltage source, 112 is a constant current source, 120 to 123°, 126 is an input terminal, 1
24 and 125 are output terminals, respectively.

The collector of the first npn) transistor 101 is connected to the constant voltage source 111 via the first resistor 107, its base is connected to the input terminal 122, and its emitter is connected to the second
The emitter of the npn transistor 102 and the 50th rlp
rl) is connected to the collector of the transistor 105.

The collector of the second npn) transistor 102 is connected to the constant voltage source 111 via the second resistor 108 and to the input terminal 123 of its base. first npn
A connection point between the collector of the transistor 101 and the first resistor 107 is connected to the output terminal 124 and the collector of the third NPN transistor 103.

The connection point between the collector of the second npn) transistor 102 and the second resistor 108 is the output terminal 125 and the fourth npn
n) Connected to the collector of transistor 104. 3rd npn) The base of the transistor 103 is the 4th npn
pn) connected to the base of the transistor 104 and the input terminal 126. The emitter of the third npn) transistor 103 is connected to the emitter of the fourth npn) transistor 104 and the collector of the sixth npn) transistor 106.

The base of the fifth npn) transistor 105 is the input terminal 1
20, and its emitter is connected to a constant current source 112 via a third resistor 109. 6th npn
) The base of the raster 106 is connected to an input terminal 121 and its emitter is connected to a current source 112 via a fourth resistor 110.

The operation of the variable gain circuit shown in FIG. 1 will be explained below.

1st and 2nd npn) transistors 101゜102
The signal input from the input terminal 122° 123 of the differential amplifier constituted by the first and second resistors 7.8 and 124° 125 is transmitted to the output terminal 124° 125 with a voltage gain AV! expressed by the following equation. It is given in free. Here, the resistance values of resistors 7 and 8 are RL (Ω), and the thermal voltage is VT (V).

1c is the collector current of transistors 101 and 102, g
is the mutual conductance of transistors 101 and 102.

By inputting a control voltage from the input terminals 120 and 121 to the differential pair constituted by the fifth and sixth npn) transistors 105 and 106 and the third and fourth resistors 109 and 110, the 1 and 2nd npn)
Since the collector current IC of transistors 101 and 102 can be controlled, the gain of the entire amplifier can be changed.

At this time, the first and second np forming the differential amplifier
n) transistor 101. , 102 are at the same potential, the collector current I1m of the first npn) transistor is the same as that of the second npn) transistor 10.
is equal to the collector current 114 of 2. That is, I,=I, (3) is satisfied. On the other hand, since the DC collector current Ill of the fifth npn transistor 105 is given by the sum of Il and 114, the DC collector current III of the first npn transistor 101 is given by.

Next, the third and fourth npn) transistors 103.1
04 bases are all connected to the same input terminal 26,
Since the DC bias potential is the same potential, the third npn)
Collector current 11 of transistor 103. and the fourth n
pn) The collector currents 1111 of the transistors 104 are equal in phase. In other words, 1 la = 1. (5) On the other hand, the DC collector current 112 of the sixth npn) transistor 106 is given by the sum of Ls and Its (!:O, so the collector current L of the third npn) transistor Ill
s becomes.

DC bias current II of resistor 107? is σ). If the current of the constant current source 112 is IO, then ■. = I t+ + L*), and the equations (7) and (0) are obtained.

DC bias current It flowing through resistor 107 which is a load
? is constant without being affected by the control voltage.

As mentioned above, fluctuations in the output DC operating point due to gain variation can be suppressed.

(Effects of the Invention) As described above, the present invention has the effect of suppressing fluctuations in the output DC operating point by keeping the DC bias current of the differential amplifier constant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a variable gain circuit according to the present invention. FIG. 2 is a block diagram showing an example of a variable gain circuit according to the prior art. 101-106, 201-206...npn) transistors 107-110, 207-210... resistors 120-
125, 126, 220-225...Terminal 111.2
11... Constant voltage source 112.212... Constant current source

Claims (1)

[Claims] first to sixth transistors, first to fourth resistors,
It consists of a constant voltage source and a constant current source, and the collector of the first transistor is connected to the constant voltage source via the first resistor, and the source of the first transistor is connected to the first transistor. an input terminal, and connects the emitter of the first transistor to the emitter of the second transistor and the fifth transistor.
the collector of the second transistor is connected to the constant voltage source via the second resistor, and the base of the second transistor is connected to a second input terminal. , a connection point between the collector of the first transistor and the first resistor is connected to an output terminal and the collector of the third transistor, and the collector of the second transistor and the second resistor are connected to each other. A connection point of the third transistor is connected to an output terminal and a collector of the fourth transistor, a base of the third transistor is connected to a base of the fourth transistor and a fifth input terminal, and a connection point of the third transistor is connected to the collector of the fourth transistor. The emitter of the transistor is connected to the emitter of the fourth transistor and the collector of the sixth transistor, the base of the fifth transistor is connected to the third input terminal, and the emitter of the fifth transistor is connected to the emitter of the fifth transistor. connected to the constant current source via a third resistor, and connected the base of the sixth transistor to a fourth input terminal;
A variable gain circuit characterized in that the emitter of the sixth transistor is connected to the constant current source via the fourth resistor.