JPH028758A - Delay time measuring apparatus - Google Patents

Abstract

PURPOSE: To measure the signal delay time due to a device to be tested precisely by employing a switching calibration unit giving a signal propagation delay. CONSTITUTION: A timing measuring circuit 100 mounted on a printed circuit board 130 generates various test signals and receives the output signal from a device to be tested. This signal V1 is an input stimulus signal for the device 110 to be tested and a signal V2 is generated from the device 110 upon receiving the signal V1. A circuit 100 measures propagation delay between the signals V1, V2. The propagation delay thus measured is compared with a signal propagation delay of an identical physical path having no device to be tested.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to printed circuit boards, and more particularly to an apparatus for accurately measuring time delays in signal propagation within devices on a printed circuit board.

TECHNICAL BACKGROUND OF THE INVENTION AND PROBLEMS Detecting timing errors within the 44 second range is a problem in the field of printed circuit board testing systems. A printed circuit board test system is a fully integrated set of resources used to test analog, hybrid, and digital circuits. This board test system generally performs short and open circuit testing, analog, hybrid and digital in-circuit testing, and analog, hybrid and digital in-circuit testing for devices mounted on printed circuit boards. Cluster and functional testing (
Function test). The test sequence performed by this board test system is:
To meet the operational requirements of the printed circuit board under test,
programmed into the board test system by a test engineer. The design engineer will write a test program that enables the board test system to generate a series of timed stimuli and apply these stimuli to the board under test. Electrical interconnection to the substrate under test is accomplished through a "bed of nails" interface consisting of a plurality of conductive pins pre-patterned onto the substrate testing system. This board under test is
placed on top of the nails and secured in place to enable the board testing system to apply the stimulating electrical signals to various devices and conductive paths on the circuit board under test. The board testing system also monitors pre-specified points on the board under test to detect responses to stimulus signals applied to the board under test. The timing and pattern of the output signals generated by the board under test in response to the programmed stimulus signals are compared to a set of known board responses to determine whether the board under test is operating normally. .

− is undetectable. Although these conventional board test systems can determine the proper logical interconnection and logical functionality of devices on the board under test, they cannot determine the precise timing of the operation of these various devices. is a medium speed on the order of 50 to 100 nanoseconds.
It can only be analyzed by rate. Therefore, existing board testing systems are inadequate for distinguishing between two different families of logically identical digital devices. For example, a conventional board test system has a 74A L S 74 response time of 16 nanoseconds.
It is not possible to distinguish between a D-type flip-flop device and a 74A S74 D-type flip-flop device, which has a response time of 8 tenos.

(Objective of the Invention) An object of the present invention is to provide an apparatus that can accurately measure signal delay time caused by a device under test.

SUMMARY OF THE INVENTION The problems described above are solved and a technological advance is achieved in the field by the precision measurement device for device delay timing of the present invention. The device uses a switchable calibration device that provides precisely defined signal propagation delays. This device delay timing precision measurement equipment is
This calibration device is used to measure the storage time of a test signal through a selected signal calibration path in a board testing device that includes this calibration device. A device under test on the printed circuit board is then switched into this signal calibration path, in which changes in the test signal propagation path caused by the presence of this device under test are calculated by the apparatus. If the device under test has a slightly longer signal propagation delay time, the device under test is switched to a predetermined test signal propagation path of the calibration apparatus. If the device under test has a very short test signal propagation delay time, the device under test is switched into the test signal propagation path in series with the calibration device.

In either case, this arrangement provides a precise measurement of the signal propagation delay time caused by the device under test.For devices, this equipment can be used to determine the exact time of signal propagation when the device under test is connected and unconnected. Enables delay measurements.

EMBODIMENTS OF THE INVENTION A printed circuit board test system is a fully integrated set of resources used to test analog, hybrid and digital circuits. This board test system performs short circuit and open circuit tests on devices mounted on a single printed circuit board, as well as analog,
Hybrid and digital in-circuit testing and analog, hybrid and digital cluster and functional testing are commonly performed. The test sequences executed by the board test system are programmed into the board test system by a test engineer to meet the operational requirements of the printed circuit board under test. The test engineer will write a test program that enables the board test system to generate a series of timed stimulus signals and apply these stimulus signals to the board under test. Electrical interconnection to the board under test is accomplished by a bed-of-nails interface consisting of a plurality of conductive pins pre-patterned onto the board test system.

The board under test is placed on top of the "bedded nails" and fixed in place, and the board testing system transmits the stimulating electrical signals to various devices and conductive devices on the circuit board under test. The board test system also monitors pre-specified points on the board under test to detect responses to stimulus signals applied to the board under test.

The timing and pattern of the output signals generated by the board under test in response to the programmed stimulation signals are
A set of known board responses are compared to determine whether the board under test is operating normally.

A limitation of existing board test systems is their inability to detect timing errors in the 17 second range for the board under test. Although these conventional board test systems can determine the proper logical interconnection and logical functionality of devices on the board under test, they cannot determine the precise timing of the operation of these various devices. is 50~
It can only be analyzed at medium speed rates on the order of 100 nanoseconds. For this reason, existing board test systems are inadequate to distinguish between two different families of logically identical digital devices. Accordingly, a conventional board test system can test a 74A L S74 D type flip-flop device with a response time of 16j nos and a 74A S740 type flip-flop device with a 8 nsec response time. It is impossible to distinguish.

System Description The device delay timing precision measuring device of the present invention comprises a first
It is illustrated in block diagram form in the figure.

This device performs signal propagation delay measurements regarding various devices mounted on the printed circuit board 130. A timing measurement circuit 100 in this device delay timing precision measurement device generates and outputs test signals (such as the test signal marked Vl on lead 101) and outputs test signals (such as the signal v2 on lead 115). ) functions to receive signals output by the device under test. This signal Vl
is the input 11ilI'1I to the device under test 110
11 signal. On the other hand, the signal v on the lead 115
2, the device under test 110 inputs the input ll1lI signal V.
is the output signal generated by the device under test 110 when it receives t. Timing measurement circuit lOO
precisely measures the propagation delay between the generation of test signal v1 by this circuit 100 and the return of output signal V2 from the device under test on lead 115. This measured propagation delay time is compared to the test signal propagation delay time through the same physical path without the device under test. The difference between these two test signal propagation delay times is the signal delay caused by the device under test 110.

In operation, controller 122 sends control signals to test vector memo IJ 120 over bus 121. Control signals from controller 122 serve to address a particular test vector located in test vector memory 120, which test vector is sent to timing measurement circuit 100 via bus 119 in test vector memory 120. It is downloaded from 120. This test vector is expected to be received from the device under test 110 as a result of human stimulus signals, signal timing information, and input stimulus signals applied to the device under test 110 that are required to operate the device under test 110. A set of programmed signals representing the identification of output signals. (Typically, a test vector is a digital word with so-called "input bits" and "output bits." Typically, certain bits within this word are input bits and the remaining bits are output bits.) where the human bits of a given test vector are applied to the device under test in a circuit board tester,
The output bits of this vector define the expected output of the device under test in response to the input bits. During testing, the actual output of the device under test in response to the input bits of the test vector is compared to the expected output bits of the test vector. The matching between the actual output and the expected output means that the device under test is working as expected with respect to the test vector. ) The timing measurement circuit 100, in response to the test vectors received from the test vector memo 1J 120, outputs a series of test signals, i.e., input stimuli, on a plurality of leads (e.g., 101) shown in FIG. A signal is generated to a number of drivers (eg, 102). Each driver converts the test signal output by timing measurement circuit 100 into a corresponding drive signal that is output to board under test 130 (eg, through lead 103).

Circuit board interconnect device under test 110 typically includes a printed circuit board 1
This is a device attached to 30. In a board test system, the various devices and interconnections on the printed circuit board under test 130 are accessed by a matrix of electrical interconnects commonly referred to as the "bed of nails" 124. of·
The conductor of Nails 124 is conductor 105.107, lO9
It is represented in FIG. 1 as a box connected to and 111. This “Bed of Nails 124”
consists of a pattern of conductive vias projecting from the surface of a test bed in the shape of a printed circuit board 130 to be tested. Each of these conductive vias can be used to contact a conductive path or terminal of one of the devices mounted on printed circuit board 130. Each of the conductive pins in the bed of nails 124 connects the bed of nails 124 to the switch matrix 10.
4, which serve to interconnect a plurality of conductors 123. This switch matrix 104 connects various driver and receiver circuits.
An electrical interconnect device that serves to connect to the conductive vias on the bed of nails 124. Therefore, the switch matrix 104 is connected to the test vector memory 1
20 into a series of electrical connections that interconnect each driver of the plurality of drivers (e.g., 102) and conductors on the printed circuit board 130 (e.g., 109). and connect receivers (e.g., 114) to conductors (e.g., 111) on printed circuit board 130.
) to interconnect. Accordingly, the drive signal output by driver 102 on conductor 103 can be switched by switch matrix 104 to conductor 105 and conductor 109 illustrated in FIG. Riichido 1
The output signal generated by the device under test in response to the drive signal output by driver 102 on 03 is:
Conductor 111 is connected to switch matrix 104 which interconnects these output signals to conductor 113 of receiver 114.
transmitted by. (This switch matrix 1
04 can also interconnect conductor 107 to conductor 113) Timing Measurement Circuit Timing measurement circuit 100 is a phase-locked loop!
2513 and dividers 126-128 are used to precisely measure the time interval between generating the test signal and receiving the output signal from the device under test 110. An interval reference clock signal is applied to a lead 134 to a divider 126, which is configurable by software within the controller 122 to divide the clock signal into smaller intervals. The resulting clock signal is applied across lead 135 to phase-locked loop 125 with associated feedback divider circuitry 128 to generate a frequency stable reference clock signal for the test to be performed. Divider 127 acts as a range divider and outputs a clock signal on lead 137. Thus, a clock signal can be set on the software board 137 within the controller 122.

Therefore, software within controller 122 adjusts the clock time through dividers 126-128 to increase or decrease the time between the generation of the test signal (i.e., the generation of vl) and the receiver scan (i.e., the scan for v2). Intervals can be set.

Timing measurement circuit 100 includes a receiver 1 that monitors the output of a device under test in response to a given test vector.
Scan 14. Compare with the internal part of the timing measurement circuit. This scanning is performed using the output signal v2 from the device under test.
using a logic gate (not shown) and a clock signal output on lead 137 to toggle a "match" bit in memory if a match occurs between the test vector and the expected output portion of the test vector. This is achieved by

As mentioned above, controller 122 can program the time interval between generation of test signal Vt and scanning of receiver 114 for the signal. By regularly varying the time interval in software (as discussed below) and simultaneously monitoring the "match" bit, the controller 12
2 can determine the device delay time and output the device delay time through lead 117 to display 118 to provide test data in a human readable form.

Timing calibration Precise test signal propagation delay timing of the device under test,
To provide measurements, a calibration device 106 is used to obtain the required accuracy. This is accomplished by establishing a calibration signal path interconnecting timing measurement circuit 100 and driver 102 to calibration device 106 and receiver 114 to obtain a precise determination of the propagation time through this path. Calibration device 106 is any device that has a precisely defined and constant test signal propagation delay time.

Therefore, the timing measurement circuit 100
Upon generating the test signal Vt on the lead 103, the driver 102 converts this signal v1 into a drive signal applied to the lead 103 and applies this drive signal to the calibration device 106. This drive signal is delayed by a precisely defined amount of time by a calibration device 106 before appearing on conductor 107, which is connected to conductor 113 by a switch matrix 104 to direct this output signal to a circuit 114. Apply. The compensated output signal from the calibration device 106 is converted by a return signal v2 receiver 114 that is applied to the timing measurement circuit 100 via path 115. The transit or propagation time of this signal from conductor +01 to conductor 115 through the calibration signal path described above is measured by timing measurement circuit 100 to obtain an indication of the inherent delay in this signal path.

To ensure the accuracy of this calculation, the calibration tests described above are performed multiple times by timing measurement circuit 100 to obtain an accurate determination of the propagation delay of this signal path. In order to measure the test signal propagation delay of the device under test 110, the IJ hook 04 can replace this device under test 110 with the calibration device 106 in the calibration signal path described above, or the device under test 110 can be 11
0 can also be inserted in series with the calibration device 106 in this calibration signal path. If the device under test 110 has only a significant amount of time to test the device under test 110 during the calibration signal path, connecting the device under test 110 in series with the calibration apparatus 106 can further improve Get accurate measurements. In the former case, switch matrix 104 interconnects conductors 103, 109 and conductors IH, 111 to replace device under test 110 with calibration apparatus 106. In the latter example, when device under test 110 is connected in series with calibration apparatus 106, switch matrix 104 connects conductors 103.
105 and conductor 105.107 and conductor 109 and conductor Ill
, 113 are interconnected. This series interconnection is
A device under test 110 is added to the calibration signal path described above. In either case, timing measurement circuit 100 can calculate the difference in propagation delay caused by the insertion of the device under test into the calibration signal path.

Test Signal FIG. 2 shows signal waveforms and timing diagrams to illustrate the propagation delay of the aforementioned test signal. The first signal waveform is labeled vl and represents a typical waveform seen on conductor 103. This signal begins at a level identified as 0 and opens a transition to a level identified as 1 at time t0. Since driver 102 has a fixed response time to the test signal force on lead 101, this response time is at time t. and time t
, is illustrated in Figure 2 as the difference between . this is,
This is the driver setup delay time, or signal propagation delay time, which is the time required for driver 102 to transition between a 0 level and a 1 level. Added to this setup delay time is the signal delay propagation time caused by conductor 103, switch matrix 104, and conductor 105. This is illustrated diagrammatically in FIG. 2 by the time difference t, minus tl. The following signal propagation delay times illustrated in FIG.
This is the signal propagation delay time of the calibration device 106.

This is illustrated diagrammatically in FIG. 2 by the transition in the signal wave, shape VD, during the time interval from t2 to t. Additionally, conductor 107 and switch matrix 1
04 and conductor 113, to E.

There is a return path signal delay time reduced by . Receiver 1
14 adds its own set-up time delay, illustrated in FIG. 2, by the time difference ts minus t4, which is the time delay that receiver 114 responds to the signal received from calibration device 106 at time t.

The waveform labeled v2 transitions from level 0 at time t to level l at time t.

Time t. The overall signal propagation delay time, shown diagrammatically in FIG. 2 as the time delay from It is possible. This program is the manual test signal waveform generation instructions and identification of driver-to-receiver interconnections within the switch matrix 104. That is,
Assign In to pin 1assign
Out to pin 2pcf order
is In, 0utevents every 25
0n interval timing set def
ault Time is 4 eventsdrive
e vector at event 0receiv
e vector at event 1end ti
Calibration of signal propagation delay is obtained by measuring the signal propagation delay around the loop as described above.The program below performs this measurement. A typical test routine is for I = 170 to 1805tep O,
IJ = 1 1e-9 events every J 1ntervalex
ecute test if debug failed=OthenCal v
alue=[ goto End cal end if ext l If the device under test 110 to be tested has a delay of 7 seconds and 3 seconds, a second program is used to evaluate the signal propagation delay time of this device under test 110. In this case, this device under test 110 is a switch/device as described above.
Calibration device 106 is replaced by matrix 104 . This program remeasures the test signal propagation time through the calibration signal path with the device under test 110 replacing the calibration apparatus 106, and then measures the signal propagation delay caused by the insertion of the device under test 110 into the calibration signal path. Calculate. This program is as follows.

for I = 190 to 2105tep O,
IJ= [Kyo1e-9 events every J 1ntervalex
ecute test if debugfailed=o thenTemp
=1 goto End measure end 1f next 1 and measure:! Delay value = (Temp-Cal value
ue)+50if Delay value<70o
r Delay value>80 thenrepo
rt Delay 1ine UXX out of
tolerance end if In this program, the calibrated signal propagation delay time is subtracted from the remeasured signal propagation delay time and the nominal value of the signal propagation delay produced by the calibration device 106 is added to this value to determine the tolerance of the device under test 110. Obtain an accurate display value of this signal propagation delay time. I would like to draw your attention to this.

If the device under test 110 has only a very small signal propagation delay time, the device 110 is a switch.
When serially inserted into the calibration device 106 by the matrix 104, the above program is modified by subtracting the calibrated signal propagation delay time from the remeasured signal propagation delay time. Using this method, a precise measurement of the signal propagation delay time of the device under test 110 can be obtained by the timing measurement circuit 100. This calculated value may be displayed in human readable form on display 118 for a tester by the board testing system.

(Effects of the Invention) As described above, by using the present invention, the signal delay time of a device under test can be precisely measured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a device delay timing precision measuring device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining the waveforms and timings of various signals in the measuring device. 100: Timing measurement circuit 102.132: Driver 104: Switch matrix 106: Calibration device 114.134: Receiver 118: Display 120: Test vector memory 122: Controller 124: Bed of nails

Claims (1)

[Scope of Claims] Means for measuring the propagation time of a test signal through a calibration signal path; means for switching and connecting a device under test to the calibration signal path; and inserting the device under test into the calibration signal path. means for determining a propagation time change of the test signal caused by the change in propagation time of the test signal;