JPH0286239A - Serial controller - Google Patents

Abstract

PURPOSE:To continue communication at any time except two disconnected signal lines between same nodes by providing a signal switching means sending a disconnected line frame signal to two signal lines with a node of the post-stage when both two signal lines are disconnected. CONSTITUTION:Nodes 10-1-10-n and a main controller 100 are connected in series via two loops I, II and no priority is placed on the loops I, II. Then the main controller 100 collects detection signals from sensor groups 1-1-1-n connecting to the nodes 10-1-10-n and sends a driving data to actuator groups 2-1-2-n connecting to the nodes 10-1-10-n sequentially. Thus, a signal is sent by using all loops between nodes without no disconnected line and the system- down is not simply taken place and the durability and reliability of the disconnected line of the system are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial control device suitable for use in a centralized control system for presses, machine tools, unmanned conveyance devices, and the like.

(Prior art) When centrally managing presses, machine tools, construction equipment, ships, air ports, unmanned conveyance equipment, unmanned C warehouses, etc., a large number of sensors (Limitsu I switch, (operation buttons, encoders, etc.) and numerous actuators (valves, relays, lamps, etc.) that control the status of each part of the device.
Is required. For example, when considering a press, the number of sensors and actuators is as high as 3,000 or more, and in other devices, the number may be even larger.

Conventionally, a centralized management system for centrally managing this type of device connects the many sensors and actuators mentioned above to a main controller, collects the outputs of the many sensors through the main controller, and also collects the outputs from the main controller. The controller is configured to control a large number of actuators using signals from the controller.

In the case of such conventional centralized control systems, as the number of sensors and actuators increases, the number of wires connecting the main controller and the sensors and actuators also increases, and the configuration of the input/output section of the main controller also becomes very large. It becomes complicated.

Therefore, multiple nodes are connected in series, one or more sensors and actuators are connected to each node, and these nodes are connected in a loop via a main controller, and each node receives a signal from this main controller. A configuration is being considered in which a CD is controlled. 4′? In the case of an I configuration, basically the main controller only needs to have a signal input line and an output line, and each node also connects the signal input line and output line.
Wiring man-hours can be significantly reduced.

However, if the above nodes are connected in series,
The problem is how to ensure the simultaneity d3 of collecting the outputs of each sensor and the simultaneity of &IJ IM of each actuator. For example, assign the address Z11 to each node,
In a configuration in which each node is controlled based on this address, a delay due to this address processing becomes a problem, and satisfactory simultaneity in collecting the output of each sensor and controlling each actuator becomes a problem. It cannot be guaranteed.

Therefore, the invention name, etc., was created by abandoning the idea of assigning an address to each node while having a configuration in which nodes are connected in series, and identifying each node by the order of connection, thereby eliminating the need for addresses 98 raccoons. The present invention provides a serial control device that can eliminate time delays associated with address processing, and can greatly simplify the configuration of nodes.

According to this device, each node sequentially adds the signal from Sen→) to the signal from the previous node based on a predetermined rule, and also adds a predetermined signal from the signal from the previous node based on a predetermined rule. [Go back to the configuration of sequentially deleting and outputting to the actuator. In this case, each node does not need an address at all, and since address processing is not required, the time delay caused by each node (only for timing alignment) is very small, and the node configuration is also very simple. It will be easy.

By the way, in this series control device, one signal line (loop) connecting each node is usually considered to be sufficient, but as a backup measure to prevent the system from going down in the event of a loop break, we added another loop. There are many requests to create a double loop.

This 2ff! Regarding loops, C, the conventional general idea is to provide a primary loop and a secondary loop as shown in Figure 22, and then use the primary loop and switch to the secondary loop if the primary loop breaks. It is.

(Problem to be solved by the invention) However, such a switching method from primary to secondary [.

As shown in Figure 22, J3 is located somewhere in the forward loop.
There is a problem that if a disconnection occurs at one point in the main and sub-loop, the system will go down.

This invention was made in view of the above circumstances, and is designed to reduce communication to 1 when both loops are disconnected between the same nodes.
The present invention aims to provide a series control 20 device that improves the reliability of the system by making it possible to continue the system.

(Means for Solving the Problem) Therefore, in the present invention, the plurality of nodes and the main controller are connected in series with two No. first and second disconnection detection means for detecting a disconnection of the signal line between the two signal lines, respectively; Based on the detection outputs of the frame signal generation means and the first and second detection means, if the disconnection is not R1, the data frame signal received from the previous node via the two signal lines is detected. If one of the two signal lines is disconnected, the data frame signal from the fi line on the non-disconnected side is sent to the subsequent node. It is sent to two signal lines between
1) When both of the two signal lines are disconnected, the generated
The present invention includes a signal switching means for transmitting and switching the disconnected frame signal to two signal lines between the node and the subsequent node.

(effect) It takes! If only one signal line is broken, the signal from the signal line of Tsukuda j, which is not broken, is sent to the two signal lines with the subsequent node. therefore,
Two signal lines between the same nodes are l! Communication can be interrupted except when using the Ii line.

[Embodiments] The present invention will be described below with reference to embodiments shown in the accompanying drawings.

FIG. 1 shows an embodiment of a series control device according to the present invention. This 'y' embodiment is applied to, for example, a centralized control system for a press. In this case, the main controller 100 is provided in the controller section of the press,
Sensor groups 1-1 to 1-n correspond to sensors that detect the state of each part of the press, and actuator groups 2-1 to 2-n correspond to various actuators that drive each part of the press.

Sensor group 1-1 and actuator group 2-1 are connected to node 10-1, sensor 8Y1-2 and actuator group 2-2 are connected to node 10-2, sensor group 1-3 and actuator group 2 -3 is node 10-3
and the actuator tJ2-n are connected to the node 10-n. Further, the nodes 10-1 to 10-n and the main controller 100 are connected in series through two loops, loop 1 and loop (2).

These loops 1. II does not have a priority order of DJ or DJ.

In this configuration, the main controller ioo controls the sensor group 1-1 connected to each node 10-1 to 10-n.
Collect the detection signals of ~1−“), and each node 1
Acti l connected to 0-1~10-n Saturday-Evening 8 yen 2-
The driving signals 1" to 2-n are sequentially sent out.

In this case, in this system, data is sent and received using the ``fi Q'' of the four fly hazes shown in Fig. 3. In other words, a star [- code ST is placed at the beginning, After this star 1-code ST, 7゛-
The f-evening edition data OL that reduces the column length L (number of bits) of data (DATA>) is placed, and after this, input data (data from the sensor group) and output data (data to the actuator group) are placed around 1. Input/output data (DATA) is arranged.In this embodiment, input data is always inserted from U'lt of the data string length data DL, and output data is taken out from the last one of the data frame part DATA. In this case, a data length variable method is used in which there are no empty data bits 1 to 1, and therefore the data frame portion DA
Immediately after the frame signal is sent from the main controller 100, the TA receives input data [)in.

[) 1n-1... are not included, and the signal is transmitted to each node 10 to 1. There is no output data when input to the main controller 100 via 10-n. A stop code SP is placed at the beginning of the data frame DATΔ, followed by a CRC code (CRC code). This is the code for.

An error code ERR indicating various errors is arranged after the CRC code. This error code ERR can represent various error contents depending on the code contents. For example, one of them is the difference between the data string length indicated by the data string length data DL and the actual data string length. A possible solution would be to check whether the comparison results match or not, and to indicate when there is a discrepancy. Note that this error code ERR does not include a disconnection error.

The loop ■disconnection code BRK1 is to indicate the disconnection of the loop ■ and the position of the disconnection, and the loop ■disconnection code B
RK2 is for indicating the breakage of the loop ■ and its breakage position. These codes BRK1 and BRK2 are all "○" when no breakage occurs, and when a breakage occurs, the code indicates the side where the breakage occurred. Data for indicating the occurrence and position of the wire breakage is written in the code area corresponding to the loop. However, these disconnection codes BRKI and BRK2 are caused by the two lube 5s between the relevant node and the previous node.
The data indicating the occurrence and location of the disconnection is written by the node that detected the disconnection only when only one of the loops in ■ is 1llia, and loops ■ and ■ are disconnected at the same node H]. At this time, a disconnection frame signal Z having a format different from that of the data frame signal shown in FIG. 3 is transmitted. As shown in FIG. 6, this disconnection frame signal Z is composed of a predetermined code BRKW representing a disconnection in both loops and a disconnection position data section BWD for indicating the position of the disconnection.

Each node 10-1. FIG. 4 and FIG. 5 show the manner of data exchange in steps 10-n to 10-n.

FIG. 4 shows the input/output of a data frame signal regarding a node 10 equipped with one actuator 2, so that the last bit of the data frame portion of the input data frame signal is handled within the node 10. The extracted data of 1 bit 1~ is applied to the actuator 2 of the node 10 concerned. Further, the node 10 converts the data string length data DL into data string length data DL corresponding to the data string length (4 in this case) of the remaining data after the last data is extracted, and then converts this frame signal into data string length data DL. Output.

Since FIG. 5 shows the input/output of data frame signals related to the node 10 equipped with one sensor 1, in this case, in the node 10, the sensor 1 is placed at the beginning of the data frame portion of the input frame signal. Detection signal (in this case 1″
) and converts the data string length data DL into data string length data corresponding to the data string length increased by the insertion of the sensor detection signal, and then outputs this frame signal.

FIG. 2 shows the node 10-1 shown in FIG. This shows an example of 1) 1' fine configuration of ~10-n, where each node 10-1~1
Each 0-port consists of the same configuration.

In this embodiment, data transmission between each node 10 is performed using CNi.
This is done using a coded mark inversion (l) code. This is done in order to minimize transmission errors due to noise, etc. that occur during the transmission process, and also to regenerate the clock signal by each node.
This is to enable extraction). Therefore, in this case, there is no need to provide each node 10 with a clock oscillator.

Now, in FIG. 2, each node 10 has two loops 1. It is connected and node 1o
Inside are these two loops 1. The 2m configuration corresponds to I[. That is, in FIG. 2, the two-width components, the receiving circuit 20° 20', and the T-ri processing circuit 25
．． 25', transmission circuit 30, 30', 42g input detection circuit 35.35'1 new 1 gland detection circuit 40. /l○′
, disconnection code detection circuit 45.45', 10i operation auxiliary circuit 50.50'↑jF other logic 1~55.56
have exactly the same configuration and perform the same specialized operations. In the structure shown in Fig. 2, the sensor shown in Fig. 1 is used. The configuration for data input/output with AY 1 , J3 and actuator group 2 is omitted.

The receiving circuits 20 and 20' receive the frame signal from the previous stage node, and convert the received signal, that is, the signal modulated by the CMI signal, into a normal NRZ (Non Return 2 ero) code corresponding to 1.J, rOJ. The receiving circuits 20 and 20' also regenerate the clock signal used at this node from the input signal modulated into the CMI code.

The detection signal J3 of the sensor group (not shown) connected to this node 10 and the outputs of the receiving circuits 20 and 20' are input to the data processing circuits 25 and 25', respectively. 25' detects the start code ST in the input frame signal from the previous node;
Detection of stop code SP, detection of error ERR, reading of data string length data DL, counting of actual data length, comparison of actual data count value and data string length data DL, data added to actuator group (not shown) (see Figure 4), insertion of the detection signal of the sensor (not shown) into the data string (see Figure 5), error code ERR
Perform various processing such as adding . Since the details of these processes are not directly related to the gist of the present application, further explanation will be omitted.

d et al., the data processing circuits 25 and 25' perform the following processing regarding disconnection processing. That is, loop I in the data frame signal shown in FIG. 3, [breakage code BRK1. As shown in FIG. 9, BRK2 includes a wire breakage flag bit BF1.8F2 that indicates the presence or absence of a wire breakage, and a wire breakage position data section BD1.8F2 that indicates the location of the wire breakage.
802, the main controller 100
As mentioned above, these BRKl
, [In the 3RK2 code, all the pins are always rOJ. However, if a disconnection occurs, the data processing circuit 25.25' will be replaced by a disconnection detection circuit 40.40, which will be described later.
' In response to the disconnection detection output S2゜$1 of BRK2. B.R.
Disconnection flag in K1 code pitch hBF2. BF1 is “1”
”.

This flag processing is performed by the data processing circuit 25.25' at the node immediately after the loop position where the disconnection occurred, and by the data processing circuit 25.25' at the node at the subsequent stage.
Then, the disconnection flag bit rlJ in the BRK1°BRK2 code is detected, and the detection signals J and J' are input to both the +1 derivation auxiliary circuits 50 and 50'.

That is, in the data processing circuits 25 and 25' of each node, regarding the wire breakage processing, the following steps are performed: "1", detection signal J based on rOJ determination,
It has a function to execute the output processing of J'.

The switching circuit SW selects the outputs y and y of the data processing circuit 25' connected to the loop (2), the output X1 of the data processing circuit 25 connected to the loop (2) based on the output 31.82 of the gl'i line detection circuit 40.40' Disconnection frame (, 2 outputs A by selectively switching the 3 outputs Z of the ffi generator 60
, [3], and the two outputs are sent to the transmitting circuit 30.30' via the disjunctive OR group 1-55.56.
Add to.

The transmitter circuit 30, 30' transmits the applied signal to CMl (
, ¥, and outputs the modulated signal to the next node via each loop (2) and (2).

Next, a signal input detection circuit 35.35', a disconnection detection circuit 40.40', a disconnection code detection circuit 45.45',
+1 calculation auxiliary circuit 50.50' configuration and switching circuit S
The switching operation of W will be explained below.

The main controller 100 shown in FIG. 1 sends out a data frame signal in the format shown in FIG. 3 at a predetermined period T as shown in FIG. signal is r1
When no input is made to the node for a period of nT (n≧2, e.g. n-2) or more, this I! It is designed to detect i-line. In other words, the No. 3 input detection circuits 35 and 35' monitor the outputs of the receiving circuits 20 and 20', respectively, and detect star 1 to code ST in the data frame signal shown in FIG. Detect the line codes BRKW at both loops in the disconnection frame signal shown, and read these codes S.
As soon as T and BRKW are detected, reset signals RT and R are activated.
Output T'.

Specifically, the fX-ray detection circuit 40.40' has a timer configuration in which the above-mentioned period 0 is set as a timer, and its time value is sent by the reset signal RT from the signal input detection circuit 35.35'.
, RT' is added to the initial value.

Therefore, r! The f1s detection circuits 40.40' are normally reset each time a data frame signal is input, but if more than n frames are missing during the timer setting, the signal input detection circuits 35.40' are reset during this period. Since the set signals 35' and 35' are not inputted, the timer overflows, and the disconnection detection circuits 40 and 40' output disconnection detection signals Sl and S2. That is, when a frame dropout occurs that is n times or more the transmission cycle T of the data frame signal, the disconnection detection circuits 40 and 40' detect this as a disconnection, and send the detection signals 81 and 82 to the switching circuit SW.
and is output to the disconnection frame signal generator 60.

Furthermore, the output 8 of these Fli line detection circuits 40 and 40'
1.82 is input in reverse correspondence to the data processing circuit 25, 25', and in the data processing circuit 25 to which the disconnection detection @S2 is input, the loop ■ disconnection code BRK2 in the data frame signal in Fig. 3 is input. The new line flag bit BF2 in the data frame signal is set to "1", and the data processing circuit 25' to which the detection signal S1 is input sets the disconnection flag bit [3fM] of the BRKI code in the data frame signal to "1".

The disconnection frame signal generator 60 is connected to the disconnection detection circuit 40.
. , the output of the circuit 60 is connected to a switching circuit SW. Incidentally, the wire breakage position data part BWD in the wire breakage frame signal Z is all "0" when it is sent from the wire breakage frame signal @ generator 60.

The disconnection code detection circuit 45.45' is connected to the reception circuit 20.45'.
20' from the previous node based on the output of r! Check whether or not a frame signal has been received from each loop,■
The disconnection frame signal Z
When the disconnection code BRKW inside is detected, the detection signals 31 and 82 of the disconnection detection circuits 40 and 40' are output by outputting the detection signals 3e and 3e' to the disconnection detection circuits 40 and 40'.
Clear. In this case, the disconnection detection circuit 40.40'
When it detects a disconnection, its output, 81.82, is rHJ
to "LJ", and the above detection signal Se,
Se′ is l! When input to the li line detection circuit 40.40', the signal S1. S2 is forced back to r)-IJ.

Detection of the above 1fil gland code detection circuit 45 and 45'
r S c , S e ' are +1 sieve auxiliary circuit 5
0°50 + is also input.

FIG. 10 shows an example of the internal configuration of the +1 law auxiliary circuit 50, in which the OR gate 51.11 L It detection circuit 52
, an AND gate 53.1 bit delay circuit 5/l, and an SR flip-flop 57, and these circuits and an exclusive OR gate 55 shown in FIG. 2 constitute a +1 addition circuit, respectively. 'Jd3, + I N, Q
The sleeve [1/J circuit 50' also has the same structure as shown in FIG. 10.

The OR game h51 contains the detection signal Sc of the disconnection code detection circuit 45 and the detection signal J of the data processing circuit 25, 25'.
, J' are input, and the OR output of these is input to the second terminal S of the SR flip-flop 57.

The "L" detection circuit is composed of, for example, an inverter, to which the output of the receiver circuit 20 is input, and is configured to perform logic inversion of the input signal.
This circuit detects u, and its output is connected to one input terminal of the AND gate 53. and gate 5
Q of the SR flip-flop 57 is connected to the other input terminal of 3.
The output G is fed back.

The 1-bit delay circuit 54 converts the output of the AND gate 53 to 1
With a bit delay, the output is transferred to the SR flip-flop 5.
Input to reset terminal R of 7.

The SR flip-flop 57 is a normal Sesotripip 1-
The output G of the flip-flop is input to the exclusive OR gate 55 in FIG.

In the +1 power-off auxiliary circuit 50 having such a configuration, the disconnection code detection circuit 4 is connected to the terminal S of the cell 1 of the SR flip-flop 57.
5 and the detection signals @J and Jl of the data processing circuits 25 and 25' are inputted thereto, and the 1-bit delayed output of the L detection circuit 52 is inputted to its reset terminal R. Therefore, when the disconnection frame signal Z is input to the node, the output G of the SR flip-flop 57 becomes the 11th
As shown in Figure (a), it rises at the same time as the detection of both loop breakage codes BRKW, and the position data B
It is held at "l" until the first rOJ during WD. Furthermore, when a data frame signal with the disconnection flag pin hBF1 or BF2 set to "1" is input to the node, the output G of the SR flip-flop 57 is as shown in FIGS. As such, data processing circuit 2
5 of the disconnection flag bit (in this case B “1”)
” rises at the same time as detection J or J', and rHJ until the first rOJ in the disconnection position data BD1 or 13D2.
is maintained.

Figure 8 (shows the circuit configuration of the switching circuit SW, 10
The signal input from the disconnection detection circuit 40, 40', which is composed of gates 71 to 80, is
As mentioned above, +iff becomes rLJ when a disconnection is detected.In other words, the switching circuit 'f6
SW has three inputs (
Select Z 'r X, '7, 2 and output 2 outputs A, B
The output is sent to .

Exclusive OR goo h55.56, respectively, cut? 3
Output A, B of circuit SW and +1 calculation auxiliary circuit 50.50'
By taking the exclusive OR with the outputs G and G',
The disconnection position data part BWD in the disconnection frame signal Z input via the switching circuit SW is incremented by +1 as shown in FIG. 11(q), and the BR in the data frame signal is
Disconnection position data section BD for KI code and BRK2 code
1°BD2 is added by +1 as shown in FIG. 12 (9).

Hereinafter, before explaining the overall operation, the switching operation of each switching circuit SW, etc. will be explained for various disconnection cases as shown in time chart t□-l'' in FIG.

・T1. T5 T1 shown in FIG. T5 brightness indicates the state of the node where no disconnection has occurred between the node and the preceding node, and is the output S1. of the disconnection detection circuit 40°40'.
S2 is both r l-I J and d3, switching circuit S
The output X of the data processing circuit 25 on the loop I side is selected as the output on the loop 1 side of W, and the output B of the loop ■ side of the disconnection 8 circuit SW is selected as the output Output y is selected.

At each node 10-1, 10-2...
l! between the relevant node and the previous node. When the I'i line is not connected, the transmitting circuit 30 on the loop ■ side selects the signal from the receiver (H circuit 20 and data processing circuit 25) on the loop ■ side, and the transmitting circuit 30' on the loop ■ side Signal 8 from the receiving circuit 20' and data processing circuit 25' on the loop ■ side
select.

・T2 During this period, a stone line is generated on the loop I side between the relevant node and the preceding node), and the signal 81 becomes "L" and the signal S2 becomes "F("). , the output J]y of the 1-data processing circuit 25' on the Rouge ■ side is output to B to the outputs of both OR gates 79 and 80 of the switching circuit SW. If loop I is a line, and loop ■ is normal; /JJ>, in this case, the disconnection detection signal 81 of "L" is input from the disconnection detection circuit 40 on the loop 1 side to the f-event processing circuit 25' on the loop ■ side. Therefore, the data processing circuit 25' is shown in FIGS. 3 and 9!
Set wire breakage flag bit BF1 of line code BRK1 to "1". In this case, the wire breakage position data BD11 and all rOJ in the loop (1) wire breakage code BRKl are output as they are.

・T3 In this period, contrary to the above period T2, a disconnection occurs on the loop ■ side between the node and the previous node, and the signal 82 becomes Ill and the signal S1 becomes "11", and the switching is performed. The output X of the data processing circuit 25 on the Louvue side is output to the outputs A and B of both OR gates 7980 of the circuit SW. In other words, if the loop ■ is broken between the relevant node and the 1ffr stage node, and the loop ■ is normal, the two loops ■ and ■ between the 7th stage node and the subsequent node have a positive;ilt loop. The first side will be sent out. In this case, the data 98 luck circuit 25 on the loop I side has the 11 data on the loop ■ side.
11i wire detection circuit 40' to "shi" disconnection detection signal S
2 is input, the data processing circuit 25 processes the loop ■ in the data frame signal shown in FIGS. 3 and 9.
Set wire breakage flag bit BF2 of wire breakage code BRK2 to “1”
Make it. In addition, in this case, the loop ■I! li8 code BR
The wire breakage position data BD2 in K2 is outputted as all "0"s.

・Work A During this period, a disconnection has occurred in both loops I and ■ between the relevant node and the previous stage node, and both signals S1 and S2 become rLJ, and both OR gates of switching circuit SW 79.80 Output A.

The disconnection frame signal QZ from the disconnection frame signal generator 60 shown in FIG. 6 is output to the loop 1. A disconnection frame signal Z is sent to a subsequent node via n.

Next, as shown in FIG.
Loop I between 0 and node 10-1, and node 1
The overall operation of the system when a disconnection occurs in loop 2 between node 0-2 and node 10-3 will be described with reference to FIG.

In this case, the node 10-1 corresponds to the node in the T2 period in FIG. 13, and the data processing circuit 25' on the loop ■ side of the node 10-1 receives the main controller data from the loop ■ which is not disconnected!・The frame signal from the row 5100 (see FIG. 15(a)) is processed as described above (data insertion, extraction, etc.), and the disconnection detection circuit 4 on the loop I side is roughly processed.
In response to the "L" input of the disconnection detection signal S1 from 0, the loop II line flag pin l-B in data frame No. 43
Set F1 to "1" as shown in FIG. 15 fb). In this case, the output y of the data processing circuit 25' on the loop (2) side is selected as the outputs A and B of the cut-off tJ circuit SW, so the output y of the data processing circuit 25' on the loop (2) side is selected as the output y of the data processing circuit 25' on the loop (2) side. 15th via Ilf
As shown in Figure (b), a data frame signal red including RK1 and BRK2 codes is sent out.

In the data processing circuits 25 and 25' of the node 10-2, loops 1. The data frame signal received via I[ is subjected to predetermined processing related to data input/output, etc., and furthermore, the disconnection flag bit BF1 in the loop I Ji line code BRKI is detected as "1", and the +1 calculation auxiliary circuit Detection signals J and J' are output at 50 and 50', respectively. Therefore, +1 auxiliary circuit 50.50'
operate as shown in FIGS. 12(a) to ([), respectively, and the outputs G and G' are exclusive OR game
.

Wrg in BRK1 code by 56! Location data B
A signal for adding +1 to D1 is output.

On the other hand, since no disconnection has occurred at this node 10-2, the state of the switching circuit SW corresponds to the period Tl, 5 in FIG. are input to the transmitting circuit 30.30' via exclusive OR gates 1-55 and 56, respectively, and the transmitting circuit 30.
30' to loops I and II. In addition,
By passing through the exclusive OR games h55 and 56, the disconnection position data BD1 of the loop III line code BRK1 in the data frame signal of each loop I is added by +1 and becomes "100. ...O" and
It is output to the next stage node 10-3.

In the node 10-3, a break has occurred in the loop ■, so the node 10-3 in this case corresponds to the node in the T3 period in FIG. 13, and the loop ■ side of the node 10-3 In the data processing circuit 25, the data frame signal received from the unbroken loop ■ is subjected to predetermined processing related to the data input/output frame /I'Iii, and the disconnection flags P1 to B in the loop II cutting line code BRKl are processed. "1's" 1
” is detected and +1? The detection signal J is output to the detourits auxiliary circuit 50.50'. Therefore, the +1 calculation auxiliary circuit 50.degree. 50' outputs a signal for incrementing the disconnection position data BD1, as described above. - The force/disconnection detection circuit 40' detects the breakage or disconnection of the loop (2), and inputs the detection signal S2 to the data processing circuit 25.

By inputting this signal S2, the f-reprocessing circuit 25 detects the loop vJTB flag pin h in the data frame signal.
B F 2 is set to "1" as shown in FIG. 15(d) - J: Sea urchin. In this case, since the output X of the data processing circuit 25 on the loop T side is selectively output to the outputs A and B of the switching circuit SW, the data! 18 The data frame signal output from the logic circuit 25 is passed through the exclusive OR game 1-55.
After the signal is added to the signal, the signal is sent back to the loops (2) and (H) via the transmitting circuit 30*30'. That is, node 1o-3
From then, l! as shown in FIG. 15(d). A data frame signal including the li line code portion is sent to loops ① and ②.

In this case, subsequent nodes 10-4. ...10
Since no disconnection has occurred at -n, each node 10-4
．． -・-10-n, both loops ■.

■If the data frame signals received via
Loop 1. II cut 1?2 code BRKI.

Disconnection position data BD1 in BRK2. BD2 is worshiped by +1 in sequence as shown in FIGS. 15(e) to (9).

As a result, the main controller 100 has nodes 10
-n, a data frame signal including a disconnection code section is input as shown in FIG. 15(0).

The main controller 100 recognizes the occurrence of a wire breakage by looking at the wire breakage flag pitch hBF1.8F2 of these wire breakage code sections, and further records the wire breakage position data 13D1. BO2
By standing the body on its head, you can determine the location of the gland that has occurred.

Next, as shown in FIG. 16, the overall operation when a disconnection occurs in both the node-to-node loops I and II will be described. In this case, a disconnection has occurred in both loops between nodes 10-1 and 10-2.

t! by disconnection detection circuit 40.40' of node 10-2!
Detected by Ii line detection No. 13 S1. S2 becomes rLJ. As a result, the disconnection frame signal generator 60 (Y) has a period Ta (which is shorter than the frame transmission period king of the main controller 100) (with Ta<TI, l!l shown in FIG. 6).
Generates an Ii line frame signal. Further, the switching circuit SW has d5 outputs 11 and d5 so that the outputs A and B of the switching circuit SW select the output of the disconnection frame signal generator 60, similar to the open gate T3 in FIG. Figure 17 (
A broken frame signal as shown in a) is loop 1. II.

Node 10-3° after this node 10-2...
At line detection circuit 2'g40.40', node 1
A disconnection caused by a disconnection in the immediately preceding loop III of S1.0-2 is detected, and the signal S1. An attempt is made to set S2 to rLJ, but almost at the same time, the disconnection code detection circuit 45.45' of the node 10-3 is turned on by the @ line frame lX signal Z sent from the previous node 10-2. Disconnection code 13R
KW is detected and a detection signal Se is sent to the disconnection detection circuit 40.40' and the +1 calculation auxiliary circuit 50.50'.

3. Output each e'.

Therefore, disconnection detection circuit 40.40 of node 10-3
The output 31.82 of ' does not become rLJ, but becomes rHJ. Therefore, each contact of the disconnection E circuit SW is not on the disconnection frame signal generator 60 side.

It is connected to the data processing circuit 25, 25' side. Also, +
1 performance p auxiliary circuit 50.50' is the above detection example ese,
By inputting Se', it operates as shown in FIG. 11, and the exclusive OR game! -55.

78 for adding +1 to the 1 new line position data part BWD of the disconnection frame signal to 56, respectively.

Furthermore, when the i-line frame signal Z is input to the data processing circuits 25 and 25', the signal Z is passed through as is, so that the signal Z is transmitted from the node 10-2 via the loops I and II. I've been beaten! The Iia frame signal Z is applied to the exclusive OR gates 1-55.56 via switching circuits SW, and these exclusive OR gates 1-55.56 change the disconnection position data section BWD to the 17th After being incremented by +1 as shown in Figure (b), the signal is sent to loops I and IF via the transmitting circuit 30.degree. 30'.

Below, node 10-4.10-5. ...10-n
Also, the same 4 as node 10-3! As a result, r! is generated from node 10-2. The FT line frame signal Z is
Each node 10-3.1O-4r its disconnection position data part B
WD is sequentially incremented by +1 as shown in FIG. 17 fc) to (e) and input to the main controller 100. This l! By inputting the Ii line frame signal Z, the main controller 100 can check the disconnection position data BWD and recognize that a disconnection has occurred in the loops I and If immediately before the node 10-2.

Thus, in this example. Since loops I and I[ are not prioritized as primary or secondary, and all loops between nodes with no disconnections are utilized for signal transmission, the same node - Signal transmission is performed except when a disconnection occurs in loops I and II between the nodes. Therefore, the system does not go down easily, and the durability and reliability against disconnection of the system can be improved.

Furthermore, when the data frame signal is formed as shown in FIG. 3 and a disconnection occurs in one loop, the 1gfI line code section BRK1. In addition to filling BRK2 with data indicating the occurrence of wire breakage and the wire breakage position, when both loops are broken, a wire breakage frame signal Z including lvi line position data as shown in FIG. 6 is used, so that the main controller 100 side In this case, it is possible to properly recognize this fact, and the subsequent disconnection recovery work is facilitated. Furthermore, in the above embodiment, the disconnection code section BRK1 of the data frame signal,
BRK2 disconnection position data section BD1. The wire breakage location data BWD in BD2 and the wire breakage frame signal Z are sequentially multiplied by +1 at each node, and this added data is viewed from a distance by the main controller to determine the wire breakage location.
Each node has a node number to identify each node.
This eliminates the need for all nodes to be drawn exactly the same, which is very cost-efficient and work efficient when designing and manufacturing a single circuit.

Further, the double loop groove structure shown in this embodiment produces the following additional effects. That is, the duplicate 4MB of each node is made exactly equal to J3, and loops I and II
Since no priority is assigned to the input/output terminals of each node, there is no need to distinguish which loop the input/output terminals belong to when connecting them, making wiring work much easier. This is the same even when the loop is a middle loop, and it is sufficient to connect the input terminal and output terminal to the instep without making any special settings to distinguish the loops.

It should be noted that the present invention may be modified as appropriate to the above embodiments; for example, the format of the frame signal used in the present invention is not limited to that shown in FIG.

For example, if only sensor 1 is connected to each node,
As shown in FIG. 18, the input data Di1 to Din from the sensor 1 of each node are sequentially inserted into the data frame portion between the start code 68 and the stop code SP, and the frame signal is passed through two loops. It is sufficient to send the data to ■ and ■. In FIG. 18, (a) is the signal immediately after being sent out from the main controller 100, and by adding the input data Di1 to Din of each node to this signal, the final result is +d in the figure. ) is input to the main controller 100. In FIG. 18, the position of data insertion at each node may be changed so that the input data is arranged in the order of Dil, Dl2, . . . Dln after the start code.

Moreover, when only the actuator 2 is connected to each node, as shown in FIG. 19, the area between the ST code and the SP code is used as an area for control data Do1 to Don for the actuator 2 of each node, If these control data are extracted sequentially from each node, it is possible.

Of course, in FIG. 19, (a) is the signal immediately after being sent out from the main controller 1 to the roller 100, and (d) is the signal input to the main controller 100. NaJ
5. In this case, the order of DO1 to Don may be reversed, that is, the order of DOn, DOn-1, . . . , DOl may be changed.

Furthermore, as shown in FIG. 20, output data D such as the start code STI for input 7-data Di.

A separate start code STO may be provided for each. In this case, Dlq is the input data to be inserted at the node, Dl is the input data already inserted at the previous node, Do (1 is the control data to be extracted at the node, Do is the control data to be extracted at the subsequent node) Show each data and set Dlton to Sfu-1~Code ST
[], and DOq is extracted immediately after the start code STO, but these data DIq
.

DOq may be inserted and extracted after data Di and Do, respectively.

By the way, although the above frame structure is of a variable data length system in which the signal length is variable, a frame system with a fixed data length as shown in FIG. 21 may also be used. That is, in FIG. 21, data frames DF1 to DF
s are data areas fixedly allocated to each of the five nodes, (a) shows the signal immediately after being sent from the main controller 100, and (b) and (c) show the data area for the nodes 10-1 and 10, respectively. -2, the signal output from (d
) is the main controller 100 with red and white five nodes.
This shows the signal input to. As is clear from the figure, in this case, each node extracts the control data Do for the actuator of the node from the data area DF corresponding to the node, and at the same time extracts the control data Do for the actuator of the node from the data area DF corresponding to the node. Detection data D
By inserting i, the signal length is always the same.

Format 1 shown in FIGS. 18 to 21, one example of which is shown above.
- data frame signals also have disconnection codes BRK1.- as shown in FIG. Of course, BRK2 is added.

In addition, in the above-mentioned embodiment, by adding (-1) to the l1Ii line position data section at each node, it was unnecessary to set a node identification number at each node. Each node may be configured to set .

Furthermore, the signal input detection circuit 35. Configuration for detecting disconnection by P3 and disconnection detection circuit 40, +1 conductor auxiliary circuit 5
The configuration for +1 addition Ω using 0 and exclusive OR data I.55 is merely an example, and any circuit configuration may be used as long as equivalent performance is achieved.

In addition, the disconnection code part [3RK1
．． 8RK2) t-mat, disconnection frame signal 74-
The mats are also not limited to those shown in the examples.

In addition, in the embodiment described above, f2 number of nodes 10-
1 to 10-n are connected in an open loop via the main controller 100, but if multiple nodes 10-n
The same configuration can be achieved by connecting the main controllers 1 to 0 in a loop with a ratio of 8/v.

[Effect of explanation] As explained above, according to the present invention, a plurality of nodes and the main coat roller are connected in series via two signal lines, and a loop between nodes in which no disconnection occurs is connected. Since all the signals used are transmitted, system failure does not occur easily, and durability and reliability against system disconnections can be improved.

Furthermore, in the event of a disconnection that makes it impossible to transmit signals, this fact is reported to the main controller, so that restoration work can be carried out quickly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the overall system configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing an example of the internal structure of each node, and Fig. 3 shows formats 1 to 1 of examples of data frame signals. 4 and 5 are diagrams for explaining data addition and data extraction at each node, respectively, and FIG.
FIG. 7 is a diagram for explaining the sending cycle of the data frame signal, FIG. 8 is a logic circuit diagram showing an example of the internal logic configuration of the switching circuit of each node, and FIG. 9 is a diagram for explaining the data frame signal. A detailed diagram illustrating a disconnection code section included in the signal,
FIG. 10 is an internal circuit diagram of the +1 cast auxiliary circuit, FIG. 11 is a time chip p-h showing the addition of the disconnection position data of the disconnection frame signal, and FIG. 12 is the addition of the disconnection position data of the data frame signal. Time chart showing p mode, 1st
Figure 3 is a time chart 1 to 1 for explaining the four switching states of loops I and If at each node, Figure 14 is a diagram showing an example of a disconnection, and Figure 15 is a diagram showing an example of a disconnection shown in Figure 14. FIG. 16 is a diagram showing a part of the data frame signal output from each node in the above case, FIG. 16 is a diagram showing another example of disconnection, and FIG.
The figure shows the lla frame signal output from each node when the disconnection shown in Fig. 16 occurs, and Figs. 18 to 21 each show other format examples of the frame signal used in the present invention. Figure 2211W is a diagram used to explain the disadvantages of the prior art. ■, ■... Loop, 1... Kefusa group, 2... Actuator, 10... Node, 20.20'...
Receiving circuit, 25.25'... data processing circuit, 30.
30'... Transmission circuit, 35.35'... Signal input detection circuit, 40.40'... Disconnection detection circuit, 45.45
'...Disconnection code detection circuit, 50.50'...+
1 calculation auxiliary circuit, 60... disconnection frame signal generator,
SW...Switching circuit, 100...Main controller. Moe Soju Frame, 0'N! Figure Figure 7/7$ 8th! Day F? KI RK2 F 8D+ F2 D2 Fig. 50, 50 Fig. 10〈 From RK+ Day RK2 Fig. 15 Fig. 16 Y-ray εNy''-Evening BWD No. s71E 5th SP ERF?
Figure 20 Figure 18 Figure 21 Figure Shin 19 Procedure ``11 Official Book (Method) % Formula % 1. Indication of the case 1988 Patent Application No. 237263 2. Name of the invention Case for persons who correct serial control device Relationship with Patent Applicant (123) Komatsu Ltd. 4, Substitute (104) 2-11-2 Ginza, Chuo-ku, Tokyo, Figures 18 to 21 are used in the present invention, respectively. FIG. 22 shows another example of the format of a frame signal.
The figure is a diagram used to explain the disadvantages of the prior art. ■,■...Loop, 1...Sensor group, 2...Actuator, 10...Node, 20.20'...
Receiving circuit, 25.25'...Data processing circuit, 30
．． 30'...Transmission circuit, 35.35'...Signal input detection circuit, 40.40'...Disconnection detection circuit, 45
．． 45'...Disconnection code detection circuit, 50.50'
...+1 performance auxiliary circuit, 60...l! 1iIIIil
Frame signal generator, SW... switching circuit, 100...
・Main controller. December 20, 1988 (light transmission date) 6. 43rd page of the original A subject to amendment

Claims (1)

[Claims] A plurality of nodes to which one or more terminals are connected and a main controller that manages these plurality of nodes are connected in series. In a serial control device that adds a signal from a terminal connected to its own node to data or extracts a signal sent to a terminal connected to its own node and sends it to a subsequent node, the plurality of nodes and the main controller are connected in series by two signal lines, and each node includes: first and second disconnection detection means for respectively detecting disconnection of the signal line between the two signal lines and the preceding node; A disconnection frame signal generating means generates a predetermined disconnection frame signal indicating a disconnection of both signal lines, and based on the detection outputs of the first and second disconnection detection means, two signals are generated when no disconnection occurs. The data frame signal from the line is sent to the two corresponding signal lines with the subsequent node, and when one of the two signal lines is broken, the data frame signal is sent from the signal line on the non-broken side. The frame signal is sent to the two signal lines between the downstream node, and when both of the two signal lines are disconnected, the generated disconnection frame signal is sent to the two signal lines between the downstream node and the downstream node. and a signal switching means for sending out signals to the signal lines.