JPH028504B2 - - Google Patents
Info
- Publication number
- JPH028504B2 JPH028504B2 JP58149598A JP14959883A JPH028504B2 JP H028504 B2 JPH028504 B2 JP H028504B2 JP 58149598 A JP58149598 A JP 58149598A JP 14959883 A JP14959883 A JP 14959883A JP H028504 B2 JPH028504 B2 JP H028504B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- rectifier circuit
- comparator
- switch element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 20
- 230000002265 prevention Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/60—Substation equipment, e.g. for use by subscribers including speech amplifiers
- H04M1/6033—Substation equipment, e.g. for use by subscribers including speech amplifiers for providing handsfree use or a loudspeaker mode in telephone sets
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、送話信号と受話信号の比較を行ない
ハウリング防止のため挿入した送話系、受話系の
損失回路を制御する拡声電話装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a loudspeaker telephone device that compares a transmitted signal and a received signal and controls loss circuits in the transmitting and receiving systems inserted to prevent howling. It is something.
（従来例の構成とその問題点）
一般に、拡声電話装置としては、第１図のよう
に、マイクロフオン１、マイクアンプ２、送話可
変損失回路３、ハイブリツドトランス４、受話可
変損失回路５、スピーカアンプ６、スピーカ７、
送話検波整流回路８、受話検波整流回路９、音声
スイツチ制御回路１０で構成されている。すなわ
ち、この装置ではハウリングを防止するため、送
話および受話の通話路に損失回路３，５を挿入
し、音声スイツチ制御回路１０により送話検波整
流回路８の出力と受話検波整流回路９の出力の大
小を比較してその損失回路３，５を制御してい
る。(Configuration of conventional example and its problems) In general, as shown in FIG. speaker amplifier 6, speaker 7,
It is composed of a transmitting call detection rectifier circuit 8, a receiving call detecting rectifier circuit 9, and an audio switch control circuit 10. That is, in this device, in order to prevent howling, loss circuits 3 and 5 are inserted into the transmission and reception channels, and the audio switch control circuit 10 controls the output of the transmission detection rectifier circuit 8 and the output of the reception detection rectification circuit 9. The loss circuits 3 and 5 are controlled by comparing the magnitudes of .
ここで送話・受話の検波整流回路８，９は、送
話・受話音声信号の差が比例動作するように、第
２図のように主にダイオードD1，D2、演算増幅
器１２から構成される対数変換回路１１と整流回
路１３から構成されている。この検波整流回路の
問題点としては送話・受話検波整流回路８，９の
入出力特性はダイオードD1，D2の電気的特性に
より左右されるため、送話及び受話検波整流回路
に使用するダイオードは特性を揃える必要があ
り、また一般のダイオードを使用した場合、対数
特性は低いレベルの入力になるにしたがつて直線
性がなくなりダイナミツクレンジは40dB前後で
ある。更にダイオードの特性は温度によつて大き
く変化するため、出力電圧、入出力特性の傾斜も
大きく変化する。これらの影響により、送話・受
話信号の差をとつて比較するには誤動作が生じ易
く正しい制御が行なわれない恐れがある。 Here, the detection rectifier circuits 8 and 9 for transmitting and receiving are mainly composed of diodes D 1 and D 2 and an operational amplifier 12 as shown in FIG. 2 so that the difference between the transmitting and receiving audio signals operates proportionally. It is composed of a logarithmic conversion circuit 11 and a rectification circuit 13. The problem with this detection rectifier circuit is that the input/output characteristics of the transmitting and receiving detection rectifier circuits 8 and 9 are influenced by the electrical characteristics of the diodes D 1 and D 2 . Diodes need to have the same characteristics, and if a regular diode is used, the logarithmic characteristics will lose linearity as the input level becomes lower, and the dynamic range will be around 40 dB. Furthermore, since the characteristics of the diode change greatly depending on the temperature, the output voltage and the slope of the input/output characteristics also change greatly. Due to these influences, when the difference between the transmitted and received signals is determined and compared, malfunctions are likely to occur and correct control may not be performed.
（発明の目的）
本発明は上記従来例の問題点を解決するもので
あり、対数変換のダイナミツクレンジを拡張して
音声スイツチ動作が安定に行なわれるようにする
ことを目的とするものである。(Object of the Invention) The present invention solves the problems of the conventional example described above, and aims to extend the dynamic range of logarithmic conversion so that the voice switch operation can be performed stably. .
（発明の構成）
本発明は、上記目的を達成するために、送話或
は受話信号の対数Ａ／Ｄ変換を行なうもので、変
換にあたつてはマイクロプロセツサ（以下CPU
と略記）内のROM或はRAMに設定した対数の
テーブルを参照しその内容をＲ−2Rネツトワー
ク（以下ラダー抵抗と略記）に出力しその出力電
圧と送話或は受話信号の検波整流出力電圧とをコ
ンパレータにより比較しながら逐次Ａ／Ｄ変換を
行なう。更に、検波整流回路の利得を制御しなが
らＡ／Ｄ変換を行ない、CPU内にて数値計算を
施しダイナミツクレンジを拡張するもので、これ
により従来の対数素子のバラツキを考慮せずにま
た簡単な構成で対数変換のダイナミツクレンジを
拡張することができる。(Structure of the Invention) In order to achieve the above object, the present invention performs logarithmic A/D conversion of a transmitting or receiving signal.
It refers to the logarithm table set in the ROM or RAM in the R-2R network (hereinafter abbreviated as ladder resistance) and outputs the output voltage and the detection rectification of the transmitting or receiving signal. A/D conversion is performed sequentially while comparing the voltage with the voltage using a comparator. Furthermore, A/D conversion is performed while controlling the gain of the detection rectifier circuit, and numerical calculations are performed within the CPU to expand the dynamic range. The dynamic range of logarithmic transformation can be expanded with this configuration.
（実施例の説明）
以下、本発明を第３図に示す一実施例により説
明する。第３図において、１４はラダー抵抗、１
５はCPU、１６はコンパレータ、１７は、送話
或は受話信号の入力端子、１８は入力信号を直流
電圧に変換する検波整流回路である。ここでこの
検波整流回路は第４図のように演算増幅器２０を
主とした構成となつており、さらにCPUの制御
信号１９でオンオフ制御されるスイツチ素子２１
により利得が可変できるようになつている。(Description of Embodiment) The present invention will be described below with reference to an embodiment shown in FIG. In Figure 3, 14 is a ladder resistance, 1
5 is a CPU, 16 is a comparator, 17 is an input terminal for a transmitting or receiving signal, and 18 is a detection rectifier circuit that converts the input signal into a DC voltage. As shown in FIG. 4, this detection rectifier circuit is mainly composed of an operational amplifier 20, and further includes a switch element 21 which is controlled on/off by a control signal 19 from the CPU.
This allows the gain to be varied.
このような構成において、一例としてダイナミ
ツクレンジ60dBの対数変換を得るための動作を
述べると、先づＡ／Ｄ変換の動作は、CPU出力
ポートPTCから信号を出力させラダー抵抗１４
の出力に現われる電圧Ａと信号入力端子１７に応
じた検波整流出力電圧Ｂとの比較をコンパレータ
１６で行ないこの出力をポートPTAで監視しな
がら逐次Ａ／Ｄ変換を行なうわけであるが、
CPUの出力ポートPTCから出力する信号は第５
図のようにあらかじめCPUのROM或はRAMに
1dB毎に変化する16進の数値を設定し順次指定さ
れる番地の内容を出力するようにしている。した
がつて、ラダー抵抗１４出力Ａと検波整流回路１
８の出力Ｂは対数での比較を行なうことになり、
さらに最終のＡ／Ｄ変換の値は、ROM或は
RAMの番地が対数のＡ／Ｄ値となる。第５図に
おいては０〜30番地まで、すなわち30dBの対数
変換ができるわけである。 In such a configuration, to describe the operation for obtaining logarithmic conversion with a dynamic range of 60 dB as an example, the A/D conversion operation first outputs a signal from the CPU output port PTC and connects the ladder resistor 14.
The comparator 16 compares the voltage A appearing at the output of the signal input terminal 17 with the detected rectified output voltage B corresponding to the signal input terminal 17, and successive A/D conversion is performed while monitoring this output at the port PTA.
The signal output from the CPU output port PTC is the fifth
As shown in the figure, it is stored in the CPU's ROM or RAM in advance.
A hexadecimal value that changes in 1 dB increments is set, and the contents of the specified address are output in sequence. Therefore, the ladder resistor 14 output A and the detection rectifier circuit 1
The output B of 8 will be compared logarithmically,
Furthermore, the final A/D conversion value is stored in ROM or
The RAM address becomes the logarithmic A/D value. In FIG. 5, logarithmic transformation of 30 dB is possible for addresses 0 to 30.
次に60dBまで拡張するための動作を述べる。
第４図においてスイツチ素子２１がオンした時に
はこの回路の利得が30dB、オフした時には0dB
となるよう抵抗R1とR2の値を設定する。ただし
ここでは入力端子１７に入力される最大レベルは
説明の簡便上0dBとして考える。 Next, we will describe the operation to expand to 60dB.
In Figure 4, when switch element 21 is on, the gain of this circuit is 30 dB, and when it is off, it is 0 dB.
Set the values of resistors R 1 and R 2 so that However, here, the maximum level input to the input terminal 17 is assumed to be 0 dB for the sake of simplicity.
次に第３図のCPUの出力ポートRTCに第５図
に示す０番地の内容を出力し、ラダー抵抗１４の
出力に現われる電圧Ａと、スイツチ素子２１がオ
フ状態で、入力端子に−30dBのレベルが入力さ
れた時の検波整流回路１８の出力電圧Ｂが同じと
なるようラダー抵抗１４に接続された抵抗Ｒの値
を設定しこの時の電圧Ａを基準電圧とする。 Next, the contents of address 0 shown in FIG. 5 are output to the output port RTC of the CPU shown in FIG. The value of the resistor R connected to the ladder resistor 14 is set so that the output voltage B of the detection rectifier circuit 18 when the level is input is the same, and the voltage A at this time is set as the reference voltage.
この設定状態において、スイツチ素子２１がオ
フとなるようCPUのポートPTBから制御信号を
出力し、ポートPTAにてコンパレータ出力を監
視する。この時、出力がLOWの場合、すなわち、
入力信号が−30dB以下の場合はスイツチ素子２
１をオンにし検波整流回路の利得を30dBに上げ
てＡ／Ｄ変換を行なう。逆にコンパレータ出力が
HIGHの時にはスイツチ素子２１をオフにし、
Ａ／Ｄ変換を行ないそのＡ／Ｄ変換結果の値に30
を加えるようにする。この一連の動作フローを第
６図に示す。 In this setting state, a control signal is output from port PTB of the CPU so that the switch element 21 is turned off, and the comparator output is monitored at port PTA. At this time, if the output is LOW, that is,
If the input signal is -30dB or less, switch element 2
1 is turned on, the gain of the detection rectifier circuit is increased to 30 dB, and A/D conversion is performed. Conversely, the comparator output
When it is HIGH, the switch element 21 is turned off,
Perform A/D conversion and add 30 to the value of the A/D conversion result.
Add . The flow of this series of operations is shown in FIG.
以上のことから本実施例においては、送話或は
受話系のレベルを制御することによりダイナミツ
クレンジが拡張できる。 From the above, in this embodiment, the dynamic range can be expanded by controlling the level of the transmitting or receiving system.
（発明の効果）
以上説明したように、本発明によれば、対数特
性はCPU内に設定した数値で決定されるため、
従来のように対数変換用素子のバラツキを考慮せ
ず安定な特性が得られ、またCPU内でＡ／Ｄ変
換を行ないダイナミツクレンジも計算によつて拡
張することができるので、安定した音声スイツチ
の動作が得られるようになり、簡単な構成で優れ
た特性の拡声電話装置を提供することができる。(Effects of the Invention) As explained above, according to the present invention, since the logarithmic characteristic is determined by the numerical value set in the CPU,
Stable characteristics can be obtained without considering variations in logarithmic conversion elements like in the past, and the dynamic range can be expanded by calculation by performing A/D conversion within the CPU, making it possible to achieve stable audio switching. As a result, it is possible to provide a loudspeaker telephone device with a simple configuration and excellent characteristics.
第１図は従来の拡声電話装置の構成図、第２図
は第１図に示す検波整流回路の具体回路図、第３
図は本発明の一実施例における拡声電話装置の対
数変換のためのＡ／Ｄ変換回路、第４図は第３図
における検波整流回路１８の具体回路図、第５図
は対数変換のためのCPU内に設定する対数テー
ブル、第６図はダイナミツクレンジ拡張のための
フローである。
１４……ラダー抵抗、１５……CPU、１６…
…コンパレータ、１７……信号入力端子、１８…
…検波整流回路、２１……スイツチ素子。
Figure 1 is a configuration diagram of a conventional loudspeaker telephone device, Figure 2 is a specific circuit diagram of the detection rectifier circuit shown in Figure 1, and Figure 3 is a diagram of the configuration of a conventional loudspeaker telephone device.
The figure shows an A/D conversion circuit for logarithmic conversion of a public address telephone device according to an embodiment of the present invention, FIG. 4 is a specific circuit diagram of the detection rectifier circuit 18 in FIG. 3, and FIG. The logarithm table set in the CPU, Figure 6 shows the flow for expanding the dynamic range. 14...Ladder resistance, 15...CPU, 16...
...Comparator, 17...Signal input terminal, 18...
...Detection rectifier circuit, 21...Switch element.
Claims (1)
ング防止のための損失回路と、送話信号、受話信
号のレベル差に応じて前記損失回路を制御する音
声スイツチ制御回路と、前記音声スイツチ制御回
路の入力側にそれぞれ設けられる検波整流回路で
あつてマイクロプロセツサにより制御されるスイ
ツチ素子を有し、このスイツチ素子のオン・オフ
動作により利得が可変できる検波整流回路と、前
記マイクロプロセツサの出力を電圧の大きさに変
換するラダー抵抗と、コンパレータとを有し、前
記検波整流回路の出力と前記ラダー抵抗の所定の
出力とを前記コンパレータで比較し、その比較結
果が小の場合は、前記スイツチ素子をオンにし前
記検波整流回路の利得を上げて前記コンパレータ
出力を前記マイクロプロセツサでＡ／Ｄ変換し、
前記比較結果が大の場合には、前記スイツチ素子
をオフにし前記検波整流回路の利得を下げて前記
コンパレータをマイクロプロセツサでＡ／Ｄ変換
するとともに所定値を加算することを特徴とする
拡声電話装置。1. A loss circuit for howling prevention inserted into the transmitting system and the receiving system, respectively, an audio switch control circuit that controls the loss circuit according to the level difference between the transmitting signal and the receiving signal, and the audio switch control circuit. A detection rectifier circuit is provided on the input side of each circuit, and has a switch element controlled by a microprocessor, and the gain can be varied by the on/off operation of the switch element, and the output of the microprocessor. and a comparator, the comparator compares the output of the detection rectifier circuit and a predetermined output of the ladder resistor, and if the comparison result is small, the turning on a switch element to increase the gain of the detection rectifier circuit and A/D converting the comparator output by the microprocessor;
If the comparison result is large, the switch element is turned off, the gain of the detection rectifier circuit is lowered, the comparator is A/D converted by a microprocessor, and a predetermined value is added. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14959883A JPS6041851A (en) | 1983-08-18 | 1983-08-18 | Loudspeaker telephone set |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14959883A JPS6041851A (en) | 1983-08-18 | 1983-08-18 | Loudspeaker telephone set |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6041851A JPS6041851A (en) | 1985-03-05 |
| JPH028504B2 true JPH028504B2 (en) | 1990-02-26 |
Family
ID=15478701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14959883A Granted JPS6041851A (en) | 1983-08-18 | 1983-08-18 | Loudspeaker telephone set |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041851A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10004445B2 (en) | 2010-09-16 | 2018-06-26 | Neurometrix, Inc. | Apparatus and method for stimulator on-skin short detection |
| AU2011301884B2 (en) | 2010-09-16 | 2015-08-06 | Neurometrix, Inc. | Apparatus and method for the automated measurement of sural nerve conduction velocity and amplitude |
| USD837394S1 (en) | 2017-07-11 | 2019-01-01 | Neurometrix, Inc. | Transcutaneous electrical nerve stimulation (TENS) device |
| USD857910S1 (en) | 2017-09-21 | 2019-08-27 | Neurometrix, Inc. | Transcutaneous electrical nerve stimulation device |
| USD865986S1 (en) | 2017-09-21 | 2019-11-05 | Neurometrix, Inc. | Transcutaneous electrical nerve stimulation device strap |
| USD861903S1 (en) | 2018-05-15 | 2019-10-01 | Neurometrix, Inc. | Apparatus for transcutaneous electrical nerve stimulation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5188104A (en) * | 1975-01-31 | 1976-08-02 | ||
| JPS5544256A (en) * | 1978-09-22 | 1980-03-28 | Komatsu Ltd | Programmable a-d converter |
| JPS55149883A (en) * | 1979-05-07 | 1980-11-21 | Seiko Epson Corp | Analog-digital converter for electric measuring device |
-
1983
- 1983-08-18 JP JP14959883A patent/JPS6041851A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5188104A (en) * | 1975-01-31 | 1976-08-02 | ||
| JPS5544256A (en) * | 1978-09-22 | 1980-03-28 | Komatsu Ltd | Programmable a-d converter |
| JPS55149883A (en) * | 1979-05-07 | 1980-11-21 | Seiko Epson Corp | Analog-digital converter for electric measuring device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6041851A (en) | 1985-03-05 |
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