JPH0284733A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0284733A JPH0284733A JP63237704A JP23770488A JPH0284733A JP H0284733 A JPH0284733 A JP H0284733A JP 63237704 A JP63237704 A JP 63237704A JP 23770488 A JP23770488 A JP 23770488A JP H0284733 A JPH0284733 A JP H0284733A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- layer
- bonding pad
- connect
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 238000007740 vapor deposition Methods 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 230000035939 shock Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に半導素子間を結線
するための金属配線構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a metal wiring structure for connecting semiconductor elements.
従来この種の半導体集積回路の金属配線は蒸着等により
一定膜厚を持った構造を有し、−層又は絶縁膜を介して
多層で形成されていた。Conventionally, metal wiring of this type of semiconductor integrated circuit has a structure having a constant film thickness by vapor deposition or the like, and is formed in multiple layers with a layer or an insulating film interposed therebetween.
上述した従来の金属配線は一定膜厚構造となっているの
で半導体素子の微細化、それに伴なう金属配線幅の縮小
化に伴ない金属配線膜厚も必然的に薄化の方向へ移行し
ているが一方で金属配線の電流密度を確保するため、金
属配線は部分的に薄化した分、配線幅を拡大せざるを得
ないと云う欠点がある。The conventional metal wiring described above has a constant film thickness structure, so as semiconductor elements become smaller and the metal wiring width decreases, the thickness of the metal wiring inevitably becomes thinner. However, in order to ensure the current density of the metal wiring, there is a drawback in that the metal wiring has to be partially thinned and the wiring width must be increased.
又、半導体素子と外部リード端子を結線するための電極
部（ボンディングパクド）も半導体素子微細化のため金
属配線が薄化するのに伴ない、薄くなりポンディング線
の接着部直下は、接着温度、加重によりアロイ化し硬化
するため、歪等によるダメージを受は易いと云う欠点が
ある。In addition, as the metal wiring becomes thinner due to the miniaturization of semiconductor elements, the electrode part (bonding pad) for connecting the semiconductor element and the external lead terminal becomes thinner, and the area directly below the bonding part of the bonding wire becomes thinner. Since it becomes an alloy and hardens due to temperature and load, it has the disadvantage that it is easily damaged by distortion and the like.
さらに該電極部は露出しているため金属配線が薄いと、
より外部の不純物等の影響を受は易いという欠点がある
。Furthermore, since the electrode part is exposed, if the metal wiring is thin,
It has the disadvantage that it is more easily influenced by external impurities.
本発明の半導体集積回路は金属配線の特定個所の幅を広
げることなく金属配線の膜厚を厚くすることにより所定
の電流密度を確保するためこの特定個所はあらかじめ金
属配線膜厚の厚くしたい電流密度寄与分を除去した金属
配線幅に設計した上、まず一定膜厚で全面金属配線を施
した後、次に特定選択個所に予定した金属配線膜厚を重
ねて所定の膜厚を施した構造を有している。The semiconductor integrated circuit of the present invention secures a predetermined current density by increasing the thickness of the metal wiring without increasing the width of a specific portion of the metal wiring. After designing the metal wiring width to remove the contribution, first apply metal wiring to the entire surface with a constant film thickness, and then apply the planned metal wiring film thickness to specific selected locations to create a structure with a predetermined thickness. have.
又、半導体素子と外部リード端子を結線するための電極
部（ポンディングパッド）の金属配線もボンディング線
接着時のアロイ化をコントロールできるだけの一定の厚
さを保持させるため、特定個所である内部金属配線膜厚
と同じ厚さを同時に作り込んだ構造を有している。In addition, in order to maintain a certain thickness for the metal wiring of the electrode part (bonding pad) for connecting the semiconductor element and the external lead terminal, which is sufficient to control the alloying when bonding wires are bonded, It has a structure in which the same thickness as the wiring film is made at the same time.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.
半導体素子部１の上部に酸化膜２を配し、さらにその上
部に半導体素子を結線するための第１層金属配線３，４
並びに半導体素子と外部リード端子を結線するための第
１層電極（ポンディングパッド）５を同時にアルミ蒸着
等により結線した後、あらかじめ、所定の電流密度を確
保するために選択した金属配線３の上部に第２層金属配
線６及び第１層電極（ポンディングパッド）５の上部に
第２層電極（ポンディングパッド）７を結線し、さらに
その上部に表面保護膜８を形成する。An oxide film 2 is disposed on the top of the semiconductor element section 1, and first layer metal wiring 3, 4 for connecting the semiconductor element is further formed on top of the oxide film 2.
After simultaneously connecting the first layer electrode (ponding pad) 5 for connecting the semiconductor element and the external lead terminal by aluminum vapor deposition, etc., the upper part of the metal wiring 3 selected in advance to ensure a predetermined current density is applied. Next, a second layer electrode (ponding pad) 7 is connected to the top of the second layer metal wiring 6 and the first layer electrode (ponding pad) 5, and a surface protection film 8 is further formed on top of the second layer electrode (ponding pad) 7.
第２図は本発明の他の実施例の縦断面図である。FIG. 2 is a longitudinal sectional view of another embodiment of the invention.
半導体素子部９の上部に酸化膜ｌＯを配し、その上部に
半導体素子を結線するための第１層金属配線１１．１２
並びに第１層電極（ポンディングパッド）１３を同時に
アルミ蒸着等により結線した後、絶縁層１４を介してそ
の上部に多層配線である第２層金属配線１５を結線する
際、あらかじめ電流密度を確保するために特定した第１
層金属配線１１の上部を開口した上部に第２層金属配線
１６及び第１電極（ポンディングパッド）１３の上部に
第２電極（ポンディングパッド）１７を同時に形成する
ため多層金属配線を行なう他の目的と同時に製造出来る
利点がある。An oxide film 1O is placed on the top of the semiconductor element section 9, and a first layer metal wiring 11, 12 for connecting the semiconductor element is formed on the top of the oxide film 1O.
In addition, after simultaneously connecting the first layer electrode (ponding pad) 13 by aluminum vapor deposition or the like, a current density is ensured in advance when connecting the second layer metal wiring 15, which is a multilayer wiring, on top of the first layer electrode (ponding pad) 13 via the insulating layer 14. The first identified
In order to simultaneously form the second layer metal wiring 16 on the upper part of the layer metal wiring 11 with an opening, and the second electrode (ponding pad) 17 on the top of the first electrode (ponding pad) 13, multilayer metal wiring is performed. It has the advantage of being able to be manufactured at the same time as the intended purpose.
以上説明したように本発明は半導体集積回路の金属配線
の一部を特定して金属配線の膜厚を厚くすることにより
金属配線の幅を広げることなく所定の電流密度を確保で
き、さらに電極（ポンディングパッド）の金属配線を同
時に厚くすることによりボンディング線の接着時の衝撃
及び接着後のモールド樹脂等の熱歪等にるダメージを軽
減出来ると共に外部からの不純物浸入による金属配線の
ダメージも軽減できる効果がある。As explained above, the present invention makes it possible to ensure a predetermined current density without increasing the width of the metal wiring by specifying a part of the metal wiring of a semiconductor integrated circuit and increasing the film thickness of the metal wiring, and furthermore, by specifying a part of the metal wiring of a semiconductor integrated circuit and increasing the film thickness of the metal wiring, By simultaneously increasing the thickness of the metal wiring of the bonding pad (bonding pad), it is possible to reduce damage caused by shock during adhesion of the bonding wire and thermal distortion of the mold resin after adhesion, as well as damage to the metal wiring caused by impurity infiltration from the outside. There is an effect that can be done.
又、多層金属配線構造の半導体集積回路装置においては
、製造工程を兼用できる効果もある。Further, in a semiconductor integrated circuit device having a multilayer metal wiring structure, there is an advantage that the manufacturing process can be used in common.
１２・・・・・・第１層金属配線、１３・・・・・・第
１層電極（ポンディングパッド）、１４・・・・・・絶
縁層、１５・・・・・・第２層金属配線、１６・・・・
・・第１層金属配線、１７・・・・・・第２電極（ポン
ディングパッド）、１８・・・・・・表面保護膜。12...First layer metal wiring, 13...First layer electrode (ponding pad), 14...Insulating layer, 15...Second layer Metal wiring, 16...
...First layer metal wiring, 17...Second electrode (ponding pad), 18...Surface protection film.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
第１図は本発明の一実施例であって半導体集積回路の金
属配線部の縦断図、第２図は本発明の他の実施例であっ
て多層配線構造を有した半導体集積回路に適用した金属
配線部の完断図である。Fig. 1 shows one embodiment of the present invention, which is a longitudinal cross-sectional view of a metal wiring part of a semiconductor integrated circuit, and Fig. 2 shows another embodiment of the invention, which is applied to a semiconductor integrated circuit having a multilayer wiring structure. It is a complete view of a metal wiring part.
Claims (1)
の膜厚を選択的に可変して結線したことを特徴とした半
導体集積回路。1. A semiconductor integrated circuit characterized in that when semiconductor elements are connected by metal wiring, the thickness of a part of the metal wiring is selectively varied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63237704A JPH0284733A (en) | 1988-09-21 | 1988-09-21 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63237704A JPH0284733A (en) | 1988-09-21 | 1988-09-21 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284733A true JPH0284733A (en) | 1990-03-26 |
Family
ID=17019272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63237704A Pending JPH0284733A (en) | 1988-09-21 | 1988-09-21 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284733A (en) |
-
1988
- 1988-09-21 JP JP63237704A patent/JPH0284733A/en active Pending
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