JPH0283862A - Variable gain system for pll circuit - Google Patents

Abstract

PURPOSE:To prevent the erroneous locking of a PLL circuit by surely making the title PLL circuit as a high gain for the sync byte or pseudo sync byte of data inputted to the PLL circuit and re-executing the pull-in until the aimed sector is found out. CONSTITUTION:The output signal of an OR gate 16 is made from a logic low into a logic high by the rising edge of a read gate (RGATE) signal to display a read action permission inputted to a terminal 4 and a sync byte detecting circuit 10, after the output signal of an OR gate 15 becomes the logic low, starts to detect the sync byte. When the byte is detected, a sync detect (the inverse of SDET) signal to display this becomes from the logic high to the logic low, an inverted WINDOW signal is outputted from a NOR gate 5 and inputted to a counter 11. When the counter 11 counts up, the output of a DDET signal becomes the logic high, the circuit 10 is made into the initial condition, the sync byte detection is started again and until the aimed data part is found out, this is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable gain system for a PLL circuit for a magnetic disk device.

[Conventional technology]

Generally, magnetic disk drives record and reproduce data in data portions called sectors. The sector is divided into an ID field and a DATA field.
The ID field and the DATA field each include a synchronization information section (hereinafter abbreviated as a sync byte section) required for the PLL circuit of the magnetic disk device and other data sections.

It is necessary for the PLL circuit to accurately synchronize with this sync byte and follow the data in the subsequent data byte.

A conventional variable gain system for a PLL circuit in a magnetic disk drive is shown in FIG. That is, a read gate (hereinafter abbreviated as RGATE) signal indicating read operation permission is input from terminal 4, a read data (hereinafter abbreviated as RDATA) signal is input from terminal 5, and a reset (hereinafter referred to as RESET) signal is input from terminal 6. (omitted) signal is input, terminal 7
A window (hereinafter abbreviated as WINDOW) signal is input from.

The signal input from the terminal 4.5.6.7 is input to the sync byte detection circuit 10. A sync byte (hereinafter abbreviated as 5DET) signal indicating that the sync byte detection circuit IO has detected a sync byte is output from the sync byte detection circuit 10 and then from the terminal 9.

The sync byte detection circuit starts detecting a sync byte by checking the positional relationship between the RDATA signal and the WINDOW signal after the RGATE signal becomes active. When the sync byte detection circuit detects the sync byte, it activates the 5DET signal. And the 5DET signal is RG
The active state is maintained until the ATE signal becomes inactive.

In other words, in a conventional PLL circuit, when a sync byte detection circuit detects a data pattern of '00' in a read data signal input to the PLL circuit, the gain of the PLL circuit is controlled by switching from a zero gain to a low gain. was.

[Problem to be solved by the invention]

The following problems occur in the variable gain method of the PLL circuit of the magnetic disk drive described above.

For example, when data is read into a diskette formatted by another magnetic disk device, the RDATA signal of the sector ID field and the DATA field may change due to variations in spindle motor rotation between the devices. There may be a difference in frequency between the RDATA signal and the RDATA signal. At this time, before the magnetic disk device finds the ID field of the target sector, the sync byte detection circuit detects the same '00° pattern as the sync byte part in the input read data signal in a part other than the original sync byte part ( (Hereinafter, it will be abbreviated as pseudo sync byte detection), the PLL circuit will have a low gain. Therefore, before finding the target sector, while reading the ID field and DATA field of the untargeted sector, the sync byte detection circuit detects the sync byte part of the untargeted sector, and the PLL In order to change and maintain the gain of the circuit from a high gain to a low gain, if an RDATA signal with a frequency difference as described above is input to the PLL circuit, there is a possibility that the PLL circuit will mislock.

[Means to solve the problem]

The variable gain method of a PLL circuit for a magnetic disk device according to the present invention includes a variable gain circuit that outputs a signal for switching between two types of gains of the PLL circuit, and a detection system that detects a sync byte from a data signal input to the PLL circuit. a counter that counts a predetermined value according to a detection signal of the detection circuit; a control signal that controls the detection circuit and the counter according to an output signal of the force counter and an external control signal; and an output signal of the detection circuit. , a means for switching the gain of the PLL circuit, a signal requesting the host CPU to process transfer data and execution results, a data request signal to the DAM controller, and a cycle permission signal of the DMA controller to the external control signal. and a circuit capable of detecting that any of them is input.

Therefore, by always setting the PLL circuit to high gain and re-synchronizing the sync byte or pseudo sync byte of the data input to the PLL circuit until the target sector is found, it is possible to prevent the PLL circuit from mislocking. It is possible.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows a first embodiment of the invention. That is, from terminal 1, a cycle permission signal of the DMA controller (hereinafter referred to as DA
A signal (abbreviated as CK signal) is inputted, and is inputted to an OR gate 14 through an inverter 13. Also, OR gate 14
A data request signal (hereinafter abbreviated as DRQ signal) to the DMA controller is input from terminal 2, and an interwoven request signal (hereinafter referred to as DRQ signal) input from terminal 3 requests the host CPU to process transfer data and execution results. (hereinafter abbreviated as INT signal) signal, and inverter 1
3 output signals are input. The output of this OR game) 14 is the D-type flip-flop 12 (hereinafter referred to as DFF).
') is input as a clock signal. The RGATE signal is input from the terminal 4, and is input as a data signal and a reset signal to the DFF 12, and is also input to the OR gate 16 through the inverter 17. Also, a data detect (hereinafter abbreviated as DDET) signal is similarly input to the OR gate 16, and the output of the OR gate 16 is input to the sync byte detection circuit. The RDATA signal, the RESET signal, and the WINDOW signal are input from the terminals 5, 6, and 7, respectively, and all three signals are input to the sync byte detection circuit.

In addition, the NOR gate 15 receives the Q output signal of the DFF 12,
Three signals, the DET signal and the WINDOW signal, are input, and the output signal of the NOR gate 15 is input to the counter 11. Further, the 5DET signal is outputted from the terminal 9 and also inputted to the counter 11. The counter 11 is NO.
A counting operation is started using the input signal from the R gate 15 as a clock signal, and when a predetermined value is counted, a DDET signal is outputted from the terminal 8.

2 and 3 show the timing chart of FIG. 1. RGATE signal rise query,
The output signal of R gate 16 goes from a logic high to a logic low. The sync byte detection circuit starts detecting the sync byte after the output signal of the OR game 15 becomes logic low.

When the sync byte is detected, the 5DET signal changes from logic high to logic low, and the inverted WIND signal is output from NOR gate 5.
The OW signal is output and input to the counter 11. At this time, INT and DRQ are received while the counter 11 is operating.

When the DACK signal is not input, that is, when data other than the DATA field of the target sector is being read, the counter 11 counts up and the DDET signal becomes a logic high, so the output of the OR gate 16 becomes a logic 1. The sync byte detection circuit is set to the initial state and sync byte detection is started again. That is, after detecting the sync byte, the PLL circuit becomes low gain, but when it detects that it is not the RDATA signal of the DATA field, the PLL circuit becomes high gain, starts detecting the sync byte again, and repeats this until the target data section is found.

On the other hand, while the counter 11 is operating, INT and DRQ.

When any one of the DACK signals is input, that is, when data in the DATA field of the target sector is being read, the output signal of the NOR gate 15, which is a clock signal, remains at a logic low level in the counter 11. Therefore, R.G.
The 5DRT signal does not go to a logic high until the ATE signal goes to a logic low.

That is, after the sync byte is detected, the PLL circuit goes into high gain, but when the RDATA signal of the DATA field is detected, the PLL circuit remains at low gain, and the magnetic disk device performs a read operation.

FIG. 5 shows a second embodiment of the invention.

That is, the DACK signal is input from terminal 1 and is input to OR gate 14 through inverter 13 . Also OR
Two signals are input to the gate 14: the DRQ signal input from the terminal 2, the INT signal input from the terminal 3, and the output signal of the inverter 13. This OR gate 14
The output of is inputted as a clock signal to the DFF 12.

RGATE signal, R from terminal 4.5.6.7 respectively.
The DATA signal, RESET signal, and WINDOW signal are input to the sync byte detection circuit. A 5DET signal is output from the sync byte detection circuit, and the signal is inputted to the data signal and reset signal of the DFF 12 through the inverter 18.

Furthermore, the NOR gate 16 receives the Q output signal of the DFF 12,
5DET signal and WINDOW signal are input, NO
The output of the R gate 16 is input to the counter 11. Further, the 5DET signal is outputted from the terminal 9 and also inputted to the counter 11. Further, a DDET signal is outputted from the counter 11, inputted to the sync byte detection circuit, and outputted from the terminal 8.

6 and 7 show the timing chart of FIG. 5. When the RGATE signal becomes a logic high, it starts detecting a sync byte, and when a sync byte is detected, the sync byte is detected.
The DET signal goes from logic high to logic low. Therefore, 5
At the falling edge of the DET signal, an inverted WINDOW signal is output from the NOR gate 16, and the counter 11
is input. At this time, while the counter 11 is operating, the INT
.

When the DRQ and DACK signals are not input, that is, when data other than the DATA field of the target sector is being read, the counter 11 counts up and the DDET signal is set to logic high, so the sync byte detection circuit becomes the initial state. , starts detecting sink bytes again. That is, after detecting the sync byte, the PLL circuit becomes low gain, but when it detects that it is not the RDATA signal of the DATA field, the PLL circuit becomes high gain and starts detecting the sync byte again.

On the other hand, INT and DRQ occur while the counter 11 is operating.

When any one of the DACK signals is input, that is, when data in the DATA field of the target sector is being read, the counter 11 receives the clock signal NOR.
Since the output signal of gate 16 remains at logic low,
The 5DRT signal does not go to a logic high until the RGATE signal goes to a logic low.

That is, after the sync byte is detected, the PLL circuit becomes low gain, but when the RDATA signal of the DATA field is detected, the PLL circuit is kept in the low gain state and a read operation is performed.

As described above, the second embodiment has the function of detecting whether or not it is a data portion after the 5DET signal becomes active, so it is possible to reliably detect the data portion.

〔Effect of the invention〕

As explained above, the PL of the magnetic disk device of the present invention is
The variable gain method of the L circuit is the ID field and DAT
When detecting the A field sync byte, be sure to use PL.
Since the sync byte detection is started after changing the gain of the L circuit from low gain to high gain, mislocking of the PLL circuit can be prevented.

In other words, by always performing synchronization with the PLL circuit set to high gain for the sync byte section and pseudo sync byte in the read data signal, synchronization can be reliably performed with each sync byte of the ID/DATA field after the target sector. Therefore, it is possible to reliably find the target sector without causing the PLL circuit to mislock.

5 is a timing chart of FIG.

1.2, 3, 4, 5, 6.7 are DACK respectively.

DRQ, INT, RGATE, RDATA, RESET
.

It is an input terminal for the WINDOW signal, and 8 and 9 are output terminals for the DDET signal and 5DET signal, respectively. 10
11 represents a sync byte detection circuit, 11 represents a counter, and 19 represents a variable gain circuit.

Further, 12 indicates a D-type flip-flop.

Furthermore, 13, 17, and 18 are inverters, 14 is a 3-person OR gate, 16 is a 2-person OR gate, and 15 is a 3-person NOR gate.

Agent: Patent Attorney Susumu Uchihara

[Brief explanation of drawings]

Claims (2)

[Claims] (1) A variable gain circuit that outputs a signal for switching between two types of gains in the PLL circuit, and a detection circuit that detects the synchronization information part required by the PLL circuit of the magnetic disk device from the data signal input to the PLL circuit. and a counter that counts a predetermined value based on the detection signal of the detection circuit.
A PLL circuit comprising at least a control means for controlling the detection circuit and the counter using an output signal of the counter and an external control signal, the gain of the PLL circuit being switched by the output signal of the detection circuit. Variable gain method. (2) As the external control signal, a signal requesting the host CPU to process transfer data or execution results, a data request signal requesting data from the DMA controller, and a cycle permission signal of the DAM controller are used; A variable gain system for a PLL circuit according to claim 1, further comprising a circuit capable of detecting that any one of them is input.