JPH0283729A - Parallel multiplier - Google Patents

Abstract

PURPOSE:To perform the addition at high speed with a circuit of a small scale by using a full adder which connects adders in a tree structure and adds the output of the adder of a first stage with a carry signal and adding 4 data input terminals to those adders forming a tree structure. CONSTITUTION:The adders 1 and 2 set on the 1st stage of an i-th digit perform the addition at every 7 bits supplied in parallel and process 14 bits in all. Then the adders 1 and 2 send the sums S1 and S2 to an adder 3 of a 2nd stage. Furthermore the adder 1 sends a 1-bit carrier signal C1a which is carried up to the (i+1)-th digit and a 1-bit carry signal C2a carried up to the (i+2)-th digit to the adders 30 and 35 respectively. While the adder 2 sends the carry signals C1b and C2b to the adders 30 and 35. An unprocessed bit out of the inner product of 15 bits, both sums S1 and S2, and each bit of carry signals C1a', C1b' and C2b' received from the adder of the 1st stage are inputted to the adder 3 and added together. This sum S3 is sent to a full adder 4 and at the same time the carry signals C3d and C3e are sent to the full adders 31 and 36 and added with the sums S3 received from the adders 30 and 35 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel multiplier that is small in circuit scale and can perform high-speed partial product addition by using a multi-bit adder and a full adder.

[Prior art and its problems] As an example of a method for processing addition of partial products generated by parallel multipliers, there is a method that includes only full adders 50 in multiple stages and forms a tree structure, as shown in FIG. be.

This uses a full adder that is supplied with 3-bit signals in parallel and sends out a sum and carry signal (indicated as C in the area), and for example, multiplies a multiplier by a multiplicand. For example, if the i-th partial product consists of 15 bits, five full adders 50 are provided in the first stage, and the sum sent by each full adder 50 and the i-1st partial product are A carry signal sent by a full adder (not shown) is sent to each of the three full adders 50 provided in the second stage.

The following are connected sequentially to multiple stages in the same way, and the full adder 5 in the sixth stage
The final addition result S is obtained at 0. Although Fig. 4 describes only the i-th digit, the i-11th digit, i+2nd digit, i-1st digit, i-2nd digit, etc.
・There is also a circuit with the same configuration.

In conventional partial product addition using only full adders, the number of stages of full adders forming the circuit increases because only 3-bit signals can be sent to the full adders, which inevitably increases the number of wires. There was a problem that the formed circuit became large.

On the other hand, instead of using a full adder, a multi-bit adder to which signals of 4 bits or more are supplied is used as a read-only memory (hereinafter referred to as ROM).
Although it is conceivable to implement the adder with a table (abbreviated as "abbreviated") and form the above-mentioned tree structure, it is also possible to implement the adder with a small number of bits, such as 4 bits or 7 bits, as used in the parallel multiplier of the present invention, using a ROM. Attempting to realize this would require a large circuit area, and it would be extremely difficult to integrate it into a single layer.

SUMMARY OF THE INVENTION The present invention was made in order to solve the two problems, and therefore, an object of the present invention is to provide a parallel multiplier that has a small circuit structure and can perform addition calculations of partial products at high speed. shall be.

[Means for Solving the Problems] The present invention connects adders in a tree structure and further includes one full adder that adds the addition result sent from the final adder and a carry signal. The multiplier is characterized in that the adder having a tree structure has four or more data input terminals.

[Operation] Sends a carry signal to be carried forward. As shown in FIG. 2, the adder L has N-channel L transistors 10 and transistors 10, which are arranged in a matrix with seven input terminals A to G1 each in the vertical and horizontal directions, to which data is supplied. This circuit is made up of a semiconductor element and includes seven sense amplifiers 11, NAN I) circuits 12 and 13, and an inverter 14, which amplify the signals. The input terminals A to G provided in each column are connected one-to-one to the respective common lines to which the gates of the l-runstars IO are connected, and in each row, the respective common lines to which the drains of the transistors 10 are connected are , are connected to sense amplifiers 11 provided for each row. For example, the positive logic output line 20 of the sense amplifier Ila and the negative logic output line 21 of the sense amplifier llb are connected to the input side of the NAND circuit 12a, and the positive logic output line 22 of the sense amplifier 11b and the negative logic output line of the sense amplifier llc are connected to the input side of the NAND circuit 12a. 23 is NΔAND circuit +2b
The sense amplifier 11 is connected to the input side of the sense amplifier 11 in the same way.
and the NΔAND circuit 12 are connected. Note that the sense adder processes signals of 4 bits or more, and is provided in multiple stages until the signal supplied to one full adder becomes 3 bits. Since the adder processes signals of 4 bits or more, the number of stages is reduced and the calculation speed is increased. Only one full adder is used and adds the 3-bit signals supplied in parallel.

[Example] Figures 1(a) and 1(b) showing an example of the present invention
When multiplication is performed using a parallel multiplier, for example, when the partial product of the first fold is 15 bits, a 7-pit adder (
In the figure, it is written as ADI). ) 112 and 3 and a full adder (denoted as FA in the figure) 4, forming a tree structure. In addition, Fig. 1 (1)) is Fig. 1 (a)
Although the "-" position from the 1st + 2nd digit is not shown in Figure 1 (a) and the position lower than the i-2 fold is not shown in Figure 1 (b), it exists similarly. be.

In this embodiment, adders 1, 2 and 3 add the data of 7 data supplied in parallel, sum it up, carry it to the 1st place, and the positive logic of the carry signal and the 2-digit upper amplifier I1g. Output line 24 is connected to the input end of inverter 14. The NAND circuit 13a sends out the sum S° of the signals supplied from the input terminals A to G.
2a, 12c.

+2e and the output side of the inverter 14 are connected to the NAND circuit 13b which sends out the carry signal CI.
The NAND circuit 13c, which is connected to the output side of the ND circuits 12b, I2c, and 12f and the inverter 14 and sends out the carry signal C2, includes an NΔAND circuit 12d,
I 2e, I 2f and the output side of the inverter 14 are connected.

When O data is supplied to all of the input terminals A to G in the adders 1.2 and 3 having such a configuration, all the positive logic outputs of the sense amplifiers Ila to Ilg send out a 0 signal, Since all the negative logic outputs of the sense amplifiers Ila to Ilg send out l signals, NAND
The circuits 12a to I2r and the inverter 14 are all
The signal is sent out. Also, when data of 1 is supplied to any one of the input terminals A to G, the sense amplifier 1I
The positive logic output of a sends out the signal of I, and the sense amplifier Il
Since the negative logic output of b sends the signal of I, N
Only the AND circuit 12a sends out an O signal. Similarly,
When data of 1 is supplied to two input terminals A to G, only the NAND circuit I2b sends out a signal of O. Every time the data of l supplied to the input terminals A to G increases, the NAND circuit 12 that sends out a 0 signal to the following groups changes, and when data of 1 is supplied to all of the input terminals A to G, the inverter Only 14 transmits a 0 signal. And the NAND circuit 13 is the NAND circuit 12
The sum S° and carry signals C1 and C2 are output based on the signals sent by the inverter 14.

Note that the adder 1.2 to which the above-mentioned 7-bit signal is supplied
A 4-bit to 6-bit multi-bit adder can also be created by configuring the adder in the same manner as 3 and 3.

In the parallel multiplier of this embodiment shown in FIGS. 1(a) and (b), when the partial product of a certain digit consists of 15 bits, the carry signal output terminals of adders 40 and 45 in the first stage are connected. Ru. The sum output terminal 3a of the adder 3 provided at the i-th digit is connected to the input side of the full adder 4, and the carry signal output terminals 3b and 3c of the adder 3 are connected to the full addition terminal 3a provided at the i+1st digit and the i+2nd digit. 3I and 36. On the input side of the full adder 4, an adder 41 is provided at the 11th digit and the i-2nd digit.
and 46 carry signal output terminals are connected, and the sum output terminal 4a and carry signal output terminal 4b of the full adder 4 provided at the i-th digit are connected to a known CLA or C5A3 that processes carry signal propagation at high speed. Ru.

In the parallel multiplier of the present invention having the above configuration,
Adders 1 and 2 provided at the first stage of the i-th digit each perform addition processing of 7 bits each supplied in parallel, processing a total of 14 bits. The adder 1 sends the sum Sl, which is the result of the addition, and the adder 2 sends the sum S2, respectively, to the adder 3 provided at the second stage of the i-th digit. Also, the adder 1 is the 1st higher digit (i+1 digit) carried forward by 1 bit, and the adder 1 is provided in the first stage and processes 7 bits, and the adder 2 is provided in the second stage. one adder 3 that processes 7 bits, one full adder 4 provided in the third stage, and a carry look ahead (hereinafter abbreviated as CL A) or carry select provided in the fourth stage. The adder (hereinafter abbreviated as C9A) 5 is provided.

The sum output terminals 1a and 2a of the aforementioned 7-bit data adders 1 and 2 provided in the first stage of the i-th digit have the same configuration and function as adders 1 and 2 provided in the second stage. The carry signal output terminals 1b and 2b of the adders 1 and 2 to the upper digit indicated by i+1 are connected to the input side of the adder 3 having It is connected to the input side of 30. Carry-up signal output terminals 1c and 2c to the upper two digits indicated by i+2 are connected to the input side of a second-stage adder 35 provided at the i+2nd digit. The input side of the adder 3 provided at the second stage is supplied with the remaining 1 bit of the 15 bits and a carry signal C1 for adding the partial products of the i-1st digit and the i-2nd digit.
a and a 1-bit carry signal C2a that is carried up to the i+2nd digit, which is two higher digits, to the adders 30 and 35 provided in the second stage of the i+1st digit and the i+2nd digit, respectively. 2 also sends carry signals C, 1b and C2b to the adders 30 and 35 in the second stage of the higher order.

The adder 3 provided at the second stage of the i-th digit receives the unprocessed remaining 1 bit of the aforementioned 15-bit partial product and the sums Sl and S sent by the aforementioned adders I and 2.
2, and one bit each of the carry signals C1a', C1b', C2a', and C2b' sent by the adders 40 and 45 provided in the first stage of the 11th digit and the i-2nd digit. Since a total of 7 bits are supplied in parallel, these data can be processed by a single 7-bit adder.

Therefore, the adder 3 adds these data and sends the sum S3 to the full adder 4 at the next stage, and also sends the carry signal C3d and the full adder 31 and 36 provided in the third stage for the i+1st digit and the i+2nd digit. Send C, 3e. The data supplied to the next stage is 1 bit of the sum S3 sent out by the adder 3, and 1 bit each sent out by the adders 4I and 46 provided in the second stage for the i-1st and i-2nd digits. carry signal C
3d' and C3e°, the total number of bits supplied is 3 bits, and these data can be processed by one full adder. Therefore, the full adder 4 provided at the i-th digit is
The sum S and carry signal C, which are the processing results, are sent to the next stage, for example, C.
Send to LA 5. CLA5 propagates the carry signal from the lower digits at high speed and sends out the final addition value F.

In this way, (1) 5-bit partial product addition can be realized using three stages of adders and one CLA or CSA, making it possible to perform calculations with a smaller circuit size and higher speed than in the conventional example.

” The two series of explanations are for the case where the partial product is 15 bits, but the first
Taking as an example the case where the partial product shown in the table consists of 4 bits, the first
The adder shown in the figure will be explained.

Table 1 shows the case where a 4-bit multiplicand of X4X3X2X is multiplied by a 4-bit multiplier of Y, Y3Y2Y.

For example, the i-th partial product IX,Y is supplied to the terminal P, and the partial product 2X3Y2 is supplied to the terminal P2.

The other partial products 3.4 are similarly supplied to the terminals P3, ))4 for addition, and the addition results are output from the full adder 4.

Table 1 4X3 →-)Y4Y,.

X, Y, lX,, Y IX4Y21 X,, Y, 1X2Y, lX4Y, 1X3
Y31 X2Y31X, Y30) X4Y4 X3Y
41X2Y41 XIY4X2 XI 2 Y X, Y, X, Y IY2 Q, Q10. I Q, l C41C31Q,
Q Multiplicand Multiplier Partial Product 1 Partial Product 2 Partial Product 3 Partial Product 4 Product Figure 3 shows the case where the partial product of the i-th digit consists of 9 bits. A circuit with the same configuration and function is provided at the lower level.

The first stage includes two adders 1' and 2° that process the 7-bit signal supplied to the parallel 1-nor, and one adder 6 that processes the 5-bit signal that is supplied in parallel. The second stage is equipped with one adder 3° that similarly processes 7 bits, the third stage is equipped with one adder 7 that similarly processes 5 bits, and the fourth stage is equipped with one adder 3° that similarly processes 7 bits. is equipped with a full adder 4', and the fifth stage is equipped with CLA or C5A3.

This embodiment also basically has the same configuration as the above-mentioned embodiment, and because the number of bits of the partial product has increased, the first and third stages
5-bit adders 6 and 7 are added to each stage.

Adders 1' and 2' that process a 7-bit signal provided in the first stage and adder 6 that processes a 5-bit signal send out a 1-bit sum SBI, S2'', and S6, and this digit. Carry signals C1a'', C1b'', 02a'' and C2b'', each consisting of 1 bit, are sent out by adders (not shown) provided in the first stage of the 1st and 2nd digits lower than the i-digit second stage. It is sent to the adder 3' which processes the 7-bit signal provided in the 7-bit signal.In addition to the carry signals CIa"C1b", C2a", and C2b" mentioned above, the carry signal C1a" etc. are sent to the second stage. Carry signals C6a'' and C6b' are sent out from the adder that sends out the adder 3.
' is a 7-bit process, so the carry signals C6a' and C6
b' is sent to the adder 7 provided at the third stage of the first digit. Note that the carry signal that the first stage adder provided in the lower digit than the i-th digit sends to the third stage adder provided in the first digit is the carry signal that is sent to the adder provided in the third stage lower than the i-th digit. The carry signal C6a' from the adder and the carry signal C6b' from the adder located two digits lower than the i-th digit are used, but the present invention is not limited to this, and the carry signals Cla'', C1b'', etc. may not be arbitrarily combined. can. Then, the adder 3' provided in the second stage of the i-digit digit adds the sum S3' consisting of l bits to i
The carry signals C3°a and C3°b are sent to the adder 7 provided in the third stage of the digit, and the carry signals C3°a and C3°b are sent to the adders (not shown) provided in the third stage one and two digits higher than the wooden digit. do.

Therefore, the adder 7 provided in the third stage of the i digit receives the aforementioned carry signals C6a' and C6b', the sum S3'', and the adder 7 provided in the second stage (not shown) which is one and two digits lower than this digit. The carry signals C3°a° and C3°b' sent out by the adder of
A total of 5-bit signals, 1 bit each, are supplied in parallel. Then, the adder 7 adds the supplied signals and sends the sum S7 to the total sum value 4' provided in the fourth stage of the i-th digit.

The full adder 4° contains the sum S7, one digit from this digit, and two digits.
Carry signals C7a' and C7b' sent out by an adder (not shown) provided in the third stage of the lower digit are supplied in parallel with a total of 3 bits of signal power of 1 bit each, and the full adder 4' is supplied with The added signals are added and the sum S and carry signal C are sent to, for example, CLA5, which executes the addition process and sends out the final added value F.

Even when the partial products consist of 19 bits in this way, partial product addition can be realized using four stages of adders and one CLA or CSA, making it possible to perform high-speed calculations with a small circuit scale.

Furthermore, instead of configuring the adding circuit only with a full adder whose partial product consists of N bits and can only process a 7-bit signal, by using an adder that can process a signal of 4 bits or more, The number of stages configuring the adder circuit is reduced. Therefore, the scale of the circuit becomes smaller, and
Addition calculations can be performed quickly.

[Brief explanation of the drawing]

1(a) and 1(b) are block diagrams showing one embodiment of the present invention, FIG. 2 is a diagram showing the configuration of an adder used in the parallel multiplier of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. This figure is a block diagram showing another embodiment of the present invention, and FIG. 4 is a block diagram of a conventional circuit for performing partial product addition. 1 to 3... Adder, 4... Full adder, 5 ・CL A or C8A.

Claims (1)

[Claims] (1) A multiplier in which adders are connected in a tree structure and further includes one full adder that adds the addition result sent by the final stage adder and a carry signal, which has a tree structure. A parallel multiplier, wherein the adder has four or more data input terminals.