JPH0282815A - Counter check system - Google Patents

Abstract

PURPOSE:To easily detect a fault in the stepping of a counter only through the addition of a simple hardware by discriminating the counter to be faulty when a detection means confirms that an output of a circuit latching parity is unchanged with the stepping of the counter. CONSTITUTION:A counter 1 in figure is operated so that the count is stepped every time an advance condition signal 10 is 'ON' (same definition as 'present'). An output signal 15 of a parity latch circuit 3 is compared with an output signal (count) 12 of the counter 1 by a parity check circuit 4, which generates a parity error output signal 13 if the parity is dissident. Moreover, a parity change detection circuit 5 has a function storing the output signal 15 of the parity latch circuit 3 depending on the preceding count and compares the parity of a new parity output signal 15 of the parity latch circuit 3 revised with the stepping condition signal 10 set to 'ON' with the stored parity by the preceding count to detect the coincidence.

Description

[Detailed Description of the Invention] CII Required] Regarding the fault checking method for the counter circuit used in the combi coater system, in order to check the validity of the count value of the counter circuit, it is necessary to retain the previous count value and to check the validity of the count value of the counter circuit. With the aim of solving the problem of increasing hardware due to the need for a circuit that compares the count value or a circuit that compares the current count value with a value defined by the system, we developed a parity prediction circuit and a parity prediction circuit. In a counter circuit that has a circuit that holds the parity predicted by the parity, and a circuit that performs a parity check using the output of the parity holding circuit and the count value of the counter, the increment value at which the parity changes each time the counter increments is calculated. means for detecting a change in the output of the parity holding circuit, and is configured to check whether or not the parity changes when the counter increments.

[Industrial Field of Application] The present invention relates to a counter circuit used in a combinatorial system (in this specification, when a counter and a peripheral check circuit are included, the term "counter circuit" is used, and when only a counter is referred to, the term "counter circuit" is used). The present invention relates to a check method called an "r counter", and in particular to a counter check method for detecting a parity change in a counter circuit having a parity prediction circuit.

[Prior Art] In recent years, there has been a strong demand for non-stop systems in arithmetic processing devices. To this end, various measures have been taken to prevent a failure in one part of the system from affecting the entire system. ing. Detection of a failure in a part of this system needs to be done quickly and accurately.

Generally, in a combinator system, a large number of counters are used, each of which performs an important function, and failure detection of the counters is an important issue.

Conventional counter checking methods generally include a method in which the counter is equipped with a parity prediction circuit and the result is checked for parity, or a method in which the counters are duplicated and compared with each other.

However, in the above method, the validity check is performed to check whether the current counter value is a valid increment from the previous counter value, or whether the current counter value is defined as a system and there is no contradiction. It has not yet reached that point.

[Problem to be Solved by the Invention] Therefore, in order to check the validity of the count value of a counter, a circuit that holds the previous count value and compares it with the current count value, or a circuit that compares the current count value with the system-defined value is required. This required a circuit to compare the values, which caused the problem of increased hardware.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a counter check method that can check the validity of the increment of a count value with only the addition of a small amount of hardware.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims. That is, the present invention provides a counter circuit that includes a parity prediction circuit, a circuit that holds the parity predicted by the parity prediction circuit, and a circuit that performs a parity check based on the output of the parity holding circuit and the output of a counter. , comprising means for giving a counter increment value so that the parity changes each time the counter increments, and detecting a change in the output of the circuit holding the parity each time the counter increments, This counter check method determines that the counter has failed when the detection means confirms that the output of the parity holding circuit does not change when the counter increments.

[Function] The counter that is the target of failure detection is given an increment value such that when the counter increments, the parity according to the count value of the counter always changes, and the parity change detection circuit Each time an increment is made, it is checked whether the parity of the previous count value and the parity of the current count value are different. If they are the same, the count value of the target counter did not increment normally, or It is determined that the count value has not changed and the counter failure output signal is turned "ON".

[Embodiment] FIG. 1 shows a circuit block diagram of an embodiment of the present invention, in which 1 is a counter subject to failure detection, 2 is a parity prediction circuit, 3 is a parity holding circuit, and 4 is a parity check. 5 is a parity change detection circuit, 10 is a step condition signal, 11 is a step value signal, 12 is a counter output signal (
13 is a parity error output signal,
14 represents a counter failure output signal, and 15 represents an output signal of the parity holding circuit.

The counter 1 in the figure operates so that the count value increments every time the increment condition signal 10 becomes "ON" (synonymous with "ON"). Also, determine whether the count value of counter 1 is to be counted up or down, and whether the count value is 1, 2, etc. . . . n is determined by the condition given by the step value signal 11.

The parity prediction circuit 2 predicts the parity that should be generated by the count value of the counter 1 at the next time based on the count value of the counter 1 at the present time and the given step value condition, and transmits the prediction result to the parity holding circuit 2. to hold.

The output signal 15 of the parity holding circuit 3 is converted to the output signal (counted value) 1 of the counter 1 in the parity check circuit 4.
2, and if the parities do not match, a parity error output signal 13 is generated.

Further, the parity change detection circuit 5 has a function of storing the output signal 15 of the parity holding circuit 3 according to the previous count value, and the parity holding circuit 3 is updated when the step condition signal 10 turns "ON". The new parity output signal 15 is compared with the stored parity based on the previous count value, and a match or mismatch is detected.

For example, if the increment of the counter 1 is determined so that the parity is always inverted for each count, the parity change detection circuit 5 stores the output signal 15 of the parity holding circuit 3 and the previous count value. If the comparison result with the parity obtained by
is set to “ON”.

FIG. 2 is a diagram showing an example of the configuration of a parity change detection circuit, in which 6 is a flip-flop (FFI) that holds the parity of the previous count value, 7 is a comparison circuit between the parity of the previous count value and the current parity; 8 is a flip-flop (FF2) that holds the output of the comparator circuit 7, and 16 is a flip-flop (FF2) that holds the parity of the previous count value.
17 represents the output signal of the comparator circuit.

For those skilled in the art, this parity change detection circuit can have a wide variety of configurations, and this example is just one of them.

The operation of the parity detection circuit shown in FIG. 2 can be easily understood by the time chart shown in FIG.

FIG. 3 shows a time chart for explaining the operation of the parity change detection circuit, in which (1) is the step condition signal, (
2) is the output signal of the parity holding circuit, and (3) is the flip (FFI) that holds the parity based on the previous count value.
(4) represents the output signal of the comparator circuit, and (5) the output signal of the flip-flop (FF2) shows how the signal waveforms change over time.

In the same figure, 20, 21, and 22 are step condition signals on the time chart, 23 are the output signals of the parity holding circuit on the time chart, 24 are the output signals of the flip-flop (FFI) on the time chart, and 25 are the time The output signal 26 of the comparison circuit on the chart represents the output signal of the flip-flop (FF2) on the time chart.

The output signal 23 of the parity holding circuit 3 is the step condition signal 20
．． 21 ON side rising signal (prefixed lines al, a in the figure)
(signal indicated by 2) (this example deals with the case where the step condition is given so that the parity changes every count).

In addition, the output signal 24 of the flip-flop (FFI) 6 that holds the parity based on the previous count value is the falling signal of the step condition signal (signal indicated by leading lines b1 and b2 in the figure).
, the contents of the parity output signal 23 of the parity holding circuit are taken in (the state shown by the arrowed lines C1 and C2 in the figure),
The output signal 25 of the comparator circuit 7 has a signal level of "1" when the signal 23 and the signal 24 match, and has a signal level of "0" when they do not match.

The flip 70 knob (FF2) 8 that generates the counter failure output signal 26 is operated by a margin such as the operation time of the parity holding circuit 3 from the rising signal (al, C2, C3) of the step condition signal 20 to the "ON" side. , with a delay of ΔT,
The output signal 25 of the comparator circuit 7 is output at timing 1.
The data is captured at a time of 1°t (data capture states indicated by dl, C2, and C3 in the figure).

Among the step condition signals 20, 21, and 22, the parity output signal 23 of the parity holding circuit 3 and the output of the flip-flop (FFI) 6 are The signal 24 changes normally, and at the timing (1+11) when the comparison circuit output 25 is taken into the flip-flop (FF2) 8, the comparison circuit output 25 is at the signal level "0", and the flip-flop (FF2>8 The output signal 26 of is at signal level “0” (“
(synonymous with “OFF”).

Now, if a failure occurs in the counter at time tr and a situation occurs in which the count value is not updated, the count value of the counter will not change even if the step condition 22 is entered, so the parity output signal 23 of the parity holding circuit 3 will be at the signal level. The output signal 24 of the flip-flop (FFI) 6 remains unchanged at the signal level "0", and the output signal 25 of the comparison circuit 7 also maintains the signal level "1".

Therefore, the rising signal of step condition signal 2 (arrowed line a in the figure)
At time t3, which is delayed by ΔT from the signal indicated by 3), the signal level "12" of the output signal 25 of the comparator circuit is taken into the flip-flop (FF2) 8, and the output signal 26 of the flip-flop (FF2) 8 is taken in. becomes level “1” (synonymous with “ON”) after time t3, and the output signal 26
becomes the counter failure output as is.

Upon receiving this counter failure output signal, the system detects that a failure has occurred in the counter.

FIG. 4 is a diagram showing an example of the increment of the counter according to the present invention, and is an example of a 4-bit counter.

Figure (a) shows the normal stepping state, and figure (c)
shows a stepping method in which the parity changes with each step,
The line with the leading edge in the figure indicates that there is no count value corresponding to the portion where the line with the leading edge exists, and that this portion is skipped and the step advances. Also, whether the step progresses from the top to the bottom or from the bottom to the top is determined by 11 in Figure 1.
It is determined by the step value signal indicated by .

[Effects of the Invention] As explained above, according to the present invention, it is possible to easily detect failures in counter progress by simply adding simple hardware.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and FIG.
3 is a diagram showing an example of the configuration of a parity change detection circuit, FIG. 3 is a time chart for explaining the operation of the parity detection circuit, and FIG. 4 is a diagram showing an example of the increment of a counter according to the present invention. 1... Counter, 2... Parity prediction circuit, 3... Parity holding circuit, 4...
・Parity check circuit, 5...Parity change detection circuit, 6...Flip 70 tube (FFI)
, 7...Comparison circuit, 8...Flip-flop (FF2), 10...Step condition signal, 1
1...Step value signal, 12...Counter output signal, 13...Parity error output signal,
14... Counter failure output signal, 15...
...Output signal of parity holding circuit, 16...Output signal of flip-flop (FFI), 17...
- Output signal of the comparison circuit, 20.2122... Step condition signal on the time chart, 23... Output signal of the parity holding circuit on the time chart, 24...
...Flip-flop (FFI) on the time chart
), 25... Output signal of the comparison circuit on the time chart, 26... Output signal of the flip 70 flip (FF2) on the time chart

Claims (1)

[Scope of Claims] A counter comprising a parity prediction circuit, a circuit that holds the parity predicted by the parity prediction circuit, and a circuit that performs a parity check based on the output of the parity holding circuit and the output of the counter. The circuit includes means for providing a counter increment value such that the parity changes each time the counter increments, and detecting a change in the output of the circuit that maintains the parity each time the counter increments. A counter check method characterized in that, when the detection means confirms that the output of the parity holding circuit does not change when the counter increments, it is determined that the counter has failed.