JPH0282758A - Picture data reproducing device - Google Patents

Abstract

PURPOSE:To simplify a control by inputting and outputting video signal data asynchronously to an external synchronizing signal to input a video signal. CONSTITUTION:A data reproducing device 1 has a pair of buffers 10, a counter 20, a write control part 30, and a frame memory 40. Further, the video signal, which is inputted at a continuously fixed length and at a constant rate, is transferred to the frame memory 40. Thus, since the data rate at which the video signal is sent can be asynchronously operated to the operating frequencies of the frame memory 40, the display timing of the frame memory 40 can be overlapped with the write timing, and the control can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data reproducing apparatus, and particularly to synchronization of input data such as a video signal in an image data reproducing apparatus.

As is well known, a video signal represents an image in chronological order using scanning lines obtained by cutting a surface image into small pieces.

For this reason, when storing video signal data recorded in an external recording device, for example, in the frame memory of an image playback device, in order to accurately restore the decomposed video signal, it is necessary to input an external synchronization signal from the external recording device. The video signal data had to be imported field by field into the frame memory while synchronizing with the video signal data. In other words, the frame memory must be synchronized to an external synchronization signal.

Therefore, a synchronization signal was required for video signal data. Therefore, in order to extract a synchronization signal from a video signal, for example, Japanese Patent Application Laid-Open No. 82-84878 or No.
8 etc. is used. Also, when writing video signal data from an external storage device to frame memory,
There was one that accessed memory using DMA transfer.

In this way, when video signal data is stored in the frame memory in synchronization with the external synchronization signal, this external synchronization signal is also used as a reference when reading the video signal data from the frame memory. Therefore, in order to display the video signal read from the frame memory on a display without flickering, for example, the speed conversion for TV relation output must be performed in the frame memory, and the problem is that the control becomes extremely complicated. was there. For example, there is a technique described in Japanese Patent Laid-Open No. 62-82888 that teaches this speed conversion.

Purpose The present invention solves and eliminates the drawbacks of the prior art, and makes it possible to operate a frame memory at an operating frequency asynchronous to an external synchronization signal for inputting a video signal without being affected by it. The purpose of the present invention is to provide an image data reproducing device.

According to the present invention, an image data reproducing device that stores video signal data sent in synchronization with an external synchronization signal in a frame memory stores video signal data in synchronization with the external synchronization signal. It has a buffer means for transferring the accumulated video signal data to the frame memory in synchronization with an internal synchronization signal which is the operating frequency of the frame memory.

According to the present invention, input video signal data sent in synchronization with an external synchronization signal is stored in a frame memory, and the input video signal data forms a frame by interlaced scanned odd and even fields. The image data reproducing device stores video signal data for one scanning line of an odd field in synchronization with an external synchronization signal, and transfers the stored video signal data to a frame memory in synchronization with an internal synchronization signal. a second buffer means for storing video signal data for one scanning line of even fields in synchronization with an external synchronization signal, and transmitting the stored video signal data to the frame memory in synchronization with an internal synchronization signal. By alternately setting the first buffer means and the second buffer means in a writing state at a predetermined period in synchronization with an external synchronization signal, the input video signal data is transferred to the first buffer means in a field-by-field manner. and a first control means for storing data in either of the second buffer means, and alternately puts the first buffer means and the second buffer means in a read state at a predetermined period in synchronization with an internal synchronization signal, and By notifying the frame memory that it is in the read state, the first buffer means and the second buffer means
and second control means for transferring the video signal data stored in the buffer means of the first buffer means to the frame memory, and synchronizes the video signal data from the first buffer means and the second buffer means with an internal synchronization signal. By transferring the synchronization signal to the frame memory, the frame memory is operated independently of the external synchronization signal.

Next, embodiments of the image data reproducing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a functional block diagram of an embodiment of the image data reproducing apparatus according to the present invention is shown. The image data reproducing apparatus 1 receives an external synchronizing signal (data CLK) from an external recording device 70 such as a memory card, for example. ) is a playback device that writes/reads video signal data sent in synchronization with the frame memory 40 asynchronously with this external synchronization signal, and outputs the read video signal to an image output device such as a display. . The data reproducing device fit includes a pair of buffers 10, a counter 20, and a write control section 30.
and a frame memory 40.

Each of the pair of buffers IO temporarily stores the video signal sent from the external recording device 70 as data for one horizontal scanning line (IH) in synchronization with an external synchronization signal, and also stores the stored video signal data as data for one horizontal scanning line (IH). The external synchronization signal is a buffer that asynchronously sends one line at a time to the frame memory 40. To explain in more detail, the buffer lO has a write clock terminal WCLK which inputs an external synchronization signal 10G of, for example, 3.58 MHz sent from the external recording device 70 via the clock signal line 100, and a write clock terminal WCLK which inputs an external synchronization signal 10G of, for example, 3.58 MHz sent from the external recording device 70 via the clock signal line 100, and a write clock terminal WCLK which inputs an external synchronizing signal 10G sent from the external recording device 70 via the clock signal line 100. It has an input terminal IN to which video signal data of 70 is input, and a write control terminal WE which is L active to which a write control signal is input via a control line 130. When the write control terminal WE becomes "L", the buffer IO inputs and stores 768 one-line video signal data via the signal line 120 in synchronization with the external synchronization signal 100.

Buffer lO also. Internal clock (4FSC) 500 of the image data reproducing device l via a clock signal line 500
RCLK, an output terminal OUT for transferring accumulated video signal data to frame memory 40 via signal line 100, and a read control terminal RE connected to control line 302 and active.

When the read control terminal RE becomes rLJ, the buffer 10 outputs the stored video signal data to the frame memory in synchronization with the internal clock 500. In this embodiment, the buffer 10 that stores video signal data for one scanning line of an odd field is called a buffer Buff, and the buffer 10 that stores video signal data for one scanning line of an even field is called a buffer Buf2. In this embodiment, three buffers Buff and BaF2 are provided, each corresponding to RGB video signals.

The counter 20 is a control device that controls writing of a video signal sent from an external device into the buffer 10.

The counter 20 receives an external synchronization signal 100 via a clock signal line 100 and a start signal 1 indicating that video signal data is to be sent from the external recording device 70 via a control line 130.
30 are each scanned. After receiving the start signal 130, the counter 20 controls the buffers IO so that video signal data is alternately stored in the buffers Bufl and BaF2 in synchronization with the external synchronization signal 10G.

More specifically, when the control output 200 is in the "L" state, the control output 202 is set to rHJ, and the buffer Buf
When the control output 202 is in the "L" state, the control output 200 is controlled to be "H" and the video signal data is stored in the buffer Buf2. do. Further, the counter 20 is
A signal FIELD indicating switching timing of buffers Buff and BaF2 is supplied to frame memory 40 via control output 204. Note that in this embodiment, when the video signal data is stored in the buffer Buff, the signal FIELD becomes "L" level, and the buffer Buff
When the video signal data is stored in f2, the signal F
IELD becomes rHJ level.

The write control unit 30 is a control circuit that controls reading out the video signal data stored in the buffer IO and transferring it to the frame memory 40. In detail, the control unit 30
receives an internal clock 500 via a clock signal line 500 and a horizontal synchronizing signal (10) via a signal line 310, and uses these signals to alternately control the readout control terminals RE of the buffers Buff and BaF2 at a predetermined period.
It is set to the "L" level during the H period, and the video signal data stored in each buffer is transferred to the frame memory 40. The write control unit 30 also outputs the output 3 while keeping either the buffers Buff or BaF2 in the read state.
A write request signal WREQ is output to the frame memory via 00.

The frame memory 40 stores l frames of video F! , a memory that stores signal data. The frame memory 40 outputs, for example, 525 scanning lines of data per field at 30 frames per second. During the IH period when the frame memory 40 receives the write request signal WREQ from the write control unit 30, the frame memory 40 writes one field worth of video signal data sent from the buffer Buff via the input/output line 400 into a predetermined area. , when the write request signal is not received, the stored video signal data is sent to the D/A converter (not shown) via the input/output line 400 at the aforementioned speed. Note that in this embodiment, the frame memory 4
When the video signal data for 3 fields of 0 is sent to the D/A converter, the video signal data for 1 field is input from the buffer 10, and the contents inside the frame memory are rewritten. That is, the inside of the frame memory 4G becomes new video signal data every 4v cycle.

In this example, one period of the horizontal synchronization signal (10) is 910 pulses (4FSC).From this, one continuous line (788 pulses) at the rate of the subcarrier frequency (FSC)
) data is 788 x 4/910 = 3.378M. Therefore, there are three or four horizontal synchronization signals HD in one line of data.

FIG. 2 shows a processing sequence illustrating an example of the operation of the image data device 1. In FIG. The operation of this embodiment will be explained using this figure and FIG. For example, when the memory card 70 is attached to the playback device 1 and the video signal data stored therein is received by the image data playback device 1, the memory card 70 first changes the control line 130 from the H level to the L level. As a result, a start signal 130 is output to the counter 20.

After sending out the start signal, the card 70 sends the stored video signal data to the buffers Buf1 and BaF via the signal line 120 as input data in synchronization with the subcarrier frequency FSC, which is an external synchronization signal of 3.58 MHz.
Send to 2.

When the counter 20 receives the start pulse, the counter 20 inputs the input data to the buffer Buf for each scanning line.
The respective write control terminals WE are alternately set to L level so that data is stored in f and BaF2.

As a result, the 768 pieces of input data on the first line are synchronized with the external synchronization signal and stored in the buffer Buff, and the 768 pieces of data on the second line are sent to the buffer Buff2.
will be written to. Similarly, in the next cycle, the third line data is sent to the buffer Bu instead of the previously input data.
ff, the data of the fourth line is written to the buffer Buf2. Further, the counter 20 has a control output 2
04 to notify the frame memory 40 of the signal FIELD. That is, when the write control terminal WEt of buffer Buf1 is set to L level, the counter 20 sets the control output 204 to L level to indicate that writing to buffer Buff is being performed, and also sets the write control terminal WE of buffer Buf2 to L level. control output 20 when
4 to H level to notify the frame memory 40 that input data is being written to the buffer Buf2.

When a video signal is written as input data to the buffers Bufl and BaF2, the write control unit 30 writes the buffers Buff and BaF2 in synchronization with the horizontal synchronization signal HD.
In other words, the write control unit 30 alternately controls the readout control terminal RE of the buffer Buff or BaF2 to go low every four cycles of the horizontal synchronization signal HD. level. At this time, the write control unit 30 sends the write request signal WREQ to the frame memory 40 while the write control unit 30 is at L level. Therefore, the frame memory 40 stops outputting the stored video signal data during the IH period of the horizontal synchronization signal HD, receives the video signal data from the buffer 10, and transfers the received video signal data to the line data of a predetermined field. overwrite the memory location. As described above, according to this embodiment, it is possible to input and output video signal data asynchronously with the external synchronization signal.

Note that the embodiments described here are for explaining the present invention, and the present invention is not necessarily limited thereto, and modifications and variations that can be made by those skilled in the art without departing from the spirit of the present invention. Modifications are within the scope of this invention.

肱-1 As described above, according to the present invention, a video signal from an external recording device that is continuously input in a fixed length and at a constant rate can be transferred to a frame memory that is continuously operating at a different frequency. Can be done.

In this way, since the data rate at which the video signal is sent and the operating frequency of the frame memory can operate asynchronously, the timing of displaying and writing to the frame memory can overlap, and therefore Control becomes easy.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment of an image data reproducing device according to the present invention, and FIG. 2 is a signal sequence diagram showing an example of a processing sequence in the device of FIG. 10゜20゜30゜40゜Parts Description Image data reproducing device Buffer counter write control unit Frame memory Patent applicant Fuji Photo Film Co., Ltd. Agent Person number Takao Maruyama

Claims (1)

[Claims] 1. An image data reproducing device that stores video signal data sent in synchronization with an external synchronization signal in a frame memory, the device comprising: An image data reproducing apparatus characterized in that it has a buffer means for accumulating the video signal data and transferring the accumulated video signal data to the frame memory in synchronization with an internal synchronization signal which is an operating frequency of the frame memory. 2. An image data reproducing device that stores input video signal data sent in synchronization with an external synchronization signal in a frame memory, and forms a frame using odd and even fields that are interlaced scanned. In this apparatus, the apparatus stores video signal data for one scanning line of the odd field in synchronization with the external synchronization signal, and stores the stored video signal data in the frame memory in synchronization with the internal synchronization signal. a first buffer means for storing video signal data for one scanning line of the even field in synchronization with the external synchronization signal, and storing the stored video signal data in synchronization with the internal synchronization signal; A second buffer means for transferring the input video signal to the frame memory, and a first buffer means and a second buffer means are alternately brought into a writing state at a predetermined period in synchronization with the external synchronization signal, thereby reducing the input video signal. a first control means for storing data in either the first buffer means or the second buffer means in a field-corresponding manner; By putting the video signal data stored in the first buffer means and the second buffer means into the read state at a predetermined cycle and notifying the frame memory that the read state is in the read state, a second control means for transferring to the frame memory, and transferring the video signal data from the first buffer means and the second buffer means to the frame memory in synchronization with the internal synchronization signal, An image data reproducing device characterized in that the frame memory operates independently of the external synchronization signal.