JPH0282733A - Spread spectrum signal demodulating circuit - Google Patents

Abstract

PURPOSE:To correctly demodulate an information signal by controlling a phase modulating means to phase-modulate a reference signal from a reference signal generating means in accordance with the change direction of the output amplitude of a multiplying means. CONSTITUTION:The output of a multiplying means 14 to multiply an input signal and a code from a code preparing means 13 is extracted and held at a prescribed timing and compared with the output of the multiplying means 14 extracted before one timing. Based on the compared result, the phase relation of the input signal and the code from the code generating means 13 is decided and a phase modulating means 12 to output the reading clock signal of the code generating means 13 is controlled so as to synchronize the input signal and the code. Thus, without using a voltage control type oscillator, the synchronizing accuracy and demodulating accuracy can be improved.

Description

[Detailed description of the invention] (b) Industrial application fields The present invention relates to a spread spectrum signal demodulation circuit.

(b) Conventional technology Conventionally, for example, a two-way pseudo noise code (Pseudo No. 1seC) having a sufficiently wider spectrum width than the information signal
ode) (hereinafter referred to as PN code), and the receiving side demodulates the original information by multiplying the received signal by the same PH10 code used on the transmitting side. Diffusion communication is known (see, for example, the November 1978 issue of Denshi Science).

In such spread spectrum communication, as mentioned above, the information code is modulated using a PN code or the like having a wide spectrum width, so in order to accurately demodulate the information signal, the code generated on the receiving side must be the same as the code on the transmitting side. need to be synchronized with.

As a method for achieving the above synchronization, Tau dither ((Hu-
dither) method is known. The tau dither method will be explained with reference to FIG.

In Figure 3, (1) is the input terminal into which the spread spectrum signal is input, and (2) is the voltage controlled oscillator (VCO).
, (3) is a phase modulator that modulates the phase of the output of the VCO (z) with the output signal from the low frequency R[device (4), and (5) is a clock that reads the output signal from the phase modulator (3). (6) is a first multiplier that multiplies the spread spectrum signal from the input terminal (1) by the code from the code generator (5); (7) is the first multiplier (6) ), and (8) is the signal from the demodulator (7) (a signal obtained by envelope detection of the output signal of the first multiplier).
A band pass filter (BPF) (9) is supplied with the signal passed through B P F (8) and a low frequency oscillator (4
), a second multiplier (10) is a low-pass filter (LPF) to which the output signal of the second multiplier (9) is supplied, and the signal passed through this L P F (10) is is supplied to V CO (2) as a control signal.

Now, in spread spectrum communication, it is known that the level of the output signal from the first multiplier changes depending on the phase relationship between the input signal and the code, and this relationship is shown in Figure 4. The operation of the circuit shown in FIG. 3 will be explained with reference to FIG.

Now, if the initial position of the code sequence is at point 1a in Figure 4, and the phase advances and moves to point 1b, then the low frequency oscillator (
The relative phase of the code reciprocates between pixels due to the rectangular wave signal from 4), and accordingly, the output signal of the first multiplier (6) undergoes amplitude modulation at the same frequency as the rectangular wave signal. .

Such amplitude modulation component is extracted by B P F (8) and then multiplied by the square wave signal in a second multiplier (9) to obtain the correct signal for controlling V CO (2). It is converted into DC signal components with polarity and level. Due to such a DC signal component, the output of the V CO (2) changes the rate of generation of the code sequence in a direction in which correlation increases and synchronization occurs.

Note that when the relative phase of the code sequence reciprocates between points 2a and 2b, the polarity of the amplitude variation is reversed, and the change in the rate of generation of the code sequence is also reversed.

Furthermore, when the relative phase of the code sequence reciprocates across the correlation peak, that is, when it reciprocates between points 3a and 3b, there is no change in the amplitude of the output signal of the first multiplier (6). There is no amplitude variation component supplied to the second multiplier (9), and the oscillation frequency of the VCO (2), that is, the rate at which the code sequence is generated does not change.

(C) Problems to be Solved by the Invention In the conventional technology described above, the oscillation frequency of the VCO is used to generate a code in synchronization with the input signal when demodulating the spread spectrum signal.

However, since the VCO is generally configured to include a variable capacitance diode and the like, it is easily affected by temperature drift, etc., and has the problem of unstable operation.

(d) Means for Solving the Problems In view of the above points, the present invention provides a reference signal generating means for generating a reference signal of a predetermined frequency, and a phase modulating means for phase modulating the reference signal from the reference signal generating means. , a code generating means for generating a code such as a pseudo-noise code according to the output signal from the phase modulation means, a multiplication means for multiplying the code from the code generation means by an input signal, and an output from the multiplication means. a comparison means for holding the output signal according to a predetermined clock signal and comparing the held output with an output held one cycle before the clock signal; The present invention is characterized by comprising determining means for determining a phase state and controlling the phase modulating means to synchronize the input signal and the code.

Preferably, the phase modulation means includes a programmable frequency divider that divides the output signal from the reference signal generation means by N (N is an integer), and is configured to change the frequency division ratio based on the signal from the determination means. It is characterized by being

(E) Operation According to the present invention, the output of the multiplication means for multiplying the input signal by the code from the code generation means is extracted and held at a predetermined timing, and is compared with the output of the multiplication means extracted one timing before.

Based on the comparison result, the phase relationship between the input signal and the code from the code generation means is determined, and the phase modulation means for outputting the readout tarlock signal of the code generation means is controlled so as to synchronize the input signal and the code. do.

(F) Embodiment FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, (11) is a reference signal generation circuit that generates a reference signal of a predetermined frequency, including, for example, a crystal oscillator, and (12) is a phase modulation circuit that modulates the phase of the reference signal from the reference signal generation circuit (11). As shown in FIG. 2, the circuit consists of a programmable frequency divider (12A) and an N setting section (12B) for setting the frequency division ratio N of the frequency divider.

(13) is a code generator that generates a code such as a pseudo noise code by using the output signal from the phase modulation circuit (12) as a readout signal; Multiplier that multiplies, (15) multiplies 16 (14)
The demodulator (16) demodulates the output of the demodulator (16), which is a bandpass filter (BPF) (1
7) is a low frequency oscillator, (18) is a low frequency oscillator (17)
The output signal from the clock signal is used as a clock signal, and the signal passed through the BPF (16) is held in response to this tarok signal, and the held output is compared with the output held -period ago of the clock signal. As shown in Figure 2, this circuit includes a sample hold section (1
9), a delay circuit section (20) that delays the output of the sample and hold section (19) by 12 clocks, a holding section (21) that holds the output from the delay circuit section (2o), and a sample and hold section (21) that holds the output from the delay circuit section (2o). It is composed of a comparator (22) that compares the outputs from the section (19) and the holding section (21). (2
3) is a determination circuit that determines the phase state of the code with respect to the input signal based on the output signal from the comparison circuit (18);
As shown in the figure, it is composed of 70 D flips (24).

Next, the operation will be explained. Programmable frequency division using the N setting section (13)! It is assumed that the frequency division ratio N is set in (12A).

Now, the spread spectrum signal input from the input terminal is multiplied by the code output from the code generator (13) in the multiplier (14), and as a result, the carrier component of the spread spectrum signal (the carrier is two-phase modulated) is multiplied by the code output from the code generator (13). , a two-phase modulated carrier component) is derived.

Such a carrier component passes through a demodulator (15) and is derived from an output terminal. Further, the envelope of the carrier component is supplied to a comparison circuit (18) via a bandpass filter (16).

In such a comparison circuit (18), as shown in FIG.
The envelope of the carrier component that has passed through F (16) is subjected to low frequency oscillation 1! In response to the output signal (clock signal) from (17), it is sampled and held in the sample hold section (19) and is supplied to the non-inverting input terminal of the comparison 1iF (22). In addition, the sample hold section (19
) are compared via the delay circuit section (2o) and the holding section (21)! It is also supplied to the inverting input terminal of (22).

Therefore, compare! (22) is the current multiplier output amplitude and 1
The amplitude of the multiplier output before the clock is compared.
As is clear from FIG. 4, when the output of the comparator (22) is at H level, the input signal and the code are in the synchronous direction, and when it is at the L level, the input signal and the code are in the asynchronous direction. shown.

Then, a D flip 70 tube (
24) Compare! The Q output is inverted every time the output of (22) rises to L level.

Thus, the N setting section (1) constituting the phase modulation circuit (12)
4) Programmable frequency division! From (13), the output of the determination circuit (23) is determined every time a frequency division output is generated, and when the output signal of the determination circuit (23) is at H level, the direction of change in the frequency division ratio is set to the current direction (e.g. , the direction in which the frequency division ratio is increased by 1), and when the output signal of the determination circuit (23) is at the L level, the direction of change in the frequency division ratio is maintained in the opposite direction to the current direction (the direction in which the frequency division ratio is subtracted by 1). direction).

Thus, a code is generated! (13) is controlled so that the code generated from the code generator (13) is synchronized with the code used during transmission (modulation).

(G) Effects of the Invention According to the present invention, since the phase modulation means for phase modulating the reference signal from the reference signal generation means is controlled according to the direction of change in the output amplitude of the multiplication means, the voltage controlled type There is no need to use an oscillator, and synchronization accuracy and demodulation accuracy can be improved.

Furthermore, by providing a programmable frequency divider in the phase modulation means and changing the frequency division ratio of the programmable frequency divider based on the signal from the determination means, it is possible to easily and digitally control the phase modulation. It is possible and practical.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 shows an embodiment of the present invention, Fig. 2 shows its main circuit diagram, Fig. 3 shows a conventional example, and Fig. 4 shows relative change in code phase. FIG. (11)... Reference signal generation circuit, (12)... Phase modulation circuit, (13)... Code generator, (14)...
Multiplier, (15)...Demodulator, (16)...BPF
, (17)...Low frequency oscillator, (18)...Comparison circuit, (19)...Sample hold section, (2o)...
...Delay circuit, (21)...Holding section, (23)...
Judgment circuit, (24)...D flip 70 tube.

Claims (2)

[Claims] (1) A reference signal generating means for generating a reference signal of a predetermined frequency, a phase modulating means for phase modulating the reference signal from the reference signal generating means by adjusting the phase thereof, and an output signal from the phase modulating means. code generating means for generating a code such as a pseudo-noise code in response to the code, multiplication means for multiplying the code from the code generating means by an input signal, and holding the output from the multiplication means in accordance with a predetermined clock signal. a comparing means for comparing the held output with an output held one cycle before the clock signal; and determining the phase state of the code with respect to the input signal based on the output signal from the comparing means, and determining the phase state of the code with respect to the input signal. A spread spectrum signal demodulation circuit comprising: determination means for controlling the phase modulation means so as to synchronize the signal with the code. (2) The phase modulation means includes a programmable frequency divider that divides the frequency of the output means from the reference signal generation means by N (N is an integer), and changes the frequency division ratio based on the signal from the determination means. 2. The spread spectrum signal demodulation circuit according to claim 1, wherein the spread spectrum signal demodulation circuit comprises: