JPH0282544A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0282544A JPH0282544A JP23550388A JP23550388A JPH0282544A JP H0282544 A JPH0282544 A JP H0282544A JP 23550388 A JP23550388 A JP 23550388A JP 23550388 A JP23550388 A JP 23550388A JP H0282544 A JPH0282544 A JP H0282544A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding
- electrode
- chip
- solder resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000011889 copper foil Substances 0.000 claims abstract description 11
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 101150071746 Pbsn gene Proteins 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 239000011261 inert gas Substances 0.000 abstract description 2
- 229910020658 PbSn Inorganic materials 0.000 abstract 2
- 239000007789 gas Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はテープ状の絶縁フィルムに銅箔配線を形成、こ
れにＩＣチップを搭載してなる半導体装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which copper foil wiring is formed on a tape-shaped insulating film and an IC chip is mounted on the copper foil wiring.
従来この種の半導体装置はＩＣチップにＡｕやＰｂＳ、
等でバンプ（突起状）電極を形成し、絶縁フィルムのイ
ンナーリード部と熱圧着法によりボンディングされて作
られている。Conventionally, this type of semiconductor device uses Au, PbS,
A bump (protruding) electrode is formed using a material such as the like, and is bonded to the inner lead portion of the insulating film using a thermocompression bonding method.
また一部にはテープ上にバンプ構造の電極を形成してＩ
Ｃチップとボンディングする方法も実用化されている。In some cases, bump-structured electrodes are formed on the tape.
A method of bonding with a C chip has also been put into practical use.
上述した従来の半導体装置に使用される銅箔は非常ニ薄
く、かつ、ＩＣチップとの接続部はフィルムの支えもな
く、むき出しの状態となるので非常にリードが変形しや
すいという欠点がある。The copper foil used in the above-mentioned conventional semiconductor device is extremely thin, and the connection portion with the IC chip is exposed without any support from the film, so the lead is easily deformed.
また、このリード先端にバンプ電極を形成するとさらに
変形が助長される傾向にある。Furthermore, if a bump electrode is formed at the tip of this lead, the deformation tends to be further promoted.
一方、ＩＣチップにバンプ電極を形成するには工程が複
雑となりＩＣチップ価格が非常に高いものになるという
問題がある。On the other hand, there is a problem in that forming bump electrodes on an IC chip requires a complicated process and the cost of the IC chip becomes extremely high.
本発明の半導体装置は、絶縁フィルム上に形成された銅
箔配線とその表面をフィルム上のソルダーレジストで覆
うと共に、ＩＣチップとボンディングするインナーリー
ド部のソルダーレジストに開口部を設け、この開口部に
ｐｂｓｎ等の金属でバンプ構造の電極を形成し、この電
極とＩＣチップの電極を熱圧着してなるものである。In the semiconductor device of the present invention, copper foil wiring formed on an insulating film and its surface are covered with a solder resist on the film, and an opening is provided in the solder resist of an inner lead portion to be bonded to an IC chip. A bump-structured electrode is formed from a metal such as PBSN, and this electrode and an electrode of an IC chip are bonded by thermocompression.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
絶縁フィルム１は耐熱性の点から、主にポリイミドが用
いられ、稀に、ポリエステル、ガラエポフィルム使用さ
れる。この絶縁フィルムに銅箔を接着剤で貼り合わせホ
トエツチング法により、銅箔配線２が形成される。この
上に、フィルム上のソルダーレジスト３を貼り合わせ、
やはりホトエツチング法により、ＩＣチップ４とのボン
ディング部に開口部を設ける。この開口部をＰｂＳ。From the viewpoint of heat resistance, the insulation film 1 is mainly made of polyimide, and rarely polyester or glass epoxy film. A copper foil wiring 2 is formed by bonding a copper foil to this insulating film using an adhesive and using a photoetching method. On top of this, paste the solder resist 3 on the film,
Also, an opening is provided at the bonding portion with the IC chip 4 by the photoetching method. Fill this opening with PbS.
等の溶融槽にデイツプするか、ｐｂｓ、等のペーストで
印刷する等により、バンブ構造の電極５をフィルム１上
に容易に形成することができる。この電極にＰｂＳイ等
の低融点の金属を用いることによりフィルム上からの熱
圧着でＩＣチップ４上の電極６と安定したボンディング
が可能となる。The electrode 5 having a bump structure can be easily formed on the film 1 by dipping it in a melting tank such as the like or by printing with a paste such as PBS. By using a metal with a low melting point such as PbS for this electrode, stable bonding with the electrode 6 on the IC chip 4 is possible by thermocompression bonding from above the film.
この熱圧着時には、ｐｂｓ、等金属表面を酸化させない
ように窒素ガス等の不活性ガス雰囲気中で行なう必要が
ある。This thermocompression bonding must be carried out in an atmosphere of an inert gas such as nitrogen gas so as not to oxidize the metal surface such as PBS.
以上の方法によればインナーリードな変形させることな
く、簡単にボンディングができる。According to the above method, bonding can be easily performed without deforming the inner lead.
第２図は本発明の他の実施例の縦断面図である。FIG. 2 is a longitudinal sectional view of another embodiment of the invention.
この実施例では銅箔配線２の内の１本から２つのバンプ
・電極５を形成することも可能となることを示したもの
である。これかられかる様に従来は周辺部のみに形成さ
れていた電極も、任意の場所に複数個のバンブ電極５を
可能とすることができ、ＩＣチップの設計にも、柔軟性
を持って行えるようになる。This example shows that it is also possible to form two bumps/electrodes 5 from one of the copper foil wirings 2. As you will see, it is now possible to form multiple bump electrodes 5 at any location, even though the electrodes were conventionally formed only on the periphery, allowing greater flexibility in the design of IC chips. become.
以上説明したように本発明は、絶縁フィルム上にインナ
ーリード部を設け、その上をフィルム上のソルダーレジ
ストで覆い、ボンディング部はソルダーレジストを開口
して、バブ構造上の電極５を設けることにより、インナ
ーリードが変形しない安定したボンディングが可能とな
る。また、１本の配線に複数のバンブ電極を絶縁フィル
ム上に形成することができ、ＩＣのチップの設計も非常
に柔軟に行えるという効果がある。合わせて、バンプ構
造の電極も簡単に製造ができるようになる効果もある。As explained above, the present invention provides an inner lead part on an insulating film, covers the inner lead part with a solder resist on the film, opens the solder resist in the bonding part, and provides the electrode 5 on the bubble structure. , it is possible to perform stable bonding without deforming the inner lead. Furthermore, a plurality of bump electrodes can be formed on one wiring on an insulating film, and the design of an IC chip can be done very flexibly. In addition, it also has the effect of making it easier to manufacture bump-structured electrodes.
第１図は本発明の半導体装置の縦断面図、第２図は本発
明のもう１つの実施例の縦断面図である。
ｌ・・・・・・絶縁フィルム（ポリイミド等）、２・・
・・・・銅箔配線、３・・・・・・フィルム状のソルダ
ーレジスト、４・・・・・・ＩＣチップ、５・・・・・
・バンプ構造の電極、６・・・・・・ＩＣチップの電極
、７・・・・・・ＩＣチップ上のバンブ電極。
代理人 弁理士 内 原 晋
、￥５１回
ｆｉ２−図FIG. 1 is a longitudinal sectional view of a semiconductor device of the present invention, and FIG. 2 is a longitudinal sectional view of another embodiment of the invention. l...Insulating film (polyimide, etc.), 2...
...Copper foil wiring, 3...Film-like solder resist, 4...IC chip, 5...
- Bump structure electrode, 6... Electrode of IC chip, 7... Bump electrode on IC chip. Agent: Susumu Uchihara, patent attorney, ¥51 Fi2-Figure
Claims (1)
フィルム状のソルダーレジストで覆い、かつＩＣチップ
とボンディングするインナーリード部のソルダーレジス
トに開口部を設け、この開口部に半田等の金属で突起状
電極を形成して、ＩＣチップと接続したことを特徴とす
る半導体装置。Copper foil wiring is formed on a tape-shaped insulating film, covered with a film-shaped solder resist, and an opening is provided in the solder resist of the inner lead part that will be bonded to the IC chip. A semiconductor device characterized in that a protruding electrode is formed and connected to an IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23550388A JPH0282544A (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23550388A JPH0282544A (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0282544A true JPH0282544A (en) | 1990-03-23 |
Family
ID=16986985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23550388A Pending JPH0282544A (en) | 1988-09-19 | 1988-09-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0282544A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09252023A (en) * | 1996-03-15 | 1997-09-22 | Nec Corp | Semiconductor device and its manufacturing method |
| US7420282B2 (en) | 2004-10-18 | 2008-09-02 | Sharp Kabushiki Kaisha | Connection structure for connecting semiconductor element and wiring board, and semiconductor device |
-
1988
- 1988-09-19 JP JP23550388A patent/JPH0282544A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09252023A (en) * | 1996-03-15 | 1997-09-22 | Nec Corp | Semiconductor device and its manufacturing method |
| US7420282B2 (en) | 2004-10-18 | 2008-09-02 | Sharp Kabushiki Kaisha | Connection structure for connecting semiconductor element and wiring board, and semiconductor device |
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