JPH0279613A - Automatic equalizer - Google Patents
Automatic equalizerInfo
- Publication number
- JPH0279613A JPH0279613A JP23321088A JP23321088A JPH0279613A JP H0279613 A JPH0279613 A JP H0279613A JP 23321088 A JP23321088 A JP 23321088A JP 23321088 A JP23321088 A JP 23321088A JP H0279613 A JPH0279613 A JP H0279613A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- automatic equalizer
- analog
- type automatic
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002592 echocardiography Methods 0.000 claims description 10
- 230000003111 delayed effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Landscapes
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】 〔概要〕 自動等化器に関し。[Detailed description of the invention] 〔overview〕 Regarding automatic equalizer.
周波数特性やりニアリテー等を改善するとともに、調整
も簡単に行えるようにすることを目的とし。The purpose is to improve frequency characteristics, linearity, etc., and to make adjustments easier.
進みエコーを等化するアナログ回路からなるトランスバ
ーサル形自動等化回路と、遅れエコーを等化するディジ
タル回路からなる判定帰還形自動等化回路とを具備し、
トランスバーサル形自動等化回路の遅ｆ：素子がアナロ
グ形サンプルホールド回路で構成され９判定帰還形自動
等化回路の遅延素子がフリップフロップ回路で構成され
る。Equipped with a transversal type automatic equalization circuit consisting of an analog circuit that equalizes leading echoes, and a decision feedback type automatic equalization circuit consisting of a digital circuit that equalizes delayed echoes,
The delay f: element of the transversal type automatic equalization circuit is constituted by an analog type sample-hold circuit, and the delay element of the 9-decision feedback type automatic equalization circuit is constituted by a flip-flop circuit.
本発明は自動環°花器に関する。 The present invention relates to an automatic flower vase.
自動等化器はフェージングあるいは符号量干渉等で生じ
る歪を補正するものである。この自動等化器は簡単かつ
安価に構成できることが要求されている。The automatic equalizer corrects distortion caused by fading or code amount interference. This automatic equalizer is required to be constructed easily and inexpensively.
ディジタル多重無線方式の受信機の復調回路における自
動等花器の従来の構成例が第３図に示される。この自動
等化器は直交変調方式用に！チャネル用とＱチャネル用
の二つの同一構成の５タツプのアナログ形トランスバー
サルフィルタ回路からなり、１チヤネルとＱチャネル間
での干渉も補償するように回路構成されている。FIG. 3 shows an example of a conventional configuration of an automatic oscilloscope in a demodulation circuit of a receiver using a digital multiplex radio system. This automatic equalizer is for quadrature modulation methods! It consists of two identical 5-tap analog transversal filter circuits, one for the channel and one for the Q channel, and is configured to compensate for interference between the 1 channel and the Q channel.
図中、４１〜４４はアナログ遅延素子、４５〜４９はｌ
チャネル用係数器、５０〜５４はＱチャネル補償用係数
器、５５は合成器、５６はへ／Ｄ変換器、５７は係数制
御回路であり、これらにより１チヤネル側の等化石が構
成される。なおＱチャネル側の等化石も同一構成となっ
ている。In the figure, 41 to 44 are analog delay elements, 45 to 49 are l
A channel coefficient unit, 50 to 54 are Q channel compensation coefficient units, 55 is a synthesizer, 56 is a to/D converter, and 57 is a coefficient control circuit, and these constitute an equalizer on the one channel side. Note that the isofossils on the Q channel side also have the same configuration.
この等化石は、遅延ライン４１〜４４によって各タップ
で信号を遅延させ、それに係数器４５〜４９で重み付け
をして加算合成し、その後に識別器５６で識別する完全
アナログ形の構成となっている。This equalizer has a completely analog configuration in which signals are delayed at each tap by delay lines 41 to 44, weighted by coefficient units 45 to 49, added and synthesized, and then discriminated by a discriminator 56. There is.
第３図の従来の完全アナログ形自動等化器は。 The conventional fully analog automatic equalizer shown in FIG.
アナログ回路構成であるため３周波数特性あるいはリニ
アリイー等が良くなく問題がある。また調整も節！ｎで
はなく、調整試験に時間がかかる。Since it has an analog circuit configuration, it has problems with poor three-frequency characteristics, linear E, etc. Adjustments are also a breeze! Adjustment test takes time, not n.
したがって本発明の目的は１周波数特性やリニ７リテー
等を改善するとともに、調整も簡単な自動等化器を提供
することにある。Therefore, an object of the present invention is to provide an automatic equalizer that improves the frequency characteristics, linearity, etc., and is easy to adjust.
第１図は本発明に係る原理ブロック図である。 FIG. 1 is a principle block diagram according to the present invention.
本発明に係る自動等化器は、進みエコーを等化するアナ
ログ回路からなるトランスバーサル形自動等化回路７０
と、遅れエコーを等化するディジタル回路からなる判定
帰還形自動等化回路８０とを具備し、トランスバーサル
形自動等化回路７０の遅延素子７１１〜７１ｎがアナロ
グ形サンプルホールド回路で構成され２判定帰還形自動
等化回路８０のａｔ＝素子８１１〜８１ｎがフリップフ
ロップ回路で構成される。The automatic equalizer according to the present invention includes a transversal automatic equalizer circuit 70 consisting of an analog circuit that equalizes leading echoes.
and a decision feedback type automatic equalization circuit 80 consisting of a digital circuit that equalizes delayed echoes. The at=elements 811 to 81n of the feedback automatic equalization circuit 80 are constituted by flip-flop circuits.
本発明の自動等化器では進みエコーはアナログ回路構成
のトランスバーサル形自動等化回路７０で等化され、一
方、遅れエコーはディジタル構成の判定帰還形自動等化
回路８０で等化される。このように自動等化器の半分の
回路構成がディジタル回路化されることにより９回路構
成が簡単となりまた安価となる。さらにディジタル回路
であるため調整も簡単化される。In the automatic equalizer of the present invention, leading echoes are equalized by a transversal type automatic equalization circuit 70 having an analog circuit configuration, while delayed echoes are equalized by a decision feedback type automatic equalization circuit 80 having a digital configuration. By converting half of the circuit configuration of the automatic equalizer into digital circuits in this way, the nine circuit configuration becomes simple and inexpensive. Furthermore, since it is a digital circuit, adjustment is also simplified.
以下９図面を参照しつつ本発明の詳細な説明する。第２
図は本発明の一実施例としての自動等化器を示すブロッ
ク図である。この実施例装置は多値ＱＡＭ変調方式ディ
ジタル多重無線受信機の復調回路における自動等化器に
本発明を通用した例であり、■チャネル用とＱチャネル
用の同一構成の５タツプ形の等化石からなっている。The present invention will be described in detail below with reference to nine drawings. Second
The figure is a block diagram showing an automatic equalizer as an embodiment of the present invention. This embodiment is an example in which the present invention is applied to an automatic equalizer in a demodulation circuit of a multilevel QAM modulation digital multiplex radio receiver. It consists of
図中、サンプルホールド回路ｌ、２．タップ係数器３〜
８．および合成器９は進みエコーを等化するアナログ回
路のトランスバーサル形自動等化１１路を構成する。サ
ンプルホールド回路１．２は同期検波されたアナログ信
号からなる■チャネル信号をｌシンボルずつ順次にサン
プルホールドする回路である。。In the figure, sample and hold circuits 1, 2. Tap coefficient unit 3~
8. The synthesizer 9 constitutes a transversal type automatic equalization circuit 11 of analog circuitry for equalizing the leading echo. The sample and hold circuit 1.2 is a circuit that sequentially samples and holds a (1) channel signal consisting of a synchronously detected analog signal one symbol at a time. .
係数３３〜５は■チャネル信号用のタップ係数器であり
、それぞれタップ係数Ｃ２＋ Ｃ−１＊ ＣＯをサ
ンプルホールド回路１．２の人出力信号に乗じる。係数
器６〜８はＩチャネルからＱチャネルへの干渉信号をＱ
チャネル側等化回路で補償する補償信号を発生するため
のタップ係数器であり。Coefficients 33 to 5 are tap coefficient multipliers for channel signals, each of which multiplies the human output signal of the sample and hold circuit 1.2 by a tap coefficient C2+C-1*CO. The coefficient multipliers 6 to 8 convert the interference signal from the I channel to the Q channel into a Q
This is a tap coefficient generator for generating a compensation signal to be compensated by the channel side equalization circuit.
それぞれサンプルホールド回路１．２の入出力にタップ
係数ｏ−ｚ＋ Ｄ−、、Ｄｏを乗じる。The input and output of the sample and hold circuits 1.2 are respectively multiplied by tap coefficients oz+D-, , Do.
合成器９は係数器３〜５の出力信号を加算合成すると共
に、Ｑチャネル用等化回路の係数器２６〜２８からのＱ
チャネル干渉補償信号も加算合成する。この結果の合成
信号は減算器ｌＯに送出される。The synthesizer 9 adds and synthesizes the output signals of the coefficient units 3 to 5, and also combines the output signals of the coefficient units 26 to 28 of the Q channel equalization circuit.
Channel interference compensation signals are also added and combined. The resulting composite signal is sent to subtractor lO.
一方、減算器１０．Ａ／Ｄ変換器からなる判定器１１．
フリップフロップからなる遅延器１２゜１３、係数器１
４〜１７．および合成器１８はディジタル回路からなる
判定帰還形（デイシジョン・フィードバック形）自動等
化回路を構成する。On the other hand, subtractor 10. Determiner 11 consisting of an A/D converter.
Delay unit 12゜13 consisting of flip-flop, coefficient unit 1
4-17. The synthesizer 18 constitutes a decision feedback type automatic equalization circuit consisting of a digital circuit.
ここでフリップフロップ１２．１３は判定器１１ノＦＩ
定結果をｌシンボルずつ順次に保持する。Here, the flip-flops 12 and 13 are the FI of the determiner 11.
The results are held sequentially for each l symbol.
係数器１４．１５は■チャネル信号用のタップ係数器で
あり、それぞれ入力信号にタップ係数ｃ、、ｃ２を乗算
する。一方、係ｋＷ１６．１７はＱチャネル側等化回路
用の干渉補償信号を発生ずるタップ係数器であり、入力
信号にタップ係数り、、Ｄ２を乗じる０合成回路１８は
係数器１６゜１７の出力信号を加算合成すると共に、Ｑ
チャネル側等化回路の係数器３６．３７からの補償信号
を加算合成し、それらの加算結果を減算器ｌＯに送出す
る。減算器１０は合成器９の出力信号から合成器１８の
出力信号を減算し、その結果を判定器１１に送出する。The coefficient multipliers 14 and 15 are tap coefficient multipliers for channel signals, and multiply the input signals by tap coefficients c, , c2, respectively. On the other hand, the coefficient kW16.17 is a tap coefficient multiplier that generates an interference compensation signal for the Q channel side equalization circuit, and the zero synthesis circuit 18 that multiplies the input signal by the tap coefficient and D2 is the output of the coefficient multiplier 16.17. While adding and combining the signals, Q
The compensation signals from the coefficient units 36 and 37 of the channel-side equalization circuit are added and combined, and the result of their addition is sent to the subtracter IO. The subtracter 10 subtracts the output signal of the combiner 18 from the output signal of the combiner 9 and sends the result to the determiner 11.
Ｑチャネル側の自動等化回路もｌチャネル側等化回路と
全く同じ構成となっており、サンプルホールド回路２１
．２２．係数器２３〜２８．３４〜３７９合成器２９．
３８．減算器３０９判定器３１、フリソプフロフプ３２
．３３等を含み構成される。The automatic equalization circuit on the Q channel side has exactly the same configuration as the equalization circuit on the L channel side, and has a sample and hold circuit 21.
．． 22. Coefficient units 23-28. 34-379 synthesizer 29.
38. Subtractor 309 Determiner 31, Frisopflop 32
．． It is composed of 33 etc.
係数側御回路３９は判定器１１．３２の判定結果に基づ
き１等化器内の各タップ係数器のタップ係数Ｃ−２〜Ｃ
２＋Ｄ−２〜Ｄ２を■チャネルとＱチャネルについてそ
れぞれ求めて、各タップ係数器に係数￥ＩＩ御信号とし
て供給するものである。The coefficient side control circuit 39 determines the tap coefficients C-2 to C of each tap coefficient unit in the 1 equalizer based on the determination result of the determiner 11.32.
2+D-2 to D2 are obtained for the ■ channel and the Q channel, respectively, and are supplied to each tap coefficient unit as a coefficient \II control signal.
以上の構成によれば、進みエコーはアナログ回路のトラ
ンスバーサル形等化回路で等化され、遅れエコーはディ
ジタル回路の判定帰還形振化回路で等化されるようにな
る。この結果３等化器の回路の半分はディジタル回路構
成とすることが可能となる。According to the above configuration, leading echoes are equalized by the transversal type equalization circuit of the analog circuit, and delayed echoes are equalized by the decision feedback type oscillation circuit of the digital circuit. As a result, half of the circuit of the 3-equalizer can be configured as a digital circuit.
本発明によれば自動等化石の回路の半分はディジタル回
路構成とすることができ、これにより回路を簡単化しか
つ安価にすることができ、また調整試験も簡単に行える
ようになる。According to the present invention, half of the circuitry of the automatic isolator can be configured as a digital circuitry, which makes the circuitry simple and inexpensive, and also allows for easy adjustment testing.
第１図は本発明に係る原理ブロック図。
第２図は本発明の一実施例としての自動等化器を示すブ
ロック図、および。
第３図は従来の自動等化器の構成例を示すブロック図で
ある。
図において。
１．２．２１．２２ヘ一サンプルホールド回路３〜８．
１４〜７，２３〜２８．３４〜３７゜４５〜５４．６５
〜７４−タップ係数器９．１Ｂ、２９．３８，５５．７
５・−合成器１０．３０−−一減算器
１１．３１．５６．７６・＝Ａ／Ｄ変換器１２．１３．
３２．３３−・・フリップフロップ３９．５７−−−−
係数制御回路FIG. 1 is a principle block diagram according to the present invention. FIG. 2 is a block diagram showing an automatic equalizer as an embodiment of the present invention; FIG. 3 is a block diagram showing an example of the configuration of a conventional automatic equalizer. In fig. 1.2.21.22 Sample and hold circuits 3 to 8.
14~7, 23~28.34~37°45~54.65
~74-Tap coefficient unit 9.1B, 29.38, 55.7
5.-Synthesizer 10.30--Subtractor 11.31.56.76.=A/D converter 12.13.
32.33--Flip-flop 39.57----
Coefficient control circuit
Claims (1)
ーサル形自動等化回路（７０）と、遅れエコーを等化す
るディジタル回路からなる判定帰還形自動等化回路（８
０）と を具備し、 該トランスバーサル形自動等化回路（７０）の遅延素子
（７１＿１〜７１＿ｎ）がアナログ形サンプルホールド
回路で構成され、 該判定帰還形自動等化回路（８０）の遅延素子（８１＿
１〜８１＿ｎ）がフリップフロップ回路で構成されたこ
とを特徴とする自動等化器。[Claims] A transversal type automatic equalization circuit (70) consisting of an analog circuit that equalizes leading echoes, and a decision feedback type automatic equalization circuit (80) consisting of a digital circuit that equalizes delayed echoes.
0), the delay elements (71_1 to 71_n) of the transversal automatic equalization circuit (70) are configured with analog sample-hold circuits, and the delay elements of the decision feedback automatic equalization circuit (80) (81_
1 to 81_n) are configured with flip-flop circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23321088A JPH0279613A (en) | 1988-09-16 | 1988-09-16 | Automatic equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23321088A JPH0279613A (en) | 1988-09-16 | 1988-09-16 | Automatic equalizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0279613A true JPH0279613A (en) | 1990-03-20 |
Family
ID=16951483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23321088A Pending JPH0279613A (en) | 1988-09-16 | 1988-09-16 | Automatic equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0279613A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100467528B1 (en) * | 2002-09-10 | 2005-01-24 | 주식회사 버카나와이어리스코리아 | High-speed adaptive Equalizer |
| JP2012147079A (en) * | 2011-01-07 | 2012-08-02 | Fujitsu Ltd | Reception circuit and electronic apparatus |
-
1988
- 1988-09-16 JP JP23321088A patent/JPH0279613A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100467528B1 (en) * | 2002-09-10 | 2005-01-24 | 주식회사 버카나와이어리스코리아 | High-speed adaptive Equalizer |
| JP2012147079A (en) * | 2011-01-07 | 2012-08-02 | Fujitsu Ltd | Reception circuit and electronic apparatus |
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