KR100467528B1 - High-speed adaptive Equalizer - Google Patents

Abstract

The present invention is to provide a high-speed adaptive equalizer to enable high-speed operation while minimizing the influence of noise by configuring a component that requires high-speed processing is composed of an analog circuit and a component that should be less affected by noise. will be. To this end, the fast adaptive equalizer of the present invention implements an LMS adaptive signal processing algorithm in an analog circuit and a digital circuit to compensate for the distortion of a signal received through a transmission line and inter-symbol interference noise. Multiplication, addition and subtraction between these delay signals and the adaptive tap variables are implemented using at least one analog circuit, and the conversion of the adaptive tap variables is implemented using at least one digital circuit.

Description

High-speed adaptive equalizer

The present invention relates to an adaptive equalizer, and more particularly, to a high speed adaptive equalizer configured to perform a high speed signal processing by mixing an analog circuit and a digital circuit.

1 is a view schematically showing a general communication system. After converting the low speed parallel data from the serializer 10 to the high speed serial data, the transmission driver 12 transmits the data through the channel 14, and the data transmitted through the channel 14 is received by the reception driver 16. ) Is converted into parallel data by the parallelizer 18 and outputted. The serial data output from the serializer 10 is a signal having a magnitude (for example, ± 5V) as shown in FIG. 2A, and serial data output from the transmission driver 12 to the channel 14. Is a signal having a magnitude leveled (e.g., ± 1V) as shown in FIG. 2B (where, the voltage levels of ± 5V and ± 1V may vary depending on the application). The signal of FIG. 2B generates noise while passing through the channel 14 and a bandwidth reduction phenomenon is distorted into a signal as shown in FIG. 2C to reach the reception driver 16. The reception driver 16 restores the distorted signal to the original signal as shown in FIG. 2A using an adaptive equalizer.

That is, in order to compensate for signal distortion and inter-noise interference noise generated on a transmission line, a receiver uses a least mean square (LMS) adaptive equalizer.

3 shows a schematic of the LMS algorithm. The received signal x (n) is multiplied by the tap variable c ₀ (n) in the multiplier 20 and the signals x (n-1) to x (nk) delayed by 1 to k bits respectively in the delay units 42 to 52 are Each multiplier 40-50 is multiplied by the tap variables c ₁ (n) to c _k (n), respectively, and then added to each other in the adder 22 to produce a calculation signal y (n). This calculation signal y (n) is sampled by the digitizer 24 and converted into a digital value. The desired signal d (n) is made from this digital value and the subtractor 26 calculates the difference from the calculated signal y (n) to produce the error signal ε (n). The error signal ε (n) and the received signal x (n) are multiplied by the multiplier 28 and the adaptive constant μ is multiplied by the amplifier 30 and then added to the tap variable C ₀ (n) in the adder 32. To change the tap variable. In addition, the error signal ε (n) and the signal x (n-1) to x (nk) delayed by 1 to k bits are respectively multiplied by the multipliers 34 to 44, and the adaptive constant μ is added to the amplifiers 36 to 34, respectively. After multiplying at 46), the tap parameters are changed by adding them to tap variables C ₁ (n) to C _k (n) in adders 38 to 48, respectively. The conversion expression of these tab variables is as follows.

here, to be.

Conventional methods for implementing adaptive equalizers can be broadly divided into digital and analog methods. The digital adaptive equalizer converts the input signal into a digital signal using an analog-to-digital converter, and then digitally implements equalization and adaptive tap variable conversion. This method has the advantage of being almost insensitive to noise or environmental changes because it implements the adaptive algorithm digitally. However, this method is not suitable for equalizing high-speed signals because it requires a high-speed high-resolution A / D converter, a digital adder, a digital multiplier, and the like, because the hardware for implementation and the speed are slow.

In contrast, the analog adaptive equalizer uses both analog equalization and adaptive tap variable conversion of the signal. This method enables signal equalization and adaptive tap variable conversion in real time, making it ideal for high-speed signal equalization. However, all circuits are implemented in an analog manner, which is a weak point in noise and changes in operating environment.

Because of the simple implementation, the LMS adaptive equalization algorithm has long been used in many fields such as broadcasting signal compensation and wireless signal compensation as well as communication transmission line compensation. In particular, digital equalizers have been used in many applications because they are noise resistant. The magnitude of the received signal by converting the analog signal received through the transmission line into a corresponding digital signal, sequentially delaying the data at regular intervals, and multiplying the sequentially delayed data by an adaptation coefficient and a data adaptation coefficient corresponding to automatic gain control. Since the equalizer (patent application No. 194-0017007) of the method of adjusting the output to a predetermined level and outputting the waveform equalized, was developed by the digital signal processor to recover the data transmitted to the receiving device in the simultaneous broadcasting communication system, the feedback feedback equalizer ( Patent Application No. 1996-7001445) was also implemented. An adaptive equalizer (Patent Application No. 1998-0038050) that improves the trade-off problem between the mean square error (MSE) value and the convergence speed according to the adaptation constant value of the conventional adaptive filter has also been released. An adaptive equalizer (Patent Application No. 1999-0003929) was also developed.

However, these digital adaptive equalizers are not suitable for high-speed signal equalization due to the delay in the digital conversion and adaptive equalization of data due to the complicated operation speed of the digital circuit. Therefore, analog equalizers have been developed and used in storage applications or optical communications where high-speed signal equalization is required (Patrick Arm and others, A 160MHz Front-End IC for EPR-IV PRML Magnetic-Storage Read Channel, ISSCC, pp68-). 69, Feb. 1996; Nicholas P. Sand et al., 8 persons, A 200 Mb / s Analog DFE Read Channel, ISSCC, pp72-73, Feb. 1996; Roberto Alini and 24 others, A 200-Msamples / s Trellis-Coded PRML Read / Write Channel with Analog Adaptive Equalizer and Digital Servo, IEEE Journal of Solid State Circuits, Vol. 32, No. 11, pp1824-1838, Nov. 1999; James I. Brown et al., A CMOS Adaptive Continuous-Time Forward Equalizer, LPF, and RAM-DFE for Magnetic Recording, IEEE Journal of Solid State Circuits, Vol. 34, No. 2, Feb. 1999). However, this analog equalizer is also sensitive to noise, which makes it difficult to implement.

The present invention has been made to solve the above-mentioned problems, the components that need high-speed processing is composed of analog circuits and components that should be less affected by noise are composed of digital circuits, while minimizing the effects of noise It is an object of the present invention to provide a high speed adaptive equalizer capable of high speed operation.

1 schematically shows an optical communication system,

2a to 2c exemplarily show signal waveforms in the main part of FIG. 1;

3 is a conceptual diagram of an adaptive equalizer of a least mean square (LMS) scheme;

4 is a block diagram of a fast adaptive equalizer according to the present invention;

5 is a detailed block diagram of the amplifier circuit of FIG.

6 is a detailed block diagram of a delay line of FIG. 3;

7 is a signal waveform diagram of FIG. 6.

※ Explanation of code for main part of drawing

60_1 ~ 60_k: Delay line 62_1 ~ 62_k: Delay cell

64_1 ~ 64_k: Delay cell 66: Phase-frequency comparator

68: charge pump 70: amplifier

72_0 ~ 72_k: Input terminal 74_0 ~ 74_k: Bias stage

76: output load 80: latch

82: Transmitter modeler 84_0 ~ 84_k: Error comparator

86_0 ~ 86_k: Charge pump

In order to achieve the above object, a fast adaptive equalizer according to a preferred embodiment of the present invention uses an LMS adaptive signal processing algorithm to compensate for distortion of a signal received through a transmission line and interference noise between symbols. It is characterized by the implementation.

The delay of the received signal and the multiplication, addition and subtraction between the delay signals and the adaptive tap variables are implemented using at least one analog circuit, and the conversion of the adaptive tap variables is implemented using at least one digital circuit.

To adjust the delay time of the received signal, a phase-frequency comparator and a charge pump are used to control the delay control voltage of the delay cell.

And an amplifier having multiple input stages, multiple bias stages, and one output load for multiplying, adding, and subtracting the adaptive tap variable and the delay signal.

After converting the analog calculation signal, which is the output of the amplifier, into a digital value, a transmitter modeler is installed to make a target voltage suitable for the value.

An error comparator for outputting a difference between the received signal voltage and the target voltage as an output value, and a charge pump circuit operated by the output value of the error comparator are used to control any one of the output voltage and the output current of the charge pump circuit. Change the variable.

By changing any one of the voltage and the current of the bias stage, the amplification degree of the amplifier is changed to adjust the value of the adaptive tap variable when the adaptive tap variable and the delay signal are multiplied.

The amplifier uses an input of a differential or single delay signal to multiply the adaptive tap variable and the delay signal.

The amplifier outputs a differential or disconnection calculation signal generated from the multiplication of each adaptive tap variable and delay signal and the addition and subtraction of the result.

Hereinafter, a high speed adaptive equalizer according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

The present invention intends to use an analog-digital hybrid scheme to overcome the shortcomings of the conventional digital equalizer and the analog equalizer. To do this, we implemented a sign-sign LMS algorithm. In this method, the equalization of the received signal is implemented in an analog manner and the adaptive tap variable conversion is implemented in a digital manner. For this purpose, only the error signal and the sign of the received signal are used. By doing so, the present invention is capable of equalizing high-speed signals, which is an advantage of analog, and has adaptive digital variable variable conversion, which has digital advantages. The tap conversion equation of the sine-sign LMS algorithm is as follows.

An analog-digital hybrid adaptive equalizer according to the present invention that implements this is shown in FIG.

The equalizer of the present invention includes an amplifier 70 for equalizing a received signal, a latch 80 for data sampling, a transmission stage modeler 82 for generating a signal before passing the transmission line, and several adaptive tap variable conversion circuits 84_0. , 86_0) (60_1,84_1,86_1)… It consists of (60_k, 84_k, 86_k). Each adaptive tap variable conversion circuit 84_0, 86_0 (60_1, 84_1, 86_1). 60_k, 84_k, 86_k) is composed of delay lines 60_1 to 60_k, error comparators 84_0 to 84_k, and charge pumps 86_0 to 86_k. Among them, the amplifier 70 and the delay lines 60_1 to 60k are implemented as analog circuits, and other portions of the amplifier 70 and the delay line 60_1 to 60k are latch 80, the transmission stage modeler 82, the error comparator 84_0 to 84_k, and the charge pump 86_0 to 60. 86_k) is digitally implemented.

In the adaptive equalizing receiver, the amplifier 70 performs an equalizing function of multiplying each bit variable by a bit delayed delay signal and adding the multiplyed tap variable to generate a calculated signal. That is, as shown in Fig. 5, the input signal x (n) and the delayed signals x (n-1) to x (nk) delayed by 1 to K bits are input to the input terminals 72_0 to 72_k of the amplifier 70, respectively. The bias voltages C ₀ to C _k , which are outputs of the respective charge pumps 86_0 to 86_k, are respectively applied to the bias stages 74_0 to 74_k of the amplifier 70. Input signals x (n) and respective delay signals x (n-1) to x (nk) are connected to the input terminals 72_0 to 72_k of the amplifier 70, and the bias terminals 74_0 to 72_k connected to the input terminals 72_0 to 72_k. The bias voltage of 74_k) serves as a tap variable to determine the amplification degree of each input stage. The signals amplified by the tap bias voltage are added or subtracted from one output load stage 76 to generate an estimated signal. The bias voltage of each input terminal 72_0 to 72_k that determines the tap variable is connected to the output of the charge pump circuit 86_0 to 86_k for tap variable conversion.

A delay circuit is used for the bit delay of the received signal. Only a delay line without feedback can be used for a simple implementation, but this delay circuit has a big disadvantage in that the delay time is changed by a change in the manufacturing process. In order to overcome this problem, the present invention designed a delay circuit using a delay time control technique of a delay lock loop (DLL).

6 is a configuration diagram of the delay line. As shown in the figure, the delay times of the delay cells 62_1 to 62_k and 64_1 to 64_k are controlled by the delay control voltage, which is made in the same way as to generate the delay control voltage of the delay cells of the DLL. . That is, delay cells [64_1,... Compare the phase of the reference phase clock signal passing through the delay line consisting of 64_ (k-1), 64_k] with a k-bit delayed clock signal having a phase delayed by a desired k-bit time in the phase-frequency comparator 66 and accordingly By generating an up / down signal to control the delay control voltage of the charge pump circuit 68, the delay line has a delay time exactly as desired bit time. By doing so, it is possible to minimize a change in delay time due to a change in manufacturing process or a change in operating environment. Here, a k bit delay does not mean that the number of delay cells is k, and a k bit delay can be generated even with one delay cell.

Here, the k-bit delay clock signal and the reference phase clock are clock signals having a frequency lower than that of the input bit clock signal generated in synchronization with the input signal, and use a clock divided by 10 times than the input bit clock signal. For example, in a delay line that delays an input signal by one bit, a delay clock signal that is delayed by one bit based on the input bit clock signal and an arbitrary number of delay cells (four-bit delay does not use one delay cell, namely You can use any number of delay cells, such as five or ten, and adjust the delay control voltages of these delay cells to create an arbitrary delay, such as one or four bits. By comparing the frequency comparator 66, the up / down signal is output to the charge pump circuit 68 to control the delay control voltage of the charge pump circuit 68 so that the input signal is exactly 1 bit time in any number of delay cells. The output will be delayed.

For example, in the delay line for delaying the input signal by 4 bits, a 4-bit delay clock signal in which the reference phase clock is delayed 4 bits based on the input bit clock signal as shown in FIG. 7, and delayed in any number of delay cells. The reference phase clock signal is compared by the phase-frequency comparator 66 to output the up / down signal to the charge pump circuit 68 to control the delay control voltage of the charge pump circuit 68 so that the input signal has four delay cells. Will be output with a delay of exactly 4 bits.

As described above, the delay lines 60_1 to 60_k are individually designed in the manner as shown in FIG. 6 according to the respective delay characteristics, so that the input signal is delayed and outputted exactly as desired.

The circuit required for the LMS tap conversion includes an adaptive tap conversion composed of a sampling latch 80, a transmission model modeler 82, a delay line 60_1 to 60_k, an error comparator 84_0 to 84_k, and a charge pump 86_0 to 86_k. There is a circuit. The sampling latch 80 in FIG. 4 serves to sample the calculated signal output from the amplifier 70 and convert it to a digital value. The transmitter modeler 82 generates a transmitter signal when the digital value from the sampling latch 80 does not pass through the transmission line to produce a target signal that the calculation signal should have. The error comparators 84_0 to 84_k compare the calculation signal generated by the amplifier 70 with the target signal generated by the transmission model modeler 82 to generate a digitally encoded error value. This value is multiplied by the digital value of the delay signal from the delay lines 60_1 to 60_k to produce the charge pump drive signal. The charge pumps 86_0 to 86_k change the output voltages of the charge pumps 86_0 to 86_k according to the values produced by the error comparators 84_0 to 84_k to change the tap variable by controlling the bias voltage of the amplifier 70. The amount of change in the output voltage of the charge pumps 86_0 to 86_k determines the adaptation constant.

On the other hand, the present invention is not limited to the above-described typical preferred embodiment, it can be carried out in various ways without departing from the gist of the present invention various modifications, changes, substitutions or additions in the art Anyone who has this can easily understand it. If the implementation by such improvement, change, replacement or addition falls within the scope of the appended claims, the technical idea should also be regarded as belonging to the present invention.

As described in detail above, according to the present invention, the delay line and the amplifier requiring the high-speed processing are composed of analog circuits, and the latches, transmission stage modelers, error comparators, and charge pumps, which should be less affected by noise, are composed of digital circuits. It is possible to operate at high speed while minimizing the impact.

Claims (9)

In order to compensate for the distortion of the signal received through the transmission line and the inter-symbol interference noise, a LMS (Least Mean Square) adaptive signal processing algorithm is used, and the delay of the received signal and the multiplication between the delayed signals and the adaptive tap variables Addition and subtraction are implemented using at least one analog circuit, and conversion of the adaptive tap variable is implemented using at least one digital circuit, The analog circuit controls a delay control voltage of a delay cell using a phase-frequency comparator and a charge pump to adjust the delay time of the received signal, and the digital circuit multiplies and adds the adaptive tap variable and the delay signal. High speed adaptive equalizer comprising an amplifier with multiple input stages, multiple bias stages and one output load for subtraction. delete delete delete The method of claim 1, And a transmission stage modeler is installed to convert the analog calculation signal, which is the output of the amplifier, to a digital value and then make a target voltage suitable for the value. The method of claim 5, An error comparator for outputting a difference between the received signal voltage and the target voltage as an output value, and a charge pump circuit operated by the output value of the error comparator are used to control any one of the output voltage and the output current of the charge pump circuit. Fast adaptive equalizer characterized by varying parameters. The method of claim 1, And changing the amplification degree of the amplifier by changing any one of the voltage and the current of the bias stage to adjust the value of the adaptive tap variable when the adaptive tap variable and the delay signal are multiplied. The method of claim 1, The amplifier is a high-speed adaptive equalizer, characterized in that the input of the differential or single delay signal to the input stage for multiplying the adaptive tap variable and the delay signal. The method of claim 1, And the amplifier outputs a differential or disconnection calculation signal generated from the multiplication of each adaptive tap variable and a delay signal and the addition and subtraction of the result.