JP2012147079A - Reception circuit and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area and power consumption of a reception circuit in an electronic apparatus.SOLUTION: The reception circuit includes: a plurality of sampling circuits (SWs) for sampling received data at different timings; a plurality of hold circuits (C) for holding the respective data sampled by the plurality of sampling circuits; parameter calculation circuits (70, 72, 74) for calculating parameters for determining the degree of equalization and interpolation of the input signal in accordance with outputs from the plurality of hold circuits; a weighting circuit (76) for weighting the outputs of the plurality of hold circuits according to the parameters calculated by the parameter calculation circuits; and an output circuit (N3) for combining and outputting the output data from the hold circuits weighted by the weighting circuit.

Description

  The present invention relates to a receiving circuit and an electronic device including the receiving circuit.

  In a receiving circuit of an electronic device capable of high-speed data transfer, it is known to perform equalization and interpolation of input data in order to correct signal degradation due to a transmission line. For example, the received signal is converted from a voltage signal to a current signal by the Gm cell, and the outputs at different timings of the two Gm cells are subtracted, so that the data in the previous stage of the analog-to-digital converter (ADC) A method for performing equalization is known. In addition, a method of performing data interpolation by digital signal processing in a subsequent stage of the analog-digital conversion circuit is known.

TinaTahmoureszadeh, Siamak Sarvari, Ali Sheikholeslami, Hirotaka Tamura, YasumotoTomita, Masaya Kibune “A Combined Anti-Aliasing Filter and 2-tap FFE in 65-nmCMOS for 2x Blind 2-10 Gb / s ADC-Based Receivers”

  In the conventional switch circuit, since the circuit for performing data interpolation is provided after the ADC separately from the circuit for performing data equalization, the circuit area may increase. In addition, in order to suppress quantization noise when performing data interpolation (and equalization) by digital signal processing, an ADC capable of high-resolution and high-speed operation is required, which increases circuit area and power consumption. There was a case.

  The present invention has been made in view of the above problems, and an object thereof is to reduce the area and power consumption of a receiving circuit in an electronic device capable of high-speed data transfer.

  The receiving circuit is based on a plurality of sampling circuits that sample received data at different timings, a plurality of hold circuits that hold the respective data sampled by the plurality of sampling circuits, and outputs from the plurality of hold circuits. A parameter calculation circuit for calculating a parameter for determining the degree of equalization and interpolation of the input signal, and a weight for each output of the plurality of hold circuits based on the parameter calculated by the parameter calculation circuit A weighting circuit for performing the output, and an output circuit for combining and outputting the output data of the hold circuit weighted by the weighting circuit. The electronic apparatus includes the receiving circuit and an analog-digital conversion circuit connected to a subsequent stage of the receiving circuit.

  According to this electronic circuit, the area and power consumption of the receiving circuit in the electronic device can be reduced.

FIG. 1 is a block diagram of an electronic apparatus according to the first embodiment. FIG. 2 is a block diagram of a receiving circuit according to the first embodiment. FIG. 3 is a diagram for explaining data equalization. FIG. 4 is a diagram for explaining data interpolation. FIG. 5 is a diagram illustrating a detailed configuration of the receiving circuit according to the first embodiment. FIG. 6 is a diagram illustrating the operation of the receiving circuit according to the first embodiment. FIG. 7 is a diagram illustrating changes in voltage. FIG. 8 is a diagram showing a configuration of a sampling clock switching circuit. FIG. 9 is a diagram illustrating a detailed configuration of the receiving circuit according to the second embodiment. FIG. 10 is a diagram illustrating the operation of the receiving circuit according to the second embodiment. FIG. 11 is a diagram illustrating a detailed configuration of the receiving circuit according to the third embodiment. FIG. 12 is a diagram illustrating the operation of the receiving circuit according to the third embodiment. FIG. 13 is a diagram illustrating the configuration of the receiving circuit according to the fourth embodiment.

FIG. 1 is a block diagram of an electronic apparatus according to the first embodiment. A plurality of CPUs (Central Processing Units) 10 as arithmetic means are arranged. Around the CPU 10, there is an HSIO (High Speed
A plurality of high-speed input / output circuits 20 indicated by “Input Output” are arranged. The high-speed input / output circuit 20 is connected to an external input / output interface (not shown), and plays a role of realizing high-speed data transfer between the CPU 10 and the input / output interface.

  FIG. 2 is a block diagram of a receiving circuit in the high-speed input / output circuit 20. The received signal (DATA IN) is input to the sample and hold circuit 30. The sample and hold circuit 30 includes a gm cell 32 for converting a voltage signal into a current signal, and a sample and hold unit 34 for sampling and holding (holding) data. A plurality of sample hold units 34 are provided as many as the number of input channels.

  The sample hold unit 34 includes a sampling switch SWs used for sampling data, a reset switch SWr used for resetting the circuit, and a capacitor bank CB connected to these switches. In the sample and hold circuit 30, the input signal is first input to the gm cell 32, converted into a current signal, and then output to the sample and hold unit 34. Various clock signals are input to the sample hold unit 34 from the clock generation circuit 40 indicated by CK_Gen. The output data of the sample hold circuit 30 is input to an analog digital converter (ADC) 50 in the subsequent stage.

  The output data of the ADC 50 is input to the digital signal processing circuit 60 at the subsequent stage. The digital signal processing circuit 60 executes various arithmetic processes based on the received signal converted into a digital signal by the ADC 50. Output data (DATA OUT) of the digital signal processing circuit 60 is output from the output terminal of the receiving circuit to the internal circuit of the electronic device, and is also input to the equalization control circuit 70 and the phase detection circuit 72.

  The equalization control circuit 70 calculates a deviation from the ideal value of the amplitude of the received signal based on the output data of the digital signal processing circuit 60, and calculates a parameter y for correcting this by equalization. More specifically, since the equalization operation has a high-pass characteristic, the parameter y is determined so as to reduce the DC level of the output data and amplify the AC level corresponding to the data band at an appropriate place. The phase detection circuit 72 calculates a deviation from the ideal value of the sampling phase of the received signal based on the output data of the digital signal processing circuit 60. A filter circuit 74 provided at the subsequent stage of the phase detection circuit 72 calculates a parameter x for correcting the sampling phase shift by interpolation. More specifically, in the interpolation operation, it is detected whether or not the output data deviates from the phase center calculated by the digital circuit side, and the value of the parameter x is determined so as to correct the deviation. . The output parameter y of the equalization control circuit 70 and the output parameter x of the filter circuit 74 are input to the encoder 76, respectively. However, “0 <x, y <1”. As described above, the equalization control circuit 70, the phase detection circuit 72, and the filter circuit 74 are parameter calculation circuits that calculate parameters for determining the degree of equalization and interpolation of the input signal to the reception circuit. Good.

  The encoder 76 encodes the digital parameters given from the equalization control circuit 70 and the filter circuit 74 and supplies the encoded digital parameters to the capacitor bank CB of each sample and hold unit 34. This signal may be a signal for weighting the output of each sample and hold unit 34, and the encoder 76 may be a weighting circuit for performing the weighting.

  FIG. 3 is a diagram for explaining data equalization. FIG. 3A shows a signal waveform before equalization, and FIG. 3B shows a signal waveform after equalization. As shown in FIG. 3A, the output data of the ADC 50 at a certain timing is d1, d2, d3, and d4. d1 and d4 indicate the DC level of the output, and d2 and d3 indicate the AC level of the output. Here, if the AC level representing d2 and d3 is low, it is difficult to determine whether the data is 1 or 0. Therefore, the parameter is adjusted so that the high-pass characteristic of equalization can be obtained, the amplitude of the DC level representative of d1 and d4 is reduced, and the amplitude of the AC level representative of d2 and d3 is amplified to be 1 or 0. Make it easier to distinguish. As shown in FIG. 3B, the equalization parameter (y) is calculated so that the equalized data becomes d1 ′, d2 ′, d3 ′, and d4 ′, and is fed back to the sample and hold circuit 30. The

  FIG. 4 is a diagram for explaining data interpolation. 4 (a) and 4 (b) show signal waveforms before interpolation, FIG. 4 (a) shows a state in which the data phase is delayed, and FIG. 4 (b) shows a state in which the data phase is advanced. Respectively. FIG. 4C shows a signal waveform after data interpolation. In FIG. 4A, the phase of data is delayed with respect to the center (EC: Edge Center), and the data discrimination is d1 = 0, d2 = 0, d3 = 1, and the data is not correctly discriminated. Therefore, in order to adjust the interpolation parameter in the direction in which the phase advances, the interpolation parameter (x) is calculated so as to obtain the signal waveform of FIG. 4C and fed back to the sample hold circuit 30. Similarly, in FIG. 4B, the data phase is advanced with respect to the center (EC), and the data discrimination is d1 = 0, d2 = 1, d3 = 1, and the data is not correctly discriminated. Therefore, in order to adjust the interpolation parameter in the direction in which the phase is delayed, the interpolation parameter (x) is calculated so as to obtain the signal waveform of FIG. 4C and fed back to the sample hold circuit 30.

  FIG. 5 is a diagram illustrating a detailed configuration of the receiving circuit according to the first embodiment. 5A shows the configuration of the sample and hold circuit 30, and FIG. 5B shows the detailed configuration of the variable capacitor (capacitor bank CB). The same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted. A differential plus signal Vinp and a differential minus signal Vinn are input to the gm cell 32. An output terminal on the differential plus signal Vinp side of the gm cell 32 is a node N1, and an output terminal on the differential minus signal Vinn side is a node N2. Sampling switches SWs0 and SWS1 are connected in parallel to the node N1, and variable capacitors C0 and C1 are connected in series to these switches. A reset switch SWr0 (SWr1) is connected between a node between the sampling switch SWs0 (SWs1) and the variable capacitor C0 (C1) and the power supply voltage Vdd. Sampling switches SWs2 and SWS3 are connected in parallel to the node N2, and variable capacitors C2 and C3 are connected in series to the sampling switches SWs2 and SWS3, respectively. A reset switch SWr2 (SWr3) is connected between the node between the sampling switch SWs2 (SWs3) and the variable capacitor C2 (C3) and the power supply voltage Vdd.

The sampling switches SWs0 to SWs3 may be sampling circuits for sampling received data at different timings. The variable capacitors C0 to C3 may be hold circuits that hold the respective data sampled by the sampling switches SWs0 to SWs3. Signals (S _n , S _n-1 , S _n-2 , S _n-3 ) having different timings are input from the sampling switches SWs0 to SWs3. S _n and S _n−1 are differential plus signals, and S _n−3 and S _n−2 are differential minus signals.

Control signals n0 to n3 are input to the variable capacitors C0 to C3 from an encoder 76 as a weighting circuit. The control signals n0 to n3 are signals for changing the capacitance values of the variable capacitors C0 to C3. By changing the capacitance values of the variable capacitors C0 to C3, the amount of charge that can be stored in C0 to C3 can be changed, and the input signals (S _{n to} S _n-3 ) can be weighted. As shown in FIG. 5B, the variable capacitors C0 to C3 include a plurality of capacitors C having a fixed capacitance connected in parallel between the input terminal IN and the output terminal OUT. Further, a switch SW is connected to each capacitor C in series. The switch SW is turned on / off by a control signal n (n0 to n3). When the switch SW corresponding to the control signal n is turned on, the combined capacitance of the capacitor C (the capacitance of the variable capacitors C0 to C3) changes.

  The output terminals of the variable capacitors C0 to C3 are connected to a common node N3. Thereby, the wiring on the output side of the variable capacitors C0 to C3 may be an output circuit that sums up and outputs the output data of the capacitors C0 to C3 as the hold circuit. The node N3 is connected to the ADC 50. A hold switch SWh is connected between the node N3 and the intermediate node N4 of the ADC 50 and the ground.

  Of the switches included in the sample hold circuit 30, the sampling switches SWs0 to SWs3 are driven by clock signals Clk_s [n] to Clk_s [n-3]. The reset switches SWr0 to SWr3 are each driven by a clock signal Clk_r, and the hold switches SWh0 to SWh3 are each driven by a clock signal Clk_h.

Here, a data equalization and interpolation algorithm will be described. In the equalization process, four input signals are selected two by two, and each of them multiplied by the parameter “y” or “y−1” for equalization is added to obtain two output data (however, “0 <y <1”). Specifically, the output data u1 and u2 can be obtained as follows.
_{u n = y (-S n-} 3) + (1-y) S n-1 ... ( Equation 1)
u _{n + 1} = y (−S _n−2 ) + (1−y) S _n (Expression 2)
Here, u _n and u _{n + 1} are the positive sides of the differential signal. Further, the subtraction of data (charge) can be realized by adding the operation minus signal.

Further, to the output data u _n and u _{n + 1} of the above sum to the combined over parameters for interpolation "x" or "x-1", respectively, to obtain the final output data (where "0 <X <1 "). Specifically, the output data d _n can be obtained as follows.
d _n = (1−x) u _n−1 + xu _n (Expression 3)

In the above example, equalization and interpolation processing are performed separately, but both can be performed at once. In this case, the output data d _n can be obtained as follows.
_{d n = x (1-y} ) S n + (1-x) (1-y) S n-1 -xyS n-2 - (1-x) yS n-3 ... ( Equation 4)
Here, when n0 = x (1-y), n1 = (1-x) (1-y), n2 = xy, and n3 = (1-x) y, Equation 4 is
_{d n = n0S n + n1S n} -1 -n2S n-2 -n3S n-3 ... ( Equation 5)
It can be expressed as. Note that n0 + n1 + n2 + n3 = 1. These parameters n0 to n3 correspond to n0 to n3 in FIG. 5, and the ratio of equalization and interpolation can be determined by the ratio of n0: n1: n2: n3.

  FIG. 6 is a diagram illustrating the operation of the receiving circuit according to the first embodiment. The signal waveforms of the clock signal Clk_s [n] to Clk_s [n-3] to the sampling switch, the clock signal Clk_r to the reset switch, and the clock signal Clk_h to the hold switch are shown. A clock signal ADC_samp supplied to the ADC 50 is also shown. The sample hold circuit 30 has four operation modes: reset, sampling, equalization / interpolation, and ADC latch.

First, in the reset mode, the clock signals Clk_r and Clk_h are at a high level, and the reset switches SWr0 to SWr3 and the hold switches SWh0 to SWh3 are turned on. As a result, the variable capacitors C0 to C3 are charged to a predetermined value (initial value). Here, assuming that the capacitance of each variable capacitor is C0 to C3, the accumulated charge is Q0 to Q3, and the voltage supplied from the reset switch SWr is Vdd, the charge amount to each variable capacitor is as follows.
Q0 = Vdd · C0 (Formula 6)
Q1 = Vdd · C1 (Expression 7)
Q2 = Vdd · C2 (Formula 8)
Q3 = Vdd · C3 (Formula 9)

…（式１０）
ここで、Ｖｘ０ｐにおけるｐは、電位がプラスであることを示す（以下の説明においても同じ。ｐの代わりにｎと記載した場合は電位がマイナスであることを示す）。 Next, in the sampling mode, the reset clock signal Clk_r becomes a low level, and the reset switches SWr0 to SWr3 are turned off. Further, the sampling clocks Clk_s [n-3] to Clk_s [n] are sequentially set to a high level for a certain period, and the sampling switches SWs0 to SWs3 are temporarily turned on. During this time, discharging from the capacitors C0 to C3 to the gm cell 32 is performed, and the potential of the node (Vx) on the input terminal side of the capacitors C0 to C3 decreases. For example, if the voltage of the differential minus signal supplied from the gm cell 32 is Vgm, and the time during which the sampling switch SWs0 is in the on state is t0 to t1, the potential of Vx0p is Vgmp due to the integration of the current expressed by the following equation. Decrease according to. Note that i _C0 is a current flowing from the variable capacitor C0.

... (Formula 10)
Here, p in Vx0p indicates that the potential is positive (the same applies in the following description. When n is described instead of p, it indicates that the potential is negative).

FIG. 7 is a diagram showing changes in the voltage. The potential of the node Vx0p maintains Vdd until time t0, the potential decreases following Vgmn during time t0 to t1, and is stable at Vx0p ′ after time t1. By changing the capacitance value of the variable capacitor C0, the final value of the voltage Vx0p ′ can be arbitrarily changed. Charges Q0 to Q3 remaining in the variable capacitors C0 to C3 when sampling is completed are expressed by the following equations.
Q0 = C0 · Vx0p ′ = Vdd · C0−C0 / Ctot∫Itot (t) · dt (Formula 11)
Q1 = C1 · Vx1p ′ = Vdd · C1−C1 / Ctot∫Itot (t) · dt (Formula 12)
Q2 = C2 · Vx2n ′ = Vdd · C2−C2 / Ctot∫Itot (t) · dt (Formula 13)
Q3 = C3 · Vx3n ′ = Vdd · C3−C3 / Ctot∫Itot (t) · dt (Formula 14)

Returning to FIG. 6 again, in the equalization / interpolation mode following the sampling mode, the reset clock signal Clk_r becomes high level, and the reset switches SWr0 to SWr3 are turned on. Further, the clock signal Clk_h becomes low level, and the hold switch SWh is turned off. Thus, charge accumulated in the variable capacitor C0~C3 are summed at node N3, the data d _n which equalization and interpolation has been completed is outputted. The addition of the charge is expressed by the following Expression 15, and the output voltage is expressed by the following Expression 16.
Qtot = Q0 + Q1 + Q2 + Q3 = Vdd · Ctot−Ctot / Ctot∫Itot (t) dt (Equation 15)
d _n = Vdd−Qtot / Ctot = 1 / Ctot · ∫Itot (t) dt (Expression 16)
The data d _n which is calculated here is the differential plus signal.

  In the second half of the equalization / interpolation mode, the clock signal ADC_samp supplied from the clock generation circuit 40 to the ADC 50 becomes high level, and the ADC latch mode in which the ADC 50 is driven is set. As a result, the analog data that has been equalized and interpolated is converted into digital data by the ADC 50.

  According to the receiving circuit according to the first embodiment, by changing the capacitance values of the variable capacitors C0 to C3 in the sample and hold circuit 30 based on equalization and interpolation parameters, Interpolation can be performed. Thereby, it is not necessary to separately provide a circuit for equalization and interpolation, and the circuit area can be reduced. Also, by performing equalization and interpolation in the previous stage of the ADC 50, the quantization noise of the digital signal can be reduced, so that the resolution required for the ADC 50 can be suppressed. As a result, the area and power consumption of the receiving circuit can be reduced. In addition, according to the electronic device including the receiving circuit, the area of the receiving circuit and the power consumption can be similarly reduced.

In the first embodiment, the parameter x used in the calculation of the interpolation (Equation 3) is determined by the parameter p (eye center phase) having information on the center phase of the eye pattern of the _dn data output to the digital side. And x = mod1 (2p). Specifically, in the case of “0 ≦ p <0.5”, the previous data d _n−1 is used as the interpolation data d _n . In the case of "0.5 ≦ p <1", the interpolation data _{d n} now output data _{d n-1} is used.
That is,
_{d n = S n-1 ·} p + S n-2 · p + S n-3 · p + S n-4 · p (0 ≦ p <0.5) ... ( Equation 17)
_{d n = S n · p +} S n-1 · p + S n-2 · p + S n-3 · p (0.5 ≦ p <1) ... ( Equation 18)
It becomes.

  FIG. 8 is a diagram showing a configuration of a sampling clock switching circuit. FIG. 8A shows a configuration when the sampling clock is switched, and FIG. 8B shows a configuration when the output of the sample hold unit 34 is switched. In FIG. 8A, the sampling clock is switched by the control signal P_control. When the interpolation parameter p is “0 ≦ p <0.5”, the clock signal is the previous signal “Clk_s [n−1], Clk_s [n−2], Clk_s [n−3], Clk_s”. [N-4] "is employed. When the interpolation parameter p is “0.5 ≦ p <1,” the clock signal is “Clk_s [n], Clk_s [n−1], Clk_s [n−2], Clk_s [n−3” which are the current signals. ] ”Is adopted.

In FIG. 8 (b), and _{d n} is the n th output of the sample hold unit 34, the _{d n-1} of the destination is (n-1) th output, is controlled by the control signal P-contorol. If interpolation parameter p is "0 ≦ p <0.5", _{d n} are connected to ADCn an n-th _{ADC, d n-1} are connected to ADCn-1 is a n-1 th ADC The When the interpolation parameter p is “0.5 ≦ p <1,” _dn is connected to the ADCn−1 that is the n−1th ADC.

  As described above, based on the value of the interpolation parameter p, a more accurate interpolation process can be performed by shifting the data operation by one clock as necessary.

  The second embodiment is an example in which equalization and interpolation calculations are performed using current.

  FIG. 9 is a diagram illustrating a detailed configuration of the receiving circuit according to the second embodiment. 9A shows the configuration of the sample and hold circuit 30, and FIG. 9B shows the detailed configuration of the current supply circuit (MOS bank MB) and the current control circuit 80. Unlike the first embodiment, the sample and hold circuit 30 according to the second embodiment does not include the gm cell 32. Instead, the differential positive signal Vinp is input to the node N1 connected to the input terminal, and the differential negative signal Vinn is input to the node N2. Sampling switches SWs0 and SWS1 are connected in parallel to the node N1, and hold switches SWh0 and SWh1 are connected in series to these switches. A reset switch SWr0 (SWr1) is connected between a node between the sampling switch SWs0 (SWs1) and the hold switch SWh0 (SWh1) and the ground. A capacitor Ch0 (Ch1) for holding a signal is connected between the node between the sampling switch SWs0 (SWs1) and the hold switch SWh0 (SWh1) and the ground.

  Further, sampling switches SWs2 and SWS3 are connected in parallel to the node N2, and hold switches SWh2 and SWh3 are connected in series to these switches. A reset switch SWr2 (SWr3) is connected between a node between the sampling switch SWs2 (SWs3) and the hold switch SWh2 (SWh3) and the ground. A capacitor Ch2 (Ch3) for holding a signal is connected between the node between the sampling switch SWs2 (SWs3) and the hold switch SWh2 (SWh3) and the ground.

  The outputs of the hold switches SWh0 to SWh3 are connected to MOS banks MB that may correspond to current supply circuits, respectively. The MOS bank MB includes pMOS transistors connected in parallel, and the outputs of the hold switches SWh0 to SWh3 are input to the gate terminals of the transistors. The drain side of the MOS bank MB is connected to the power supply line Vdd via the current control circuit 80. In addition, hold switches SWhd0 to SWhd3 are provided between a node between the hold switches SWh0 to SWh3 and the MOS bank MB and the power supply line Vdd. The outputs of the MOS banks MB merge at a common node N3 and are connected to an output terminal (data).

Control signals n0 to n3 are input to the current control circuit 80 from an encoder 76 as a weighting circuit. The control signals n0 to n3 are signals for changing the amount of current supplied by the current control circuit 80 (and the MOS bank MB). By changing the amount of current, the input signals (S _{n-3 to} S _n). ) Can be weighted. As shown in FIG. 9B, the MOS banks MB0 to MB3 include a plurality of switches SW connected in parallel between the power supply line Vdd and the output terminal Out. The switch SW is turned on / off by a control signal n (n0 to n3). When the switch SW corresponding to the control signal n is turned on, the amount of current supplied to the MOS bank MB changes.

  FIG. 10 is a diagram illustrating the operation of the receiving circuit according to the second embodiment. First, in the reset mode, the clock signals Clk_r and Clk_hd are at a high level, and the reset switches SWr0 to SWr3 and the hold switches SWhd0 to SWhd3 are turned on. Thereby, the capacitors C0 to C3 are charged to a predetermined value (initial value). Next, in the sampling mode, the reset clock signal Clk_r becomes a low level, and the reset switches SWr0 to SWr3 are turned off. Further, the sampling clocks Clk_s [n-3] to Clk_s [n] are sequentially set to a high level for a certain period, and the sampling switches SWs0 to SWs3 are temporarily turned on. During this time, the capacitors C0 to C3 are charged from the input terminal, and the potential of the node on the input terminal side of the capacitors C0 to C3 rises.

In the equalization / interpolation mode following the sampling mode, the clock signal Clk_h is at a high level, and the hold switches SWh0 to SWh3 are turned on. Further, the clock signal Clk_r and the clock signal Clk_hd become low level, and the reset switches SWr0 to SWr3 and the hold switches SWh0 to SWh3 are turned off. Thus, current supplied from the MOS bank MB0~MB3 is summed at node N3, the data _{d n} which equalization and interpolation has been completed is outputted. Thereafter, in the latter half of the equalization / interpolation mode, the clock signal ADC_samp supplied to the ADC 50 becomes a high level, and the ADC latch mode in which the ADC 50 is driven is set. Thereby, the signal data that has been equalized and interpolated is converted into digital data by the ADC 50.

  According to the electronic circuit according to the second embodiment, the area and power consumption of the receiving circuit can be reduced by performing equalization and interpolation in the previous stage of the ADC circuit as in the first embodiment.

  The third embodiment is an example in which equalization and interpolation calculations are performed using voltages.

  FIG. 11 is a diagram illustrating a detailed configuration of the receiving circuit according to the third embodiment. FIG. 11A shows the configuration of the sample and hold circuit 30, and FIG. 11B shows the detailed configuration of the variable capacitors C0 to C3. Unlike the first embodiment, the sample and hold circuit 30 according to the third embodiment does not include the gm cell 32. Instead, the differential positive signal Vinp is input to the node N1 connected to the input terminal, and the differential negative signal Vinn is input to the node N2. Sampling switches SWs0 and SWS1 are connected in parallel to the node N1. Further, a variable capacitor C0 and a hold switch SWhd0, and a variable capacitor C1 and a hold switch SWhd1 are connected in series to these switches. A reset switch SWr0 (SWr1) is connected between a node between the variable capacitor C0 (C1) and the hold switch SWh0 (SWh1) and the ground. A capacitor C0 (C1) for holding a signal is connected between the node between the sampling switch SWs0 (SWs1) and the hold switch SWh0 (SWh1) and the ground.

  Also, sampling switches SWs2 and SWS3 are connected in parallel to the node N2. Further, a variable capacitor C2 and a hold switch SWhd2, and a variable capacitor C3 and a hold switch SWhd3 are connected in series to these switches. A reset switch SWr2 (SWr3) is connected between a node between the variable capacitor C2 (C3) and the hold switch SWh2 (SWh3) and the ground. A capacitor C2 (C3) for holding a signal is connected between the node between the sampling switch SWs2 (SWs3) and the hold switch SWh2 (SWh3) and the ground.

  The outputs of the hold switches SWh0 to SWh3 merge at the common node N3 and are input to the negative phase input terminal of the differential amplifier 82 provided at the subsequent stage of the node N3. The positive phase input terminal of the differential amplifier 82 is grounded. The output terminal of the differential amplifier 82 is connected to the respective nodes between the variable capacitors C0 to C3 and the sampling switches SWs0 to SWs3 via the hold switches SWh0 to SWh3.

The configuration of the variable capacitors C0 to C3 is the same as that of the first embodiment. Control signals n0 to n3 are input to the variable capacitors C0 to C3 from an encoder 76 as a weighting circuit. The control signals n0 to n3 are signals for changing the capacitance values of the variable capacitors C0 to C3, and the input signals (S _{n-3 to} S _n ) are weighted by changing the capacitance values. Can do.

  FIG. 12 is a diagram illustrating the operation of the receiving circuit according to the third embodiment. First, in the reset mode, the clock signal Clk_r becomes high level, and the reset switches SWr0 to SWr3 are turned on. Thereby, the capacitors C0 to C3 are charged to a predetermined value (initial value). Next, in the sampling mode, the reset clock signal Clk_r becomes a low level, and the reset switches SWr0 to SWr3 are turned off. Further, the clock signal Clk_h becomes a high level, and the hold switches SWhd0 to SWhd3 are turned off. Further, the sampling clocks Clk_s [n-3] to Clk_s [n] are sequentially set to a high level for a certain period, and the sampling switches SWs0 to SWs3 are temporarily turned on. During this time, the capacitors C0 to C3 are charged from the input terminal, and the potential of the node on the input terminal side of the capacitors C0 to C3 rises.

  In the equalization / interpolation mode following the sampling mode, the clock signal Clk_hn is at a high level, and the hold switches SWh0 to SWh3 and SWhd0 to SWhd3 are turned on. As a result, the voltage on the input terminal side of the variable capacitors C0 to C3 is supplied to the output terminal of the differential amplifier 82 via the hold switches SWh0 to SWh3 that are turned on. At this time, since the outputs from the capacitors C0 to C3 merge at a common node, the weighted outputs (voltages) can be summed and output as in the first embodiment.

  According to the electronic circuit according to the third embodiment, the area and power consumption of the receiving circuit can be reduced by performing equalization and interpolation in the previous stage of the ADC circuit as in the first and second embodiments.

  The fourth embodiment is an example in which the sample and hold circuit is divided into a front stage and a rear stage.

  FIG. 13 is a diagram illustrating the configuration of the receiving circuit according to the fourth embodiment. Since the configuration of the equalization circuit 90 in the preceding stage is almost the same as that of the first embodiment (FIG. 5), the same reference numerals are given and detailed description is omitted. Unlike the first embodiment, the equalization circuit 90 is a 4-input 2-output circuit. For this reason, the output terminals of the variable capacitors C0 and C2 are connected to the common node N3, and the output terminals of C1 and C3 are connected to the common node N4. The node N3 is connected to the downstream gm cell 32b, and the node N4 is connected to the downstream gm cell 32c. A hold switch SWhb is provided between the node between the node N3 and the gm cell 32b and the ground, and a hold switch SWhc is provided between the node between the node N4 and the gm cell 32c and the ground. Is provided.

  The variable capacitor C4 is connected to the output terminal of the gm cell 32b, and the variable capacitor C5 is connected to the output terminal of the gm cell 32c. The output terminals of the variable capacitors C4 and C5 are connected to a common node N5. The potential of the node N5 becomes the final output of the sample hold circuit 30. A hold switch SWh is connected between the node N5 and the ground.

  The operation of the receiving circuit according to the fourth embodiment is the same as that described in the first embodiment. That is, the variable capacitors C0 to C3 (C4 to C5) are charged in the reset mode, and the charges charged in the sampling mode are discharged to the gm cells 32a (32b and 32c). In the equalization / interpolation mode, the electric charges stored in the variable capacitors C0 to C3 (C4 to C5) are weighted, synthesized, and output.

  Here, in the receiving circuit according to the fourth embodiment, the control signal input to the variable capacitors C0 to C5 is different from that of the first embodiment. That is, in the fourth embodiment, “y−1” is set to the variable capacitors C0 and C1, “y” is set to the variable capacitors C2 and C3, “x” is set to the variable capacitor C4, and “1-x” is set to the variable capacitor C5. Enter each. As a result, the equalization circuit 90, which is the front part of the reception circuit, performs only the equalization processing shown in Expressions 1 and 2, and the interpolation circuit 92, which is the subsequent part of the reception circuit, performs the interpolation shown in Expression 3. Only processing is performed.

  According to the electronic circuit according to the fourth embodiment, the area and power consumption of the receiving circuit can be reduced by performing equalization and interpolation in the previous stage of the ADC circuit as in the first and second embodiments. Even when current is used for equalization / interpolation calculation (Example 2) or when voltage is used (Example 3), the sample-and-hold circuit 30 is arranged in the front and rear stages as in Example 4. Division, equalization and interpolation may be performed separately.

In connection with the embodiment described above, the following supplementary notes are disclosed.
(Appendix 1)
A plurality of sampling circuits that sample received data at different timings, a plurality of hold circuits that hold the respective data sampled by the plurality of sampling circuits, and outputs from the plurality of hold circuits, A parameter calculation circuit for calculating a parameter for determining the degree of equalization and interpolation; a weighting circuit for weighting each output of the plurality of hold circuits based on the parameter calculated by the parameter calculation circuit; An output circuit for combining and outputting the output data of the hold circuit weighted by the weighting circuit;
(Appendix 2)
The hold circuit includes a variable capacitor connected between an input terminal and an output terminal of the hold circuit, and the weighting circuit calculates a capacitance value of the variable capacitor based on a parameter calculated by the parameter calculation circuit. The receiving circuit according to appendix 1, wherein the receiving circuit is changed.
(Appendix 3)
The receiving circuit according to claim 2, further comprising a differential amplifier connected to a subsequent stage of the hold circuit, wherein an output terminal of the differential amplifier is connected to a node preceding the variable capacitor.
(Appendix 4)
The hold circuit has one end connected to the input terminal of the hold circuit, the other end connected to the first power supply, a gate connected to the input terminal of the hold circuit, and one of the source or drain being the hold A transistor connected to an output terminal of the circuit and the other connected to a second power supply, and the weighting circuit is supplied from the second power supply to the transistor based on a parameter calculated by the parameter calculation circuit The receiving circuit according to appendix 1, wherein the amount of current is changed.
(Appendix 5)
An electronic apparatus comprising: the receiving circuit according to any one of appendices 1 to 4; and an analog-digital conversion circuit connected to a subsequent stage of the receiving circuit.
(Appendix 6)
The receiving circuit according to claim 1, wherein the weighting of the output of the hold circuit is performed by any one of charge, current, and voltage.
(Appendix 7)
The plurality of sampling circuits are each input with a differential plus signal and a differential minus signal, the output of the sampling circuit to which the differential plus signal is inputted, and the sampling circuit to which the differential minus signal is inputted The receiving circuit according to appendix 1, wherein the subtraction of data is made possible by adding to the output.
(Appendix 8)
The receiving circuit according to appendix 1, further comprising switching means for changing at least a sampling clock used in the sampling circuit based on an interpolation parameter indicating a position of data to be interpolated.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 CPU
20 High-speed input / output circuit 30 Sample hold circuit 32 gm cell 34 Sample hold unit 40 Clock generation circuit 50 Analog-digital conversion circuit (ADC)
60 Digital Signal Processing Circuit 70 Equalization Control Circuit 72 Phase Detection Circuit 74 Filter 76 Encoder 80 Current Control Circuit 82 Differential Amplifier SWs Sampling Switch SWr Reset Switch SWh Hold Switch C Capacitor MB MOS Bank

Claims (5)

A plurality of sampling circuits for sampling received data at different timings;
A plurality of hold circuits for holding the respective data sampled by the plurality of sampling circuits;
A parameter calculation circuit that calculates a parameter for determining the degree of equalization and interpolation of the input signal based on outputs from the plurality of hold circuits;
A weighting circuit for weighting each output of the plurality of hold circuits based on the parameters calculated by the parameter calculation circuit;
An output circuit for combining and outputting the output data of the hold circuit weighted by the weighting circuit;
A receiving circuit comprising: The hold circuit includes a variable capacitor connected between an input terminal and an output terminal of the hold circuit;
The receiving circuit according to claim 1, wherein the weighting circuit changes a capacitance value of the variable capacitor based on the parameter calculated by the parameter calculation circuit. A differential amplifier connected to the subsequent stage of the hold circuit;
The receiving circuit according to claim 2, wherein an output terminal of the differential amplifier is connected to a preceding node of the variable capacitor. The hold circuit is
A capacitor having one end connected to the input terminal of the hold circuit and the other end connected to a first power source;
A transistor having a gate connected to an input terminal of the hold circuit, one of a source and a drain connected to an output terminal of the hold circuit, and the other connected to a second power source;
The receiving circuit according to claim 1, wherein the weighting circuit changes the amount of current supplied from the second power source to the transistor based on the parameter calculated by the parameter calculation circuit. A receiving circuit according to any one of claims 1 to 4,
An electronic apparatus comprising: an analog-digital conversion circuit connected to a subsequent stage of the receiving circuit.

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