JPH0278267A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve a circuit device of this design in the degree of integration by a method wherein a collector and an emitter of a forward type and a reverse type bipolar transistor formed on a protrudent island region in a depthwise direction are formed into one piece. CONSTITUTION:An output stage of an Active Pull Down Non threshold Logic used in a large scale computer is constituted as follows: a forward type pull down bipolar transistor(Tr) Q6 is provided to a protrudent island region 5; the island region 5 is formed of an n<->-type epitaxial layer 2, and TrQ6 has such a longitudinal structure that an n-type emitter E, a p-type base B, and an n-type collector C are deposited in a depthwise direction of the island region 5; a reverse type emitter follower bipolar TrQ5 is structured in such a manner that an n-type collector C, a p-type base B, and an n-type emitter E are successively formed in a depthwise direction of the island region 5; and the collector or TrQ5 and the emitter of TrQ6 are formed into one piece. By this setup, an element isolating region can be dispensed with, so that the degree of integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a bipolar transistor.

[Conventional technology]

NT, which excels in high speed and low power consumption, is used as the logic circuit of the calculation part of the central processing unit (CPU) of large computers.
An L (Non-rushhold Logjc) circuit is used. This NTL circuit also has functions such as an OR/NOR gate circuit. The output stage of the NTL circuit is composed of an inverter circuit consisting of an emitter follower type bipolar transistor and a resistance element connected in series to the emitter region of the bipolar transistor. In order to increase the speed of the NTL circuit, a bias current is constantly passed through the emitter follower bipolar transistor and the resistance element regardless of whether the circuit is ON or OFF. This bias current causes increased power consumption.

Although it is not a publicly known technology, the present inventor has developed an APD (Active Dual-Operating Device) in which the output stage inverter circuit is configured with a pull-down bipolar transistor instead of a resistor element.
wn) type NTL circuit is currently being developed.

The collector region of the pull-down bipolar transistor is electrically connected to the emitter region of the emitter follower bipolar transistor via a signal wiring. AP
In the D-type NTL circuit, no bias current flows when the pull-down bipolar transistor is in OFF operation, so the NTL
It has the feature that it can achieve lower power consumption than the TL circuit. Further, since the pull-down bipolar transistor is an active element in the APD type NTL circuit, the pull-down operation is faster than that of a resistor element which is a passive element, and the circuit can be operated at a higher speed.

Regarding NTL circuits, for example, Science Forum Co., Ltd., VLSI Device Handbook, 1930
Published on November 28, 1998, pages 169 to 170.

[Problem to be solved by the invention]

In the APD type NTL circuit described above, since the number of bipolar transistors increases, the element area and element isolation area increase, resulting in a problem that the degree of integration of the semiconductor integrated circuit device decreases.

An object of the present invention is to provide a technique that can improve the degree of integration of a semiconductor integrated circuit device having bipolar transistors.

Another object of the present invention is to improve the frequency characteristics of the APD NTL circuit and reduce the area of the APD NTL circuit to improve the degree of integration in a semiconductor integrated circuit device having an APD NTL circuit. The goal is to provide technology that enables

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

A semiconductor integrated circuit device having an APD type NTL circuit, wherein a pull-down bipolar transistor of the APD type NTL circuit is arranged in an emitter region from a main surface side of a protruding island region toward its depth.

The emitter follower type bipolar transistor is constructed of a forward type in which the base region and the collector region are formed sequentially, and the collector region, base region, and emitter region are formed from the main surface side of the protruding island region in the depth direction. The collector region of the pull-down bipolar transistor and the emitter region of the emitter follower bipolar transistor are integrally formed.

[For production]

According to the above-mentioned means, the effective areas of the emitter region and the collector region can be formed to be approximately equal by the protruding island regions, so that the high frequency characteristics of the reverse emitter follower bipolar transistor can be changed to the forward type. This makes it possible to make the device substantially equivalent to that of a pull-down bipolar transistor, and also to eliminate the element isolation region between the pull-down bipolar transistor and the emitter follower bipolar transistor.

The degree of integration can be improved by a corresponding amount.

Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having an APD type NTL circuit.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

An APD type NTL circuit, which is an embodiment of the present invention, is shown in Figure 2 (
(equivalent circuit diagram).

As shown in FIG. 2, the APD type NTL circuit has six n
pn type bipolar transistors Q1-Q,.

It is composed of four resistance elements R□ to R4 and capacitance elements Cp and Cs. The bipolar transistor Qs is an emitter follower type bipolar transistor. Bipolar transistor Q6 is a pull-down type bipolar transistor.

Each of the bipolar transistors Q, Q, arranged in the first stage of the APD type NTL circuit receives the output signals V□ and ■2 of the previous stage logic circuit in its base region, and determines the output level of this circuit. It is configured as follows. In other words, the APD type NTL circuit also has an OR/NOR gate circuit function.

The bipolar transistor Q3 arranged in the middle stage is controlled by the base potential V, and is configured to apply an appropriate bias to the pull-down bipolar transistor Q6. Bipolar transistor Q4 is controlled by base potential V, and is configured to clamp the low level of the output signal of this circuit. An emitter follower type bipolar transistor Q and a pull-down type bipolar transistor Q5 arranged in the output stage constitute an inverter circuit. The output of this inverter circuit, that is, the emitter region of the emitter follower type bipolar transistor Q, and the pull-down type bipolar transistor Q6
Each of the collector regions is electrically connected to an output signal terminal V
Connected to out.

The resistive element R□ is configured to define a logic amplitude. Resistive element R2 is configured to define a circuit current. Resistance element R3 is a bias resistance for pull-down bipolar transistor Q6. Resistance element R1
is configured to determine the high level of the output signal of the emitter follower type bipolar transistor Q5.

The capacitive element Cs is a speed-up capacitor.

Capacitive element Cp is configured to improve pulse response.

In FIG. 2, v6 is the terminal voltage and GND is the ground potential.

The emitter follower type bipolar transistor Q8 and the pulldown type bipolar transistor Q, which are the output stage of this APD type NTL circuit, are each constructed as shown in FIG. 1 (a sectional view of the main part).

Each semiconductor element of this APD type NTL circuit is constructed on the main surface of a p-type semiconductor substrate 1 made of single crystal silicon.

The pull-down bipolar transistor Q6 is provided in a protruding island region (convex active region) 5 formed on the main surface of the semiconductor substrate 1. The protruding island region 5 is composed of a Go-type epitaxial layer 2 grown on the main surface of the semiconductor substrate 1. This protruding island region 5 is formed in the epitaxial layer 2.
It can be formed by removing the non-active region portion of the inactive region by mesa etching. The pull-down bipolar transistor Q has an n-type emitter region E, a p-type base region B, and
It has a vertical structure in which n-type collector regions C are sequentially formed.

The n-type collector region C of the pull-down bipolar transistor Q is composed of an epitaxial layer 2 and a buried go-type semiconductor region (buried layer) 3.

The buried go-type semiconductor region 3 is provided between the semiconductor substrate 1 and the epitaxial layer 2 and is electrically connected to the epitaxial layer 2 . In the n-type collector region C, the buried n°-type semiconductor region 3 is extended to a different position from the protruding island region 5, and the collector potential is raised from the surface of the semiconductor substrate 1 by the wiring 10. Size: m10
is formed of, for example, an aluminum film or an aluminum alloy film.

The p-type base region B is composed of a p-type semiconductor region 8 provided on the main surface of the epitaxial layer 2.

A wiring 10 is connected to the P-type base region B through a base extraction electrode 7 that is extracted from the side wall (graft base region) of the protruding island region 5 in a self-aligned manner. The base extraction electrode 7 is formed of, for example, a polycrystalline silicon film doped with p-type impurities.

The n-type emitter region E is composed of an n'-type semiconductor region 9 provided on the main surface of the p-type semiconductor region 8.

A wiring 10 is connected to the n-type=mitter region E.

As described above, this pull-down bipolar transistor QG is a self-aligned transistor in which the base extraction electrode 7 is connected to the p-type base region B on the side wall of the protruding island region 5 in a self-aligned manner. This is the so-called S I COS (S
ide Wall Ba5e Contact 5tr
It is a forward type structure.

The pull-down bipolar transistor Q.

is surrounded by an element isolation region and is electrically isolated from other semiconductor elements. The element isolation region is composed of a semiconductor substrate 1, a p° type semiconductor region 4, and an element isolation insulating film 6.

The emitter follower type bipolar transistor Q is provided in the protruding island region S similarly to the pulldown type bipolar transistor Q. The emitter follower type bipolar transistor Qs has a vertical structure in which an n-type collector region C, a p-type base region B, and an n-type emitter region E are sequentially formed from the main surface of the protruding island region 5 in the depth direction thereof. has been done.

The n-type emitter region C of this emitter follower type bipolar transistor Q is formed by the epitaxial layer 2 and the buried type n-type emitter region C.
It is composed of a type semiconductor region 3.

In other words, since the n-type emitter region E is electrically connected to the n-type collector region C of the pull-down bipolar transistor Q6, they can be configured integrally (they cannot be shared) as shown in FIG. can). The raising of the emitter potential of the n-type emitter region E is shared with the raising of the collector potential of the pull-down bipolar transistor Q6. The p-type base region B is a P-type semiconductor region 8 provided on the main surface of the epitaxial layer 2.
It is made up of. This p-type base region B is provided with a base extraction electrode 7 in a self-aligned manner on the side wall of the protruding island region 5.
is connected. The n-type collector region C is provided on the main surface of the p-type semiconductor region 8.

It is made up of a type semiconductor region 9. n-type collector region C
is connected to @io.

This emitter-follower type bipolar transistor Q is similarly configured with a 5ICOS structure, and is configured in a direction opposite to that of the pull-down type bipolar transistor Q6. Since the planar size of each of the n-type emitter region E, P-type base region B, and n-type collector region C of the 5ICO8 structure is approximately defined by the planar size of the protruding island region 5, n
The pn junction area, that is, the operational effective area of each of the emitter region E-p type base region B and the n-type collector region CP-type base region B is a gap or the like. In other words, the high frequency characteristics of the emitter follower type bipolar transistor Q in the reverse direction are similar to those of the forward pulldown type bipolar transistor Q6, so even if the emitter follower type bipolar transistor Q is configured in the reverse direction. Sufficient high frequency characteristics can be obtained.

In this semiconductor integrated circuit device having an APD type NTL circuit, the pull-down bipolar transistor Q6 of the APD type NTL circuit is an n-type transistor extending from the main surface side of the protruding island region 5 in the depth direction thereof. emitter region E,
An emitter-follower type bipolar transistor Q, which is a forward type in which a P-type base region B and an n-type collector region C are sequentially formed, extends from the main surface side of the protruding island region 5 in the depth direction thereof. The n-type collector region C of the pull-down type bipolar transistor Q6 and the emitter follower type bipolar transistor Q are constituted of a reverse direction type in which an n-type collector region C, a P-type base region B, and an n-type emitter region E are formed in sequence.

(buried n-type emitter region E) is integrated with the n-type emitter region E (buried type
By integrally configuring the ゛-type semiconductor region 3), the effective area of each of the n-type emitter region E and the n-type collector region E can be formed between the paths etc. by the protruding island region 5. Directional emitter follower bipolar transistor Q.

The high-frequency characteristics of the forward-direction pull-down bipolar transistor Q5 can be made similar to that of the forward-direction pull-down bipolar transistor Q5, and the element isolation region (4 and 6) between the pull-down bipolar transistor Q and the emitter follower bipolar transistor Q ), the degree of integration can be improved by a corresponding amount.

Furthermore, the pull-down bipolar transistor QG
The collector potential pulling region of the emitter follower type bipolar transistor Q5 and the emitter potential pulling region of the emitter follower bipolar transistor Q5 can be integrally configured (shared), so that the region corresponds to the element isolation region between the two and one of the regions. Therefore, the degree of integration can be improved.

In addition, an emitter follower type bipolar transistor Q,
and the total parasitic capacitance Ct− (semiconductor substrate 1−embedded type n°
Since the capacitance between the type semiconductor regions 3 can be reduced, the operation speed of the APD type NTL circuit can be increased.

In the above, the invention made by the present inventor has been specifically explained based on the above embodiments, but one aspect of the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various changes can be made without departing from the spirit thereof.

For example, the present invention is not limited to APD type NTL circuits,
The present invention can be widely applied to semiconductor integrated circuit devices having a circuit in which the emitter region of a bipolar transistor and the collector region of another bipolar transistor are electrically connected.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The degree of integration of a semiconductor integrated circuit device having bipolar transistors can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of an APD type NTL circuit built into a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the APD type NTL circuit. In the figure, R1-R4...resistive element, Cs, cp...capacitive element, Q~Q6...bipolar transistor, E...
・Emitter region, B... Base region, C... Collector region, 2... Epitaxial layer, 3, 4, 8.9.
. . . Semiconductor region, 5 . . . Projected island region, 6 . . .

Claims (1)

[Claims] 1. Collector region of first bipolar transistor and second bipolar transistor
A semiconductor integrated circuit device in which an emitter region of a bipolar transistor is electrically connected, wherein the first bipolar transistor has an emitter region, a base region, The second
The bipolar transistor is constructed of a reverse type in which a collector region, a base region, and an emitter region are formed sequentially from the main surface side of the protruding island region in the depth direction thereof, and the collector region of the first bipolar transistor and A semiconductor integrated circuit device characterized in that an emitter region of a second bipolar transistor is configured integrally with the emitter region of the second bipolar transistor. 2. The first and second bipolar transistors constitute an output stage of an active pull-down NTL circuit, and the first bipolar transistor is a pull-down transistor;
2. The semiconductor integrated circuit device according to claim 1, wherein the second bipolar transistors constitute emitter follower transistors. 3. Each of the first and second bipolar transistors is S
The semiconductor integrated circuit device according to claim 1 or 2, characterized in that it is configured with an ICOS structure.